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Preliminary User's Manual
V850ES/KE2
32-Bit Single-Chip Microcontroller Hardware
PD70F3726
Document No. U17705EJ1V0UD00 (1st edition) Date Published November 2005 N CP(K) 2005 Printed in Japan
[MEMO]
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Preliminary User's Manual U17705EJ1V0UD
NOTES FOR CMOS DEVICES
1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.
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Caution: PD70F3726 uses SuperFlash(R) technology licensed from Silicon Storage Technology, Inc. MINICUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany. EEPROM is a trademark of NEC Electronics Corporation. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan.
* The information contained in this document is being issued in advance of the production cycle for the product. The parameters for the product may change before final production or NEC Electronics Corporation, at its own discretion, may withdraw the product prior to its production. * Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics products depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M5D 02. 11-1
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Preliminary User's Manual U17705EJ1V0UD
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html
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* Sucursal en Espana
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Milton Keynes, UK Tel: 01908-691-133
J05.6
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PREFACE
Readers
This manual is intended for users who wish to understand the functions of the V850ES/KE2 and design application systems using the V850ES/KE2.
Purpose
This manual is intended to give users an understanding of the hardware functions of the V850ES/KE2 shown in the Organization below.
Organization
This manual is divided into two parts: Hardware (this manual) and Architecture (V850ES Architecture User's Manual). Hardware * Pin functions * CPU function * On-chip peripheral functions * Flash memory programming * Electrical specifications Architecture * Data types * Register set * Instruction format and instruction set * Interrupts and exceptions * Pipeline operation
How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. To find the details of a register where the name is known Refer to APPENDIX B REGISTER INDEX. To understand the details of an instruction function Refer to the V850ES Architecture User's Manual. Register format The name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defined as a reserved word in the device file. To understand the overall functions of the V850ES/KE2 Read this manual according to the CONTENTS. To know the electrical specifications of the V850ES/KE2 Refer to CHAPTER 23 ELECTRICAL SPECIFICATIONS (TARGET). The "yyy bit of the xxx register" is described as the "xxx.yyy bit" in this manual. Note with caution that even if "xxx.yyy" is described as is in a program, however, the compiler/assembler cannot recognize it correctly.
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Preliminary User's Manual U17705EJ1V0UD
Conventions
Data significance: Memory map address: Note: Caution: Remark: Numeric representation:
Higher digits on the left and lower digits on the right Higher addresses on the top and lower addresses on the bottom Footnote for item marked with Note in the text Information requiring particular attention Supplementary information Binary Decimal Hexadecimal K (kilo): G (giga): ... xxxx or xxxxB ... xxxx ... xxxxH
Active low representation: xxx (overscore over pin or signal name)
Prefix indicating power of 2 (address space, memory capacity): 210 = 1,024 230 = 1,0243 M (mega): 220 = 1,0242
Related Documents
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/KE2
Document Name V850ES Architecture User's Manual V850ES/KE2 Hardware User's Manual Document No. U15943E This manual
Documents related to development tools (user's manuals)
Document Name CA850 Ver. 3.00 C Compiler Package Operation C Language Assembly Language Link Directives PM+ Ver. 6.00 Project Manager ID850QB Ver. 3.10 Integrated Debugger SM850 Ver. 2.50 System Simulator SM850 Ver. 2.00 or Later System Simulator Operation Operation External Part User Open Interface Specification RX850 Ver. 3.20 or Later Real-Time OS Basics Installation Technical Task Debugger RX850 Pro Ver. 3.20 Real-Time OS Basics Installation Technical Task Debugger AZ850 Ver. 3.30 System Performance Analyzer PG-FP4 Flash Memory Programmer U13430E U17419E U13431E U17420E U13773E U17421E U13772E U17422E U17423E U15260E Document No. U17293E U17291E U17292E U17294E U17178E U17435E U16218E U14873E
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CONTENTS
CHAPTER 1 INTRODUCTION..................................................................................................................16 1.1 1.2 1.3 1.4 1.5 1.6 1.7 V850ES/Kx2 Product Lineup ..................................................................................................... 16 Features ...................................................................................................................................... 17 Applications................................................................................................................................ 18 Ordering Information ................................................................................................................. 18 Pin Configuration (Top View).................................................................................................... 19 Function Block Configuration................................................................................................... 21 Overview of Functions............................................................................................................... 24
CHAPTER 2 PIN FUNCTIONS ................................................................................................................25 2.1 2.2 2.3 List of Pin Functions.................................................................................................................. 25 Pin I/O Circuits and Recommended Connection of Unused Pins......................................... 29 Pin I/O Circuits............................................................................................................................ 31
CHAPTER 3 CPU FUNCTIONS...............................................................................................................33 3.1 3.2 Features ...................................................................................................................................... 33 CPU Register Set........................................................................................................................ 34
3.2.1 3.2.2 Program register set ...................................................................................................................... 35 System register set ........................................................................................................................ 36
3.3 3.4
Operating Modes ........................................................................................................................ 42 Address Space ........................................................................................................................... 43
3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 CPU address space ....................................................................................................................... 43 Wraparound of CPU address space .............................................................................................. 44 Memory map.................................................................................................................................. 45 Areas ............................................................................................................................................. 47 Recommended use of address space ........................................................................................... 49 Peripheral I/O registers .................................................................................................................. 51 Special registers ............................................................................................................................ 57 Cautions......................................................................................................................................... 60
CHAPTER 4 PORT FUNCTIONS ............................................................................................................63 4.1 4.2 4.3 Features ...................................................................................................................................... 63 Basic Port Configuration........................................................................................................... 63 Port Configuration...................................................................................................................... 64
4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 Port 0 ............................................................................................................................................. 70 Port 3 ............................................................................................................................................. 72 Port 4 ............................................................................................................................................. 78 Port 5 ............................................................................................................................................. 80 Port 7 ............................................................................................................................................. 83 Port 9 ............................................................................................................................................. 84 Port CM.......................................................................................................................................... 90 Port DL........................................................................................................................................... 92
4.4 8
Block Diagrams .......................................................................................................................... 94
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4.5 4.6
Port Register Setting When Alternate Function Is Used ..................................................... 112 Cautions.................................................................................................................................... 116
4.6.1 4.6.2 Cautions on bit manipulation instruction for port n register (Pn) ...................................................116 Hysteresis characteristics .............................................................................................................117
CHAPTER 5 CLOCK GENERATION FUNCTION ...............................................................................118 5.1 5.2 5.3 5.4 Overview ................................................................................................................................... 118 Configuration............................................................................................................................ 119 Registers................................................................................................................................... 121 Operation .................................................................................................................................. 125
5.4.1 5.4.2 5.4.3 Operation of each clock ................................................................................................................125 Clock output function ....................................................................................................................125 External clock input function .........................................................................................................125 Overview ......................................................................................................................................126 Register ........................................................................................................................................126 Usage ...........................................................................................................................................127
5.5
PLL Function ............................................................................................................................ 126
5.5.1 5.5.2 5.5.3
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) .................................................................128 6.1 6.2 6.3 6.4 6.5 Overview ................................................................................................................................... 128 Functions .................................................................................................................................. 128 Configuration............................................................................................................................ 129 Registers................................................................................................................................... 131 Operation .................................................................................................................................. 142
6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.5.6 6.5.7 6.5.8 Interval timer mode (TP0MD2 to TP0MD0 bits = 000)..................................................................143 External event count mode (TP0MD2 to TP0MD0 bits = 001)......................................................153 External trigger pulse output mode (TP0MD2 to TP0MD0 bits = 010)..........................................161 One-shot pulse output mode (TP0MD2 to TP0MD0 bits = 011) ...................................................173 PWM output mode (TP0MD2 to TP0MD0 bits = 100)...................................................................180 Free-running timer mode (TP0MD2 to TP0MD0 bits = 101) .........................................................189 Pulse width measurement mode (TP0MD2 to TP0MD0 bits = 110) .............................................206 Timer output operations................................................................................................................212
6.6 6.7
Eliminating Noise on Capture Trigger Input Pin (TIP0a)...................................................... 213 Cautions.................................................................................................................................... 215
CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0..............................................................................216 7.1 7.2 7.3 7.4 Functions .................................................................................................................................. 216 Configuration............................................................................................................................ 217 Registers................................................................................................................................... 222 Operation .................................................................................................................................. 229
7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 Interval timer operation.................................................................................................................229 Square wave output operation......................................................................................................232 External event counter operation..................................................................................................235 Operation in clear & start mode entered by TI010 pin valid edge input ........................................238 Free-running timer operation ........................................................................................................254 PPG output operation ...................................................................................................................263 One-shot pulse output operation ..................................................................................................266
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7.4.8
Pulse width measurement operation............................................................................................ 271 Rewriting CR011 register during TM01 operation........................................................................ 279 Setting LVS01 and LVR01 bits .................................................................................................... 279
7.5
Special Use of TM01................................................................................................................. 279
7.5.1 7.5.2
7.6
Cautions .................................................................................................................................... 281
CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 ............................................................................... 285 8.1 8.2 8.3 8.4 Functions .................................................................................................................................. 285 Configuration............................................................................................................................ 286 Registers ................................................................................................................................... 289 Operation .................................................................................................................................. 292
8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 8.4.8 Operation as interval timer........................................................................................................... 292 Operation as external event counter ............................................................................................ 294 Square-wave output operation..................................................................................................... 295 8-bit PWM output operation ......................................................................................................... 297 Operation as interval timer (16 bits) ............................................................................................. 300 Operation as external event counter (16 bits) .............................................................................. 302 Square-wave output operation (16-bit resolution) ........................................................................ 303 Cautions....................................................................................................................................... 304
CHAPTER 9 8-BIT TIMER H ............................................................................................................... 305 9.1 9.2 9.3 9.4 Functions .................................................................................................................................. 305 Configuration............................................................................................................................ 305 Registers ................................................................................................................................... 308 Operation .................................................................................................................................. 312
9.4.1 9.4.2 9.4.3 Operation as interval timer/square wave output........................................................................... 312 PWM output mode operation ....................................................................................................... 315 Carrier generator mode operation................................................................................................ 321
CHAPTER 10 INTERVAL TIMER, WATCH TIMER ........................................................................... 328 10.1 Interval Timer BRG................................................................................................................... 328
10.1.1 Functions ..................................................................................................................................... 328 10.1.2 Configuration ............................................................................................................................... 328 10.1.3 Registers...................................................................................................................................... 330 10.1.4 Operation ..................................................................................................................................... 332
10.2
Watch Timer.............................................................................................................................. 333
10.2.1 Functions ..................................................................................................................................... 333 10.2.2 Configuration ............................................................................................................................... 333 10.2.3 Registers...................................................................................................................................... 334 10.2.4 Operation ..................................................................................................................................... 336
10.3
Cautions .................................................................................................................................... 337
CHAPTER 11 WATCHDOG TIMER FUNCTIONS .............................................................................. 339 11.1 Watchdog Timer 1 .................................................................................................................... 339
11.1.1 Functions ..................................................................................................................................... 339 11.1.2 Configuration ............................................................................................................................... 341
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11.1.3 Registers ......................................................................................................................................341 11.1.4 Operation......................................................................................................................................343
11.2
Watchdog Timer 2.................................................................................................................... 345
11.2.1 Functions ......................................................................................................................................345 11.2.2 Configuration ................................................................................................................................346 11.2.3 Registers ......................................................................................................................................346 11.2.4 Operation......................................................................................................................................348
CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO)....................................................................349 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Function .................................................................................................................................... 349 Configuration............................................................................................................................ 350 Registers................................................................................................................................... 351 Operation .................................................................................................................................. 353 Usage ........................................................................................................................................ 354 Cautions.................................................................................................................................... 354 Security Function..................................................................................................................... 355
CHAPTER 13 A/D CONVERTER ..........................................................................................................357 13.1 13.2 13.3 13.4 13.5 Overview ................................................................................................................................... 357 Functions .................................................................................................................................. 357 Configuration............................................................................................................................ 358 Registers................................................................................................................................... 360 Operation .................................................................................................................................. 368
13.5.1 Basic operation.............................................................................................................................368 13.5.2 Trigger modes ..............................................................................................................................369 13.5.3 Operation modes ..........................................................................................................................370 13.5.4 Power fail detection function.........................................................................................................373 13.5.5 Setting method .............................................................................................................................374
13.6 13.7
Cautions.................................................................................................................................... 375 How to Read A/D Converter Characteristics Table .............................................................. 381
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) .....................................................385 14.1 14.2 14.3 14.4 14.5 Features .................................................................................................................................... 385 Configuration............................................................................................................................ 386 Registers................................................................................................................................... 388 Interrupt Requests ................................................................................................................... 394 Operation .................................................................................................................................. 395
14.5.1 14.5.2 Data format...................................................................................................................................395 Transmit operation........................................................................................................................396
14.5.3 Continuous transmission operation ..............................................................................................398 14.5.4 Receive operation.........................................................................................................................402 14.5.5 Reception error.............................................................................................................................403 14.5.6 Parity types and corresponding operation ....................................................................................405 14.5.7 Receive data noise filter ...............................................................................................................406
14.6
Dedicated Baud Rate Generator n (BRGn)............................................................................ 407
14.6.1 Baud rate generator n (BRGn) configuration ................................................................................407 14.6.2 Serial clock generation .................................................................................................................408
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14.6.3 Baud rate setting example ........................................................................................................... 411 14.6.4 Allowable baud rate range during reception................................................................................. 412 14.6.5 Transfer rate during continuous transmission .............................................................................. 414
14.7
Cautions .................................................................................................................................... 414
CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) ................................................................ 415 15.1 15.2 15.3 15.4 Features .................................................................................................................................... 415 Configuration............................................................................................................................ 416 Registers ................................................................................................................................... 419 Operation .................................................................................................................................. 428
15.4.1 Transmission/reception completion interrupt request signal (INTCSI0n) ..................................... 428 15.4.2 Single transfer mode.................................................................................................................... 430 15.4.3 Continuous transfer mode............................................................................................................ 433
15.5
Output Pins ............................................................................................................................... 441
CHAPTER 16 I2C BUS .......................................................................................................................... 442 16.1 16.2 16.3 16.4 16.5 Features .................................................................................................................................... 442 Configuration............................................................................................................................ 445 Registers ................................................................................................................................... 447 Functions .................................................................................................................................. 461
16.4.1 Pin configuration .......................................................................................................................... 461
I2C Bus Definitions and Control Methods .............................................................................. 462
16.5.1 Start condition.............................................................................................................................. 462 16.5.2 Addresses.................................................................................................................................... 463 16.5.3 Transfer direction specification .................................................................................................... 464 16.5.4 16.5.6 16.5.7 ACK ............................................................................................................................................. 465 Wait state..................................................................................................................................... 467 Wait state cancellation method .................................................................................................... 469 16.5.5 Stop condition .............................................................................................................................. 466
16.6
I2C Interrupt Request Signals (INTIIC0) .................................................................................. 470
16.6.1 Master device operation............................................................................................................... 471 16.6.2 Slave device operation (when receiving slave address data (address match))............................ 474 16.6.3 Slave device operation (when receiving extension code) ............................................................ 478 16.6.4 Operation without communication................................................................................................ 482 16.6.5 Arbitration loss operation (operation as slave after arbitration loss) ............................................ 483 16.6.6 Operation when arbitration loss occurs (no communication after arbitration loss) ....................... 485
16.7 16.8 16.9 16.10 16.11 16.12 16.13
Interrupt Request Signal (INTIIC0) Generation Timing and Wait Control........................... 492 Address Match Detection Method .......................................................................................... 493 Error Detection ......................................................................................................................... 493 Extension Code ........................................................................................................................ 494 Arbitration ................................................................................................................................. 495 Wakeup Function ..................................................................................................................... 496 Communication Reservation .................................................................................................. 497
16.13.1 When communication reservation function is enabled (IICF0.IICRSV0 bit = 0) ........................... 497 16.13.2 When communication reservation function is disabled (IICF0.IICRSV0 bit = 1) .......................... 500
16.14 Cautions .................................................................................................................................... 501 16.15 Communication Operations .................................................................................................... 502 12
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16.15.1 Master operation in single master system ....................................................................................503 16.15.2 Master operation in multimaster system .......................................................................................504 16.15.3 Slave operation.............................................................................................................................507
16.16 Timing of Data Communication.............................................................................................. 510 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION................................................517 17.1 17.2 Overview ................................................................................................................................... 517
17.1.1 Features .......................................................................................................................................517
Non-Maskable Interrupts......................................................................................................... 520
17.2.1 Operation......................................................................................................................................523 17.2.2 17.2.3 Restore .........................................................................................................................................524 NP flag..........................................................................................................................................525
17.3
Maskable Interrupts ................................................................................................................. 526
17.3.1 Operation......................................................................................................................................526 17.3.2 17.3.4 17.3.6 17.3.7 Restore .........................................................................................................................................528 Interrupt control register (xxlCn) ...................................................................................................533 In-service priority register (ISPR)..................................................................................................536 ID flag ...........................................................................................................................................537 17.3.3 Priorities of maskable interrupts ...................................................................................................529 17.3.5 Interrupt mask registers 0, 1, 3 (IMR0, IMR1, IMR3) ....................................................................535
17.3.8 Watchdog timer mode register 1 (WDTM1) ..................................................................................538
17.4
External Interrupt Request Input Pins (NMI, INTP0 to INTP7) ............................................. 539
17.4.1 Noise elimination ..........................................................................................................................539 17.4.2 Edge detection..............................................................................................................................541
17.5
Software Exceptions................................................................................................................ 545
17.5.1 Operation......................................................................................................................................545 17.5.2 17.5.3 Restore .........................................................................................................................................546 EP flag..........................................................................................................................................547 Illegal opcode ...............................................................................................................................548
17.6
Exception Trap ......................................................................................................................... 548
17.6.1 17.6.2 Debug trap....................................................................................................................................550
17.7 17.8 17.9 17.10
Multiple Interrupt Servicing Control ...................................................................................... 552 Interrupt Response Time......................................................................................................... 554 Periods in Which Interrupts Are Not Acknowledged by CPU ............................................. 555 Cautions.................................................................................................................................... 555
CHAPTER 18 KEY INTERRUPT FUNCTION ......................................................................................556 18.1 18.2 Function .................................................................................................................................... 556 Register..................................................................................................................................... 557
CHAPTER 19 STANDBY FUNCTION...................................................................................................558 19.1 19.2 19.3 Overview ................................................................................................................................... 558 Registers................................................................................................................................... 561 HALT Mode ............................................................................................................................... 564
19.3.1 Setting and operation status .........................................................................................................564 19.3.2 Releasing HALT mode .................................................................................................................564
19.4
IDLE Mode................................................................................................................................. 566
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19.4.1 Setting and operation status ........................................................................................................ 566 19.4.2 Releasing IDLE mode .................................................................................................................. 567
19.5
STOP Mode ............................................................................................................................... 569
19.5.1 Setting and operation status ........................................................................................................ 569 19.5.2 Releasing STOP mode ................................................................................................................ 570 19.5.3 Securing oscillation stabilization time when STOP mode is released .......................................... 572
19.6
Subclock Operation Mode....................................................................................................... 573
19.6.1 Setting and operation status ........................................................................................................ 573 19.6.2 Releasing subclock operation mode ............................................................................................ 573
19.7
Sub-IDLE Mode......................................................................................................................... 575
19.7.1 Setting and operation status ........................................................................................................ 575 19.7.2 Releasing sub-IDLE mode ........................................................................................................... 576
CHAPTER 20 RESET FUNCTION........................................................................................................ 578 20.1 20.2 20.3 Overview ................................................................................................................................... 578 Configuration............................................................................................................................ 578 Operation .................................................................................................................................. 579
CHAPTER 21 FLASH MEMORY .......................................................................................................... 583 21.1 21.2 21.3 21.4 Features .................................................................................................................................... 583 Memory Configuration ............................................................................................................. 584 Functional Outline.................................................................................................................... 585 Rewriting by Dedicated Flash Programmer .......................................................................... 587
21.4.1 Programming environment........................................................................................................... 587 21.4.2 Communication mode .................................................................................................................. 588 21.4.3 Flash memory control .................................................................................................................. 593 21.4.4 Selection of communication mode ............................................................................................... 594 21.4.5 Communication commands ......................................................................................................... 595 21.4.6 Pin connection ............................................................................................................................. 596
21.5
Rewriting by Self Programming.............................................................................................. 601
21.5.1 21.5.2 Overview...................................................................................................................................... 601 Features....................................................................................................................................... 602
21.5.3 Standard self programming flow .................................................................................................. 603 21.5.4 Flash functions............................................................................................................................. 604 21.5.5 Pin processing ............................................................................................................................. 604 21.5.6 Internal resources used ............................................................................................................... 605
CHAPTER 22 ON-CHIP DEBUG FUNCTION ..................................................................................... 606 22.1 ROM Security Function ........................................................................................................... 606
22.1.1 22.1.2 Security ID ................................................................................................................................... 606 Setting.......................................................................................................................................... 607
22.2
Cautions .................................................................................................................................... 608
CHAPTER 23 ELECTRICAL SPECIFICATIONS (TARGET).............................................................. 609 CHAPTER 24 PACKAGE DRAWING................................................................................................... 631 14
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APPENDIX A INSTRUCTION SET LIST..............................................................................................632 A.1 A.2 Conventions ............................................................................................................................. 632 Instruction Set (in Alphabetical Order).................................................................................. 635
APPENDIX B REGISTER INDEX..........................................................................................................642
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CHAPTER 1 INTRODUCTION
1.1 V850ES/Kx2 Product Lineup
Product Name Number of pins Internal memory (KB) Supply voltage Minimum instruction execution time Clock X1 input Subclock Port CMOS input CMOS I/O N-ch open-drain I/O Timer 16-bit (TMP) 16-bit (TM0) 8-bit (TM5) 8-bit (TMH) Interval timer Watch WDT1 WDT2 RTO Serial CSI interface Automatic transmit/ receive 3-wire CSI UART IC External Address space bus Address bus Mode DMA controller 10-bit A/D converter 8-bit D/A converter Interrupt External Internal Key return input Reset RESET pin WDT1 WDT2 Regulator Standby function Operating ambient temperature 9 26 8 ch Provided Provided Provided None TA = -40 to +85C Provided 8 ch - 9 29 8 ch
2
V850ES/KE2 64 pins
V850ES/KF2 80 pins 128 6 256 12
V850ES/KG2 100 pins 128 6 256 16
V850ES/KJ2 144 pins 128 6 256 16
Flash memory RAM
128 4 2.7 to 5.5 V 50 ns @20 MHz 2 to 10 MHz 32.768 kHz 8 41 (4) 2 1 ch 1 ch 2 ch 2 ch 1 ch 1 ch 1 ch 1 ch 6 bits x 1 ch 2 ch - 2 ch 1 ch - - - -
Note
8 57 (6) 2 1 ch 2 ch 2 ch 2 ch 1 ch 1 ch 1 ch 1 ch 6 bits x 1 ch 2 ch 1 ch 2 ch 1 ch 128 KB 16 bits Multiplex only - 8 ch -
Note
8 72 (8) 4 1 ch 4 ch 2 ch 2 ch 1 ch 1 ch 1 ch 1 ch 6 bits x 1 ch 2 ch 2 ch 3 ch 1 ch 3 MB 22 bits Multiplex/separate 4 ch 8 ch 2 ch 9 41 8 ch
Note
16 106 (12) 6 1 ch 6 ch 2 ch 2 ch 1 ch 1 ch 1 ch 1 ch 6 bits x 2 ch 3 ch 2 ch 3 ch 2 ch 15 MB 24 bits
Note
4 ch 16 ch 2 ch 9 47 8 ch
HALT/IDLE/STOP/sub-IDLE mode
Note
Figures in parentheses indicate the number of pins for which the N-ch open-drain output can be selected.
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1.2 Features
Minimum instruction execution time: 50 ns (operation at main clock (fXX) = 20 MHz) General-purpose registers: 32 bits x 32 registers CPU features: Signed multiplication (16 x 16 32): 1 to 2 clocks (Instructions without creating register hazards can be continuously executed in parallel) Saturated operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock Bit manipulation instructions Load/store instructions with long/short format Memory space: 64 MB of linear address space * Internal memory
PD70F3726 (single-power flash memory: 128 KB/RAM: 4 KB)
Interrupts and exceptions Non-maskable interrupts: 3 sources Maskable interrupts: Software exceptions: Exception trap: I/O lines: Timer function 16-bit timer/event counter P: 1 channel 16-bit timer/event counter 0: 1 channel 8-bit timer/event counter 5: 8-bit timer H: 8-bit interval timer BRG: Watch timer/interval timer: Watchdog timers Watchdog timer 1 (also usable as oscillation stabilization timer): 1 channel Watchdog timer 2: Serial interface Asynchronous serial interface (UART): 2 channels 3-wire serial I/O (CSI0): I2C bus interface (I2C): A/D converter: 10-bit resolution x 8 channels Real-time output port: 6 bits x 1 channel Standby functions: HALT/IDLE/STOP modes, subclock/sub-IDLE modes Clock generator Main clock oscillation (fX)/subclock oscillation (fXT) CPU clock (fCPU) 7 steps (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT) Clock-through mode/PLL mode selectable Reset * Reset by RESET pin * Reset by overflow of watchdog timer 1 (WDTRES1) * Reset by overflow of watchdog timer 2 (WDTRES2) Package: 64-pin plastic LQFP (fine pitch) (10 x 10) 2 channels 1 channel 1 channel 2 channels 2 channels 1 channel 1 channel Total: 51 Key interrupt function 32 sources 32 sources 1 source
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CHAPTER 1 INTRODUCTION
1.3 Applications
Home audio, car audio AV equipment PC peripheral devices (keyboards, etc.) Household appliances * Outdoor units of air conditioners * Microwave ovens, rice cookers Industrial devices * Pumps * Vending machines * FA
1.4 Ordering Information
Part Number Package 64-pin plastic LQFP (fine pitch) (10 x 10)
PD70F3726GB-8EU-A
Remark
Products with -A at the end of the part number are lead-free products.
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1.5 Pin Configuration (Top View)
64-pin plastic LQFP (fine pitch) (10 x 10)
PD70F3726GB-8EU-A
P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P77/ANI7 P39/SCL0 P38/SDA0 PDL7 PDL6 PDL5/FLMD1 PDL4 PDL3 PDL2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVREF0 AVSS FLMD0Note 1 VDD NCNote 2 VSS X1 X2 RESET XT1 XT2 P00/TOH0 P01/TOH1 P02/NMI P03/INTP0 P04/INTP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PDL1 PDL0 PCM1/CLKOUT PCM0 P915/INTP6 P914/INTP5 P913/INTP4 P99/SCK01 P98/SO01 P97/SI01 P96/TI51/TO51 P91/KR7/RXD1 P90/KR6/TXD1 P55/KR5/RTP05 P54/KR4/RTP04 EVDD
Notes 1. Connect to VSS in normal operation mode. 2. Leave the NC pin open. Caution Make EVDD the same potential as VDD.
P05/INTP2 P06/INTP3 P40/SI00 P41/SO00 P42/SCK00 P30/TXD0 P31/RXD0/INTP7 P32/ASCK0/ADTRG/TO01 P33/TIP00/TOP00 P34/TIP01/TOP01 P35/TI010/TO01 P50/KR0/TI011/RTP00 P51/KR1/TI50/RTP01 P52/KR2/TO50/RTP02 P53/KR3/RTP03 EVSS
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CHAPTER 1 INTRODUCTION
Pin identification ADTRG: ANI0 to ANI7: ASCK0: AVREF0: AVSS: CLKOUT: EVDD: EVSS: FLMD0, FLMD1: INTP0 to INTP7: KR0 to KR7: NC: NMI: P00 to P06: P40 to P42: P50 to P55: P70 to P77: P90, P91, P96 to P99, P913 to P915: PCM0, PCM1: Port 9 Port CM A/D trigger input Analog input Asynchronous serial clock Analog reference voltage Ground for analog Clock output Power supply for port Ground for port Flash programming mode External interrupt input Key return Non-connection Non-maskable interrupt request Port 0 Port 4 Port 5 Port 7 PDL0 to PDL7: RESET: RTP00 to RTP05: RXD0, RXD1: SCK00, SCK01: SCL0: SDA0: SI00, SI01: SO00, SO01: TI010, TI011, TI50, TI51, TIP00, TIP01: TO01, TO50, TO51, TOH0, TOH1, TOP00, TOP01: TXD0, TXD1: VDD: VSS: X1, X2: XT1, XT2: Timer output Transmit data Power supply Ground Crystal for main clock Crystal for subclock Timer input Port DL Reset Real-time output port Receive data Serial clock Serial clock Serial data Serial input Serial output
P30 to P35, P38, P39: Port 3
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1.6 Function Block Configuration
(1) Internal block diagram
NMI INTP0 to INTP7
CPU INTC Flash memory PC 128 KB 16-bit timer/event counter 0: 1 ch 32-bit barrel shifter RAM System registers BCU ALU
General-purpose registers 32 bits x 32
Instruction queue Multiplier 16 x 16 32
TI010, TI011 TO01
TIP00, TIP01 TOP00, TOP01
16-bit timer/ event counter P: 1 ch
4 KB
TI50, TI51 TO50, TO51
8-bit timer/event counter 5: 2 ch
TOH0, TOH1
8-bit timer H: 2 ch CLKOUT Port A/D converter CG X1 X2 XT1 XT2 RESET
PDL0 to PDL7
PCM0, PCM1
P70 to P77
P50 to P55
P40 to P42
CSI0: 2 ch
P90, P91, P96 to P99, P913 to P915
P30 to P35, P38, P39
P00 to P06
SO00, SO01 SI00, SI01 SCK00, SCK01 SDA0
I2C: 1 ch SCL0 TXD0, TXD1 RXD0, RXD1 ASCK0
AVREF0 AVSS ANI0 to ANI7 ADTRG
EVDD EVSS FLMD0, FLMD1 VSS
UART: 2 ch
Watchdog timer: 2 ch
Key interrupt function Watch timer
KR0 to KR7
RTP00 to RTP05
RTO: 1 ch
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CHAPTER 1 INTRODUCTION
(2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other types of instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits x 16 bits 32 bits) and a barrel shifter (32 bits) help accelerate complex processing. (b) Bus control unit (BCU) The BCU controls the internal bus. (c) ROM This consists of a 128 KB flash memory mapped to the address spaces from 0000000H to 001FFFFH. ROM can be accessed by the CPU in one clock cycle during instruction fetch. (d) RAM This consists of a 4 KB RAM mapped to the address spaces from 3FFE000H to 3FFEFFFH. RAM can be accessed by the CPU in one clock cycle during data access. (e) Interrupt controller (INTC) This controller handles hardware interrupt requests (NMI, INTP0 to INTP7) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed. (f) Clock generator (CG) A main clock oscillator and subclock oscillator are provided and generate the main clock oscillation frequency (fX) and subclock frequency (fXT), respectively. There are two modes: In the clock-through mode, fX is used as the main clock frequency (fXX) as is. In the PLL mode, fX is used multiplied by 4. The CPU clock frequency (fCPU) can be selected from among fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT. (g) Timer/counter One 16-bit timer/event counter 0 channel, one 16-bit timer/event counter P channel, and two 8-bit timer/event counter 5 channels are incorporated, enabling measurement of pulse intervals and frequency as well as programmable pulse output. Two 8-bit timer/event counter 5 channels can be connected in cascade to configure a 16-bit timer. Two 8-bit timer H channels enabling programmable pulse output are provided on chip. (h) Watch timer This timer counts the reference time (0.5 seconds) for counting the clock from the subclock (32.768 kHz) or fBRG (32.768 kHz) from the clock generator. At the same time, the watch timer can be used as an interval timer.
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(i)
Watchdog timer Two watchdog timer channels are provided on chip to detect program loops and system abnormalities. Watchdog timer 1 can be used as an interval timer. When used as a watchdog timer, it generates a nonmaskable interrupt request signal (INTWDT1) or system reset signal (WDTRES1) after an overflow occurs. When used as an interval timer, it generates a maskable interrupt request signal (INTWDTM1) after an overflow occurs. Watchdog timer 2 operates by default following reset release. It generates a non-maskable interrupt request signal (INTWDT2) or system reset signal (WDTRES2) after an overflow occurs.
(j)
Serial interface (SIO) The V850ES/KE2 includes three kinds of serial interfaces: an asynchronous serial interface (UARTn), a clocked serial interface (CSI0n), and an I2C bus interface (I2C0), and can simultaneously use up to five channels. For UARTn, data is transferred via the TXDn and RXDn pins. For CSI0n, data is transferred via the SO0n, SI0n, and SCK0n pins. For I2C0, data is transferred via the SDA0 and SCL0 pins. Remark n = 0, 1
(k) A/D converter This high-speed, high-resolution 10-bit A/D converter includes 8 analog input pins. performed using the successive approximation method. (l) Key interrupt function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins. (m) Real-time output function This function transfers 6-bit data set beforehand to output latches upon occurrence of a timer compare register match signal. A 1-channel 6-bit data real-time output function is provided on chip. (n) Ports As shown below, the following ports have general-purpose port functions and control pin functions.
Port P0 P3 P4 P5 P7 P9 PCM PDL I/O 7-bit I/O 8-bit I/O 3-bit I/O 6-bit I/O 8-bit input 9-bit I/O 2-bit I/O 8-bit I/O Alternate Function NMI, external interrupt, timer output Serial interface, timer I/O, external interrupt, A/D converter trigger Serial interface Timer I/O, key interrupt function, real-time output function A/D converter analog input Serial interface, timer I/O, external interrupt, key interrupt function Clock output -
Conversion is
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CHAPTER 1 INTRODUCTION
1.7 Overview of Functions
Part Number Internal memory ROM High-speed RAM
PD70F3726
128 KB (single-power flash memory) 4 KB 64 MB 32 bits x 32 registers Ceramic/crystal/external clock When PLL not used: 2 to 10 MHz (2.7 to 5.5 V) When PLL used: 2 to 5 MHz (4.5 to 5.5 V), 2 MHz (2.7 to 5.5 V)
Memory space General-purpose registers Main clock (oscillation frequency)
Subclock (oscillation frequency) Minimum instruction execution time DSP function
Crystal/external clock (32.768 kHz) 50 ns (when main clock operated at (fXX) = 20 MHz) 32 x 32 = 64: 200 to 250 ns (at 20 MHz) 32 x 32 + 32 = 32: 300 ns (at 20 MHz) 16 x 16 = 32: 50 to 100 ns (at 20 MHz) 16 x 16 + 32 = 32: 150 ns (at 20 MHz)
I/O ports
51 * Input: 8 * I/O: 43 (among these, N-ch open-drain output selectable: 4, fixed to N-ch open-drain output: 2)
Timer
16-bit timer/event counter P: 1 channel 16-bit timer/event counter 0: 1 channel 8-bit timer/event counter 5: 2 channels (16-bit timer/event counter: Usable as 1 channel) 8-bit timer H: 2 channels Watchdog timer: 2 channels Watch timer: 1 channel 8-bit interval timer: 1 channel 4 bits x 1, 2 bits x 1, or 6 bits x 1 10-bit resolution x 8 channels CSI: 2 channels UART: 2 channels I C bus: 1 channel Dedicated baud rate generator: 2 channels
Note 2
Real-time output port A/D converter Serial interface
Interrupt sources Power save function Operating supply voltage Package
External: 9 (9)
, internal: 26
STOP/IDLE/HALT/sub-IDLE mode 4.5 to 5.5 V (at 20 MHz)/2.7 to 5.5 V (at 8 MHz) 64-pin plastic LQFP (fine pitch) (10 x 10 mm)
Note The figure in parentheses indicates the number of external interrupts that can release STOP mode.
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CHAPTER 2 PIN FUNCTIONS
The names and functions of the pins of the V850ES/KE2 are described below, divided into port pins and non-port pins. The pin I/O buffer power supplies are divided into two systems; AVREF0 and EVDD. The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies
Power Supply AVREF0 EVDD Port 7 RESET, ports 0, 3 to 5, 9, CM, DL Corresponding Pins
2.1 List of Pin Functions
(1) Port pins (1/2)
Pin Name Pin No. P00 P01 P02 P03 P04 P05 P06 P30 P31 P32 P33 P34 P35 P38 P39 P40 P41 P42 12 13 14 15 16 17 18 22 23 24 25 26 27 55 56 19 20 21 I/O Yes Port 4 I/O port Input/output can be specified in 1-bit units. P41 and P42 can be specified as N-ch opendrain output in 1-bit units. SO00 SCK00 No I/O Yes Port 3 I/O port Input/output can be specified in 1-bit units. P38 and P39 are fixed to N-ch open-drain output. I/O I/O Pull-up Resistor Yes Port 0 I/O port Input/output can be specified in 1-bit units. Function TOH0 TOH1 NMI INTP0 INTP1 INTP2 INTP3 TXD0 RXD0/INTP7 ASCK0/ADTRG/TO01 TIP00/TOP00 TIP01/TOP01 TI010/TO01 SDA0 SCL0 SI00 Alternate Function
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CHAPTER 2 PIN FUNCTIONS
(2/2)
Pin Name Pin No. P50 P51 P52 P53 P54 P55 P70 P71 P72 P73 P74 P75 P76 P77 P90 P91 P96 P97 P98 P99 P913 P914 P915 PCM0 PCM1 PDL0 PDL1 PDL2 PDL3 PDL4 PDL5 PDL6 PDL7 28 29 30 31 34 35 64 63 62 61 60 59 58 57 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 FLMD1 - - I/O Yes I/O Yes Port CM I/O port Input/output can be specified in 1-bit units. Port DL I/O port Input/output can be specified in 1-bit units. I/O Yes Port 9 I/O port Input/output can be specified in 1-bit units. P98 and P99 can be specified as N-ch opendrain output in 1-bit units. Input No Port 7 Input port I/O I/O Pull-up Resistor Yes Port 5 I/O port Input/output can be specified in 1-bit units. Function Alternate Function TI011/RTP00/KR0 TI50/RTP01/KR1 TO50/RTP02/KR2 RTP03/KR3 RTP04/KR4 RTP05/KR5 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 TXD1/KR6 RXD1/KR7 TI51/TO51 SI01 SO01 SCK01 INTP4 INTP5 INTP6 - CLKOUT - - - - -
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(2) Non-port pins (1/2)
Pin Name Pin No. ADTRG ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ASCK0 AVREF0 24 64 63 62 61 60 59 58 57 24 1 Input - Yes - UART0 serial clock input Reference voltage for A/D converter and positive power supply for alternate-function ports AVSS 2 - - Ground potential for A/D converter and alternate-function ports CLKOUT EVDD EVSS FLMD0 FLMD1 INTP0 INTP1 INTP2 INTP3 46 33 32 3 52 15 16 17 18 External interrupt request input (maskable, digital + analog noise elimination) INTP4 INTP5 INTP6 INTP7 KR0 KR1 KR2 KR3 KR4 KR5 KR6 KR7 NC NMI 42 43 44 23 28 29 30 31 34 35 36 37 5 14 - Input Yes - Not internally connected. Leave open. External interrupt input (non-maskable, analog noise elimination) RESET 9 Input - System reset input - P02 Input Yes Key return input External interrupt request input (maskable, analog noise elimination) P913 P914 P915 P31/RXD0 P50/TI011/RTP00 P51/TI50/RTP01 P52/TO50/RTP02 P53/RTP03 P54/RTP04 P55/RTP05 P90/TXD1 P91/RXD1 - Input Output - - Input No Yes Yes External interrupt request input (maskable, analog noise elimination) No - - Internal system clock output Positive power supply for external Ground potential for external Flash programming mode setting pin PDL5 P03 P04 P05 P06 PCM1 - - - - I/O Input Input Pull-up Resistor Yes No Function A/D converter external trigger input Analog voltage input for A/D converter Alternate Function P32/ASCK0/TO01 P70 P71 P72 P73 P74 P75 P76 P77 P32/ADTRG/TO01 -
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CHAPTER 2 PIN FUNCTIONS
(2/2)
Pin Name Pin No. RTP00 RTP01 RTP02 RTP03 RTP04 RTP05 RXD0 RXD1 SCK00 SCK01 SCL0 28 29 30 31 34 35 23 37 21 41 56 I/O No I/O Yes Input Yes Serial receive data input for UART0 Serial receive data input for UART1 Serial clock I/O for CSI00 and CSI01 N-ch open-drain output can be specified in 1bit units. Serial clock I/O for I C0 Fixed to N-ch open-drain output SDA0 55 I/O No Serial transmit/receive data I/O for I C0 Fixed to N-ch open-drain output SI00 SI01 SO00 SO01 TI010 TI011 TI50 TI51 TIP00 19 39 20 40 27 28 29 38 25 Input Yes Output Yes Input Yes Serial receive data input for CSI00 Serial receive data input for CSI01 P40 P97
2 2
I/O Output
Pull-up Resistor Yes
Function Real-time output port
Alternate Function P50/TI011/KR0 P51/TI50/KR1 P52/TO50/KR2 P53/KR3 P54/KR4 P55/KR5 P31/INTP7 P91/KR7 P42 P99 P39
P38
Serial transmit data output for CSI00 and CSI01 P41 N-ch open-drain output can be specified in 1-bit P98 units. Capture trigger input/external event input for TM01 P35/TO01 Capture trigger input for TM01 External event input for TM50 External event input for TM51 Capture trigger input/external event input for TMP0 P50/RTP00/KR0 P51/RTP01/KR1 P96/TO51 P33/TOP00
TIP01 TO01
26 24 27 Output Yes
Capture trigger input for TMP0 Timer output for TM01
P34/TOP01 P32/ASCK0/ADTRG P35/TI010
TO50 TO51 TOH0 TOH1 TOP00 TOP01 TXD0 TXD1 VDD VSS X1 X2 XT1 XT2
30 38 12 13 25 26 22 36 4 6 7 8 10 11 - - Input - Input - No No No No - - Output Yes
Timer output for TM50 Timer output for TM51 Timer output for TMH0 Timer output for TMH1 Timer output for TMP0
P52/RTP02/KR2 P96/TI51 P00 P01 P33/TIP00 P34/TIP01
Serial transmit data output for UART0 Serial transmit data output for UART1 Positive power supply pin for internal Ground potential for internal Connecting resonator for main clock
P30 P90/KR6 - - - -
Connecting resonator for subclock
- -
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2.2 Pin I/O Circuits and Recommended Connection of Unused Pins
(1/2)
Pin P00 P01 P02 P03 to P06 P30 P31 P32 P33 P34 P35 P38 P39 P40 P41 P42 P50 P51 P52 P53 P54 P55 P70 to P77 P90 P91 P96 P97 P98 P99 P913 to P915 PCM0 PCM1 PDL0 to PDL4 PDL5 PDL6, PDL7 AVREF0 AVSS EVDD EVSS FLMD1 - - - - - CLKOUT - TOH0 TOH1 NMI INTP0 to INTP3 TXD0 RXD0/INTP7 ASCK0/ADTRG TIP00/TOP00 TIP01/TOP01 TI010/TO01 SDA0 SCL0 SI00 SO00 SCK00 TI011/RTP00/KR0 TI50/RTP01/KR1 TO50/RTP02/KR2 RTP03/KR3 RTP04/KR4 RTP05/KR5 ANI0 to ANI7 TXD1/KR6 RXD1/KR7 TI51/TO51 SI01 SO01 SCK01 INTP4 to INTP6 - Alternate Function Pin No. 12 13 14 15 to 18 22 23 24 25 26 27 55 56 19 20 21 28 29 30 31 34 35 64 to 57 36 37 38 39 40 41 42 to 44 45 46 47 to 51 52 53, 54 1 2 33 32 - - - - Directly connect to VDD. - - - 5-W 10-E 10-F 5-W 5-A 9-C 8-A Connect to AVREF0 or AVSS. Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. 10-A 5-W 10-E 10-F 8-A 13-AD 5-A 5-W 5-W I/O Circuit Type 5-A Recommended Connection Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open.
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CHAPTER 2 PIN FUNCTIONS
(2/2)
Pin NC RESET FLMD0 Alternate Function - - - 5 9 3 Pin No. I/O Circuit Type - 2 - Recommended Connection Leave open. - Directly connect to EVSS or VSS or pull down with a 10 k resistor. VDD VSS X1 X2 XT1 XT2 - - - - - - 4 6 7 8 10 11 - - - - 16 16 - - - - Directly connect to VSS Leave open.
Note
.
Note Be sure to set the PSMR.XTSTP bit to 1 when this pin is not used.
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2.3 Pin I/O Circuits
(1/2)
Type 2 Type 9-C
P-ch IN IN N-ch AVSS AVREF0 (threshold voltage)
+ -
Comparator
Input enable Schmitt-triggered input with hysteresis characteristics
Type 5-A
VDD
Type 10-A Pull-up enable VDD Data IN/OUT P-ch
VDD P-ch
Pull-up enable Data
P-ch VDD P-ch
Output disable Input enable Type 5-W Pull-up enable
N-ch VSS
Open drain Output disable
IN/OUT N-ch VSS
VDD P-ch VDD
Type 10-E Pull-up enable VDD Data P-ch
VDD P-ch
Data
P-ch IN/OUT IN/OUT Open drain Output disable N-ch VSS
Output disable
N-ch VSS
Input enable Type 8-A Pull-up enable VDD Data P-ch IN/OUT Output disable VSS N-ch VDD Type 10-F
Input enable VDD P-ch VDD Data Open drain Output disable P-ch IN/OUT N-ch VSS
P-ch
Pull-up enable
Input enable
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CHAPTER 2 PIN FUNCTIONS
(2/2)
Type 13-AD Type 16 Feedback cut-off P-ch Data Output disable N-ch VSS XT1 Input enable XT2 IN/OUT
Remark
Read VDD as EVDD. Also, read VSS as EVSS.
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CHAPTER 3 CPU FUNCTIONS
The CPU of the V850ES/KE2 is based on the RISC architecture and executes most instructions in one clock cycle by using 5-stage pipeline control.
3.1 Features
Number of instructions: 83 100 ns (@ 10 MHz operation: 2.7 to 5.5 V) Memory space Program (physical address) space: 64 MB linear Data (logical address) space: General-purpose registers: 32 bits x 32 Internal 32-bit architecture 5-stage pipeline control Multiply/divide instructions Saturated operation instructions 32-bit shift instruction: 1 clock Load/store instruction with long/short format Four types of bit manipulation instructions * SET1 * CLR1 * NOT1 * TST1 4 GB linear * Memory block division function: 2 MB, 2 MB, 4 MB, 8 MB/Total of 4 blocks
Minimum instruction execution time: 50.0 ns (@ 20 MHz operation: 4.5 to 5.5 V)
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3.2 CPU Register Set
The CPU registers of the V850ES/KE2 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers have 32-bit width. For details, refer to the V850ES Architecture User's Manual.
(1) Program register set
31 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31
(Element pointer (EP)) (Link pointer (LP)) CTBP DBPC DBPSW CTPC CTPSW PSW (Stack pointer (SP)) (Global pointer (GP)) (Text pointer (TP)) ECR FEPC FEPSW
(2) System register set
0 31 EIPC EIPSW
(Interrupt status saving register) (Interrupt status saving register)
0
(Zero register) (Assembler-reserved register)
(NMI status saving register) (NMI status saving register)
(Interrupt source register)
(Program status word)
(CALLT execution status saving register) (CALLT execution status saving register)
(Exception/debug trap status saving register) (Exception/debug trap status saving register)
(CALLT base pointer)
31 PC
(Program counter)
0
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3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. All of these registers can be used as a data variable or address variable. However, r0 and r30 are implicitly used by instructions and care must be exercised when using these registers. r0 always holds 0 and is used for operations that use 0 and offset 0 addressing. r30 is used as a base pointer when performing memory access with the SLD and SST instructions. Also, r1, r3 to r5, and r31 are implicitly used by the assembler and C compiler. Therefore, before using these registers, their contents must be saved so that they are not lost, and they must be restored to the registers after the registers have been used. There are cases when r2 is used by the real-time OS. If r2 is not used by the real-time OS, r2 can be used as a variable register. Table 3-1. Program Registers
Name r0 r1 r2 r3 r4 r5 r6 to r29 r30 r31 PC Usage Zero register Assembler-reserved register Always holds 0 Working register for generating 32-bit immediate Operation
Address/data variable register (when r2 is not used by the real-time OS to be used) Stack pointer Global pointer Text pointer Address/data variable register Element pointer Link pointer Program counter Base pointer when memory is accessed Used by compiler when calling function Holds instruction address during program execution Used to generate stack frame when function is called Used to access global variable in data area Register to indicate the start of the text area (area for placing program code)
(2) Program counter (PC) This register holds the address of the instruction under execution. The lower 26 bits of this register are valid, and bits 31 to 26 are fixed to 0. If a carry occurs from bit 25 to bit 26, it is ignored. Bit 0 is fixed to 0, and branching to an odd address cannot be performed.
31 PC Fixed to 0
26 25 Instruction address under execution
10 0 After reset 00000000H
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3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Read from and write to system registers are performed by setting the system register numbers shown below with the system register load/store instructions (LDSR, STSR instructions). Table 3-2. System Register Numbers
System Register No. System Register Name Operand Specification Enabled LDSR Instruction 0 1 2 3 4 5 6 to 15 Interrupt status saving register (EIPC)
Note 1
STSR Instruction Yes Yes Yes Yes Yes Yes No
Yes Yes Yes Yes No Yes No
Interrupt status saving register (EIPSW) NMI status saving register (FEPC)
Note 1
Note 1
NMI status saving register (FEPSW) Interrupt source register (ECR) Program status word (PSW)
Note 1
Reserved numbers for future function expansion (The operation is not guaranteed if accessed.)
16 17 18 19 20 21 to 31
CALLT execution status saving register (CTPC) CALLT execution status saving register (CTPSW) Exception/debug trap status saving register (DBPC) Exception/debug trap status saving register (DBPSW) CALLT base pointer (CTBP) Reserved numbers for future function expansion (The operation is not guaranteed if accessed.)
Yes Yes Yes
Note 2
Yes Yes Yes Yes
Note 2
Yes
Note 2
Note 2
Yes No
Yes No
Notes 1. Since only one set of these registers is available, the contents of this register must be saved by the program when multiple interrupt servicing is enabled. 2. These registers can be accessed only during the interval between the execution of the DBTRAP instruction or illegal opcode and the DBRET instruction. Caution Even if bit 0 of EIPC, FEPC, or CTPC is set (1) by the LDSR instruction, bit 0 is ignored during return with the RETI instruction following interrupt servicing (because bit 0 of PC is fixed to 0). When setting a value to EIPC, FEPC, and CTPC, set an even number (bit 0 = 0).
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(1) Interrupt status saving registers (EIPC, EIPSW) There are two interrupt status saving registers, EIPC and EIPSW. Upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (PC) are saved to EIPC and the contents of the program status word (PSW) are saved to EIPSW (upon occurrence of a non-maskable interrupt (NMI), the contents are saved to the NMI status saving registers (FEPC, FEPSW)). The address of the next instruction following the instruction executed when a software exception or maskable interrupt occurs is saved to EIPC, except for some instructions (refer to 21.9 Period in Which Interrupts Are Not Acknowledged by CPU). The current PSW contents are saved to EIPSW. Since there is only one set of interrupt status saving registers, the contents of these registers must be saved by the program when multiple interrupt servicing is enabled. Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved (fixed to 0) for future function expansion. When the RETI instruction is executed, the values in EIPC and EIPSW are restored to the PC and PSW, respectively.
31 EIPC
26 25 (PC contents saved)
0 After reset 0xxxxxxxH (x: Undefined) 87 0 After reset 000000xxH (x: Undefined)
000000
31 EIPSW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PSW contents saved)
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(2) NMI status saving registers (FEPC, FEPSW) There are two NMI status saving registers, FEPC and FEPSW. Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to FEPC and the contents of the program status word (PSW) are saved to FEPSW. The address of the next instruction following the instruction executed when a non-maskable interrupt occurs is saved to FEPC, except for some instructions. The current PSW contents are saved to FEPSW. Since there is only one set of NMI status saving registers, the contents of these registers must be saved by the program when multiple interrupt servicing is performed. Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved (fixed to 0) for future function expansion.
31 FEPC
26 25 (PC contents saved)
0 After reset 0xxxxxxxH (x: Undefined) 87 0 After reset 000000xxH (x: Undefined)
000000
31 FEPSW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PSW contents saved)
(3) Interrupt source register (ECR) Upon occurrence of an interrupt or an exception, the interrupt source register (ECR) holds the source of an interrupt or an exception. The value held by ECR is the exception code coded for each interrupt source. This register is a read-only register, and thus data cannot be written to it using the LDSR instruction.
31 ECR FECC
16 15 EICC
0 After reset 00000000H
Bit position 31 to 16 15 to 0
Bit name FECC EICC
Description Non-maskable interrupt (NMI) exception code Exception, maskable interrupt exception code
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(4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the program status (instruction execution result) and the CPU status. When the contents of this register are changed using the LDSR instruction, the new contents become valid immediately following completion of LDSR instruction execution. Interrupt request acknowledgment is held pending while a write to the PSW is being executed by the LDSR instruction. Bits 31 to 8 are reserved (fixed to 0) for future function expansion. (1/2)
31 PSW RFU 876543210 NP EP ID SAT CY OV S Z After reset 00000020H
Bit position 31 to 8 7
Flag name RFU NP Reserved field. Fixed to 0.
Description
Indicates that non-maskable interrupt (NMI) servicing is in progress. This flag is set to 1 when an NMI request is acknowledged, and disables multiple interrupts. 0: NMI servicing not in progress 1: NMI servicing in progress
6
EP
Indicates that exception processing is in progress. This flag is set to 1 when an exception occurs. Moreover, interrupt requests can be acknowledged even when this bit is set. 0: Exception processing not in progress 1: Exception processing in progress
5
ID
Indicates whether maskable interrupt request acknowledgment is enabled. 0: Interrupt enabled 1: Interrupt disabled
Note
4
SAT
Indicates that the result of executing a saturated operation instruction has overflowed and that the calculation result is saturated. Since this is a cumulative flag, it is set to 1 when the result of a saturated operation instruction becomes saturated, and it is not cleared to 0 even if the operation results of successive instructions do not become saturated. This flag is neither set nor cleared when arithmetic operation instructions are executed. 0: Not saturated 1: Saturated
3
CY
Indicates whether carry or borrow occurred as the result of an operation. 0: No carry or borrow occurred 1: Carry or borrow occurred
Note
2
OV
Indicates whether overflow occurred during an operation. 0: No overflow occurred 1: Overflow occurred.
1
S
Note
Indicates whether the result of an operation is negative. 0: Operation result is positive or 0. 1: Operation result is negative.
0
Z
Indicates whether operation result is 0. 0: Operation result is not 0. 1: Operation result is 0.
Remark
Note is explained on the following page.
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(2/2) Note During saturated operation, the saturated operation results are determined by the contents of the OV flag and S flag. The SAT flag is set (to 1) only when the OV flag is set (to 1) during saturated operation.
Operation result status SAT Maximum positive value exceeded Maximum negative value exceeded Positive (maximum value not exceeded) Negative (maximum value not exceeded) 1 1 Holds value before operation 1 1 0 Flag status OV 0 1 0 1 S Saturated operation result 7FFFFFFFH 80000000H Actual operation result
(5) CALLT execution status saving registers (CTPC, CTPSW) There are two CALLT execution status saving registers, CTPC and CTPSW. When the CALLT instruction is executed, the contents of the program counter (PC) are saved to CTPC, and the program status word (PSW) contents are saved to CTPSW. The contents saved to CTPC consist of the address of the next instruction after the CALLT instruction. The current PSW contents are saved to CTPSW. Bits 31 to 26 of CTPC and bits 31 to 8 of CTPSW are reserved (fixed to 0) for future function expansion.
31 CTPC
26 25 (PC contents saved)
0 After reset 0xxxxxxxH (x: Undefined) 87 0 After reset 000000xxH (x: Undefined)
000000
31 CTPSW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PSW contents saved)
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(6) Exception/debug trap status saving registers (DBPC, DBPSW) There are two exception/debug trap status saving registers, DBPC and DBPSW. Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to DBPC, and the program status word (PSW) contents are saved to DBPSW. The contents saved to DBPC consist of the address of the next instruction after the instruction executed when an exception trap or debug trap occurs. The current PSW contents are saved to DBPSW. Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved (fixed to 0) for future function expansion.
31 DBPC
26 25 (PC contents saved)
0 After reset 0xxxxxxxH (x: Undefined) 87 0 After reset 000000xxH (x: Undefined)
000000
31 DBPSW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PSW contents saved)
(7) CALLT base pointer (CTBP) The CALLT base pointer (CTBP) is used to specify table addresses and generate target addresses (bit 0 is fixed to 0). Bits 31 to 26 are reserved (fixed to 0) for future function expansion.
31 CTBP
26 25 (Base address)
0 0 After reset 0xxxxxxxH (x: Undefined)
000000
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3.3 Operating Modes
The V850ES/KE2 has the following operating modes. (1) Normal operating mode After the system has been released from the reset state, the pins related to the bus interface are set to the port mode, execution branches to the reset entry address of the internal ROM, and instruction processing is started. (2) Flash memory programming mode When this mode is specified, the internal flash memory can be programmed by using a flash programmer. (a) Specifying operating mode The operating mode is specified according to the status (input level) of the FLMD0 and FLMD1 pins. In the normal operating mode, input a low level to the FLMD0 pin during the reset period. A high level is input to the FLMD0 pin by the flash programmer in the flash memory programming mode if a flash programmer is connected. In the self-programming mode, input a high level to this pin from an external circuit. Fix the specification of these pins in the application system and do not change the setting of these pins during operation.
FLMD0 L H H FLMD1 x L H Operating Mode Normal operating mode Flash memory programming mode Setting prohibited
Remark
H: High level L: Low level x: don't care
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3.4 Address Space
3.4.1 CPU address space For instruction addressing, an internal ROM area of up to 1 MB, and an internal RAM area are supported in a linear address space (program space) of up to 64 MB. For operand addressing (data access), up to 4 GB of a linear address space (data space) is supported. The 4 GB address space, however, is viewed as 64 images of a 64 MB physical address space. This means that the same 64 MB physical address space is accessed regardless of the value of bits 31 to 26. Figure 3-1. Address Space Image
Image 63
4 GB
* * *
Data space On-chip peripheral I/O area Image 1
Program space Reserved area
Internal RAM area
Internal RAM area Access-prohibited area 64 MB
64 MB Access-prohibited area Image 0 External memory area
Internal ROM area (external memory) 1 MB Internal ROM area
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3.4.2 Wraparound of CPU address space (1) Program space Of the 32 bits of the program counter (PC), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit 25 to bit 26 as a result of branch address calculation, the higher 6 bits ignore this and remain 0. Therefore, the lower-limit address of the program space, 00000000H, and the upper-limit address, 03FFFFFFH, are contiguous addresses, and the program space is wrapped around at the boundary of these addresses. Caution No instructions can be fetched from the 4 KB area of 03FFF000H to 03FFFFFFH because this area is an on-chip peripheral I/O area. Therefore, do not execute any branch operation instructions in which the destination address will reside in any part of this area.
00000001H 00000000H
Program space
(+) direction 03FFFFFFH 03FFFFFEH Program space
(-) direction
(2) Data space The result of an operand address calculation that exceeds 32 bits is ignored. Therefore, the lower-limit address of the data space, address 00000000H, and the upper-limit address, FFFFFFFFH, are contiguous addresses, and the data space is wrapped around at the boundary of these addresses.
00000001H 00000000H
Data space
(+) direction FFFFFFFFH FFFFFFFEH Data space
(-) direction
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3.4.3 Memory map The V850ES/KE2 has reserved areas as shown below. Figure 3-2. Data Memory Map (Physical Addresses)
3FFFFFFH (80 KB) 3FEC000H 3FEBFFFH
On-chip peripheral I/O area (4 KB)
3FFFFFFH 3FFF000H 3FFEFFFH
Internal RAM area (60 KB)
3FFF000H 3FFEFFFH Use-prohibited area 3FEC000H
Use-prohibited area
00FFFFFH Internal ROM area (1 MB) 0000000H
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Figure 3-3. Program Memory Map
03FFFFFFH 03FFF000H 03FFEFFFH
Use-prohibited area (Program fetch disabled area)
Internal RAM area (60 KB) 03FF0000H 03FEFFFFH
Use-prohibited area (Program fetch disabled area)
00100000H 000FFFFFH 00000000H
Internal ROM area (1 MB)
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3.4.4 Areas (1) Internal ROM area An area of 1 MB from 0000000H to 00FFFFFH is reserved for the internal ROM area. (a) Internal ROM (128 KB) A 128 KB area from 0000000H to 001FFFFH is provided in the PD70F3726. Addresses 0020000H to 00FFFFFH are an access-prohibited area. Figure 3-4. Internal ROM Area (128 KB)
00FFFFFH
Access-prohibited area
0020000H 001FFFFH Internal ROM area (128 KB) 0000000H
(2) Internal RAM area An area of 60 KB maximum from 3FF0000H to 3FFEFFFH is reserved for the internal RAM area. A 4 KB area from 3FFE000H to 3FFEFFFH is provided as physical internal RAM. Addresses 3FF0000H to 3FFDFFFH is an access-prohibited area. Figure 3-5. Internal RAM Area (4 KB)
Physical address space 3FFEFFFH Internal RAM area (4 KB) 3FFE000H 3FFDFFFH
Logical address space FFFEFFFH FFFE000H FFFDFFFH
Access-prohibited area
3FF0000H
FFF0000H
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(3) On-chip peripheral I/O area A 4 KB area from 3FFF000H to 3FFFFFFH is reserved as the on-chip peripheral I/O area. Figure 3-6. On-Chip Peripheral I/O Area
Physical address space 3FFFFFFH
Logical address space FFFFFFFH
On-chip peripheral I/O area (4 KB) 3FFF000H FFFF000H
Peripheral I/O registers assigned with functions such as on-chip peripheral I/O operation mode specification and state monitoring are mapped to the on-chip peripheral I/O area. Program fetches are not allowed in this area. Cautions 1. If word access of a register is attempted, halfword access to the word area is performed twice, first for the lower bits, then for the higher bits, ignoring the lower 2 address bits. 2. If a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits become undefined if the access is a read operation. If a write access is performed, only the data in the lower 8 bits is written to the register. 3. Addresses that are not defined as registers are reserved for future expansion. If these addresses are accessed, the operation is undefined and not guaranteed.
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3.4.5 Recommended use of address space The architecture of the V850ES/KE2 requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in this pointer 32 KB can be directly accessed by an instruction for operand data. Because the number of general-purpose registers that can be used as a pointer is limited, however, by keeping the performance from dropping during address calculation when a pointer value is changed, as many general-purpose registers as possible can be secured for variables, and the program size can be reduced. (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. Regarding the program space, therefore, a 64 MB space of contiguous addresses starting from 00000000H unconditionally corresponds to the memory map. To use the internal RAM area as the program space, access address 3FFE000H to 3FFEFFFH (4 KB). (2) Data space With the V850ES/KE2, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address space. Therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address. (a) Application example of wraparound If R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H 32 KB can be addressed by sign-extended disp16. All the resources, including the internal hardware, can be addressed by one pointer. The zero register (r0) is a register fixed to 0 by hardware, and practically eliminates the need for registers dedicated to pointers.
0001FFFFH 00007FFFH
Internal ROM area
32 KB
(R = ) 0 0 0 0 0 0 0 0 H
FFFFF000H FFFFEFFFH
On-chip peripheral I/O area Internal RAM area FFFFE000H FFFFDFFFH
4 KB 4 KB
Access-prohibited area
24 KB
FFFF8000H
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Figure 3-7. Recommended Memory Map
Program space FFFFFFFFH
Data space
On-chip peripheral I/O FFFFF000H FFFFEFFFH Internal RAM xFFFFFFFH FFFEC000H FFFEBFFFH On-chip peripheral I/O xFFFF000H xFFFEFFFH Internal RAM xFFFE000H xFFFDFFFH xFFEC000H xFFEBFFFH On-chip peripheral I/ONote Internal RAM 03FFE000H 03FFDFFFH 03FEC000H 03FEBFFFH Use prohibited
04000000H 03FFFFFFH 03FFF000H 03FFEFFFH
Program space 64 MB
Use prohibited x0100000H x00FFFFFH Internal ROM x0000000H
00100000H 000FFFFFH 00020000H 0001FFFFH 00000000H
Internal ROM
Internal ROM
Note Access to this area is prohibited. To access the on-chip peripheral I/O in this area, specify addresses FFFF000H to FFFFFFFH. Remark
indicates the recommended area.
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3.4.6 Peripheral I/O registers (1/6)
Address Function Register Name Symbol R/W Operable Bit Unit After Reset 1 FFFFF004H FFFFF00CH FFFFF024H FFFFF02CH FFFFF04CH FFFFF06EH FFFFF100H FFFFF100H FFFFF101H FFFFF102H FFFFF102H FFFFF103H FFFFF106H FFFFF106H FFFFF110H FFFFF112H FFFFF114H FFFFF116H FFFFF118H FFFFF11AH FFFFF11CH FFFFF11EH FFFFF124H FFFFF126H FFFFF128H FFFFF12AH FFFFF12CH FFFFF12EH FFFFF130H FFFFF132H FFFFF134H FFFFF136H FFFFF138H FFFFF13AH FFFFF13CH FFFFF13EH FFFFF142H FFFFF144H FFFFF146H Port DL register Port CM register Port DL mode register Port CM mode register Port CM mode control register System wait control register Interrupt mask register 0 Interrupt mask register 0L Interrupt mask register 0H Interrupt mask register 1 Interrupt mask register 1L Interrupt mask register 1H Interrupt mask register 3 Interrupt mask register 3L Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register PDL PCM PMDL PMCM PMCCM VSWC IMR0 IMR0L IMR0H IMR1 IMR1L IMR1H IMR3 IMR3L WDT1IC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 TM0IC10 TM0IC11 TM5IC0 TM5IC1 CSI0IC0 CSI0IC1 SREIC0 SRIC0 STIC0 SREIC1 SRIC1 STIC1 TMHIC0 TMHIC1 IICIC0 ADIC KRIC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 16 00H
Note
00H
Note
FFH FFH 00H 77H FFFFH FFH FFH FFFFH FFH FFH FFFFH FFH 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H
Note The output latch is 00H. When input, the pin status is read.
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(2/6)
Address Function Register Name Symbol R/W Operable Bit Unit After Reset 1 FFFFF148H FFFFF14AH FFFFF14CH FFFFF172H FFFFF174H FFFFF176H FFFFF178H FFFFF1FAH FFFFF1FCH FFFFF1FEH FFFFF200H FFFFF201H FFFFF202H FFFFF203H FFFFF204H FFFFF205H FFFFF300H FFFFF30AH FFFFF318H FFFFF400H FFFFF406H FFFFF406H FFFFF407H FFFFF408H FFFFF40AH FFFFF40EH FFFFF412H FFFFF412H FFFFF413H FFFFF420H FFFFF426H FFFFF426H FFFFF427H FFFFF428H FFFFF42AH FFFFF432H FFFFF432H FFFFF433H FFFFF440H Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register In-service priority register Command register Power save control register A/D converter mode register Analog input channel specification register Power fail comparison mode register Power fail comparison threshold register A/D conversion result register A/D conversion result register H Key return mode register Selector operation control register 1 Digital noise elimination control register Port 0 register Port 3 register Port 3 register L Port 3 register H Port 4 register Port 5 register Port 7 register Port 9 register Port 9 register L Port 9 register H Port 0 mode register Port 3 mode register Port 3 mode register L Port 3 mode register H Port 4 mode register Port 5 mode register Port 9 mode register Port 9 mode register L Port 9 mode register H Port 0 mode control register WTIIC WTIC BRGIC PIC7 TP0OVIC TP0CCIC0 TP0CCIC1 ISPR PRCMD PSC ADM ADS PFM PFT ADCR ADCRH KRM SELCNT1 NFC P0 P3 P3L P3H P4 P5 P7 P9 P9L P9H PM0 PM3 PM3L PM3H PM4 PM5 PM9 PM9L PM9H PMC0 R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 16 47H 47H 47H 47H 47H 47H 47H 00H Undefined 00H 00H 00H 00H 00H Undefined Undefined 00H 00H 00H 00H
Note
0000H 00H 00H 00H 00H
Note
Note
Note
Note
Note
Undefined 0000H 00H 00H
Note
Note
Note
FFH FFFFH FFH FFH FFH FFH FFFFH FFH FFH 00H
Note The output latch is 00H or 0000H. When input, the pin status is read.
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Address Function Register Name Symbol R/W Operable Bit Unit After Reset 1 FFFFF446H FFFFF446H FFFFF447H FFFFF448H FFFFF44AH FFFFF452H FFFFF452H FFFFF453H FFFFF466H FFFFF46AH FFFFF472H FFFFF472H FFFFF473H FFFFF580H FFFFF581H FFFFF582H FFFFF583H FFFFF590H FFFFF591H FFFFF592H FFFFF593H FFFFF5A0H FFFFF5A1H FFFFF5A2H FFFFF5A3H FFFFF5A4H FFFFF5A5H FFFFF5A6H FFFFF5A8H FFFFF5AAH FFFFF5C0H FFFFF5C0H FFFFF5C1H FFFFF5C2H FFFFF5C2H FFFFF5C3H FFFFF5C4H FFFFF5C4H FFFFF5C5H Port 3 mode control register Port 3 mode control register L Port 3 mode control register H Port 4 mode control register Port 5 mode control register Port 9 mode control register Port 9 mode control register L Port 9 mode control register H Port 3 function control register Port 5 function control register Port 9 function control register Port 9 function control register L Port 9 function control register H 8-bit timer H mode register 0 8-bit timer H carrier control register 0 8-bit timer H compare register 00 8-bit timer H compare register 01 8-bit timer H mode register 1 8-bit timer H carrier control register 1 8-bit timer H compare register 10 8-bit timer H compare register 11 TMP0 control register 0 TMP0 control register 1 TMP0 I/O control register 0 TMP0 I/O control register 1 TMP0 I/O control register 2 TMP0 option register 0 TMP0 capture/compare register 0 TMP0 capture/compare register 1 TMP0 counter read buffer register 16-bit timer counter 5 8-bit timer counter 50 8-bit timer counter 51 16-bit timer compare register 5 8-bit timer compare register 50 8-bit timer compare register 51 Timer clock selection register 5 Timer clock selection register 50 Timer clock selection register 51 PMC3 PMC3L PMC3H PMC4 PMC5 PMC9 PMC9L PMC9H PFC3 PFC5 PFC9 PFC9L PFC9H TMHMD0 TMCYC0 CMP00 CMP01 TMHMD1 TMCYC1 CMP10 CMP11 TP0CTL0 TP0CTL1 TP0IOC0 TP0IOC1 TP0IOC2 TP0OPT0 TP0CCR0 TP0CCR1 TP0CNT TM5 TM50 TM51 CR5 CR50 CR51 TCL5 TCL50 TCL51 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W R/W R/W 8 16 0000H 00H 00H 00H 00H 0000H 00H 00H 00H 00H 0000H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0000H 0000H 0000H 0000H 00H 00H 0000H 00H 00H 0000H 00H 00H
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Address Function Register Name Symbol R/W Operable Bit Unit After Reset 1 FFFFF5C6H FFFFF5C6H FFFFF5C7H FFFFF610H FFFFF612H FFFFF614H FFFFF616H FFFFF617H FFFFF618H FFFFF619H FFFFF680H FFFFF6C0H FFFFF6C1H FFFFF6C2H FFFFF6D0H FFFFF6D1H FFFFF6E0H FFFFF6E2H FFFFF6E4H FFFFF6E5H FFFFF706H FFFFF802H FFFFF806H FFFFF820H FFFFF828H FFFFF8B0H FFFFF8B1H FFFFFA00H FFFFFA02H FFFFFA03H FFFFFA04H FFFFFA05H FFFFFA06H FFFFFA07H FFFFFA10H FFFFFA12H FFFFFA13H FFFFFA14H FFFFFA15H FFFFFA16H FFFFFA17H 16-bit timer mode control register 5 8-bit timer mode control register 50 8-bit timer mode control register 51 16-bit timer counter 01 16-bit timer capture/compare register 010 16-bit timer capture/compare register 011 16-bit timer mode control register 01 Prescaler mode register 01 Capture/compare control register 01 16-bit timer output control register 01 Watch timer operation mode register Oscillation stabilization time selection register Watchdog timer clock selection register Watchdog timer mode register 1 Watchdog timer mode register 2 Watchdog timer enable register Real-time output buffer register L0 Real-time output buffer register H0 Real-time output port mode register 0 Real-time output port control register 0 Port 3 function control expansion register System status register PLL control register Power save mode register Processor clock control register Interval timer BRG mode register Interval timer BRG compare register Asynchronous serial interface mode register 0 Receive buffer register 0 Asynchronous serial interface status register 0 Transmit buffer register 0 Asynchronous serial interface transmit status register 0 Clock select register 0 Baud rate generator control register 0 Asynchronous serial interface mode register 1 Receive buffer register 1 Asynchronous serial interface status register 1 Transmit buffer register 1 Asynchronous serial interface transmit status register 1 Clock select register 1 Baud rate generator control register 1 TMC5 TMC50 TMC51 TM01 CR010 CR011 TMC01 PRM01 CRC01 TOC01 WTM OSTS WDCS WDTM1 WDTM2 WDTE RTBL0 RTBH0 RTPM0 RTPC0 PFCE3 SYS PLLCTL PSMR PCC PRSM PRSCM ASIM0 RXB0 ASIS0 TXB0 ASIF0 CKSR0 BRGC0 ASIM1 RXB1 ASIS1 TXB1 ASIF1 CKSR1 BRGC1 R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R R/W R/W R/W R R R/W R R/W R/W 8 16 0000H 00H 00H 0000H 0000H 0000H 00H 00H 00H 00H 00H 01H 00H 00H 67H 9AH 00H 00H 00H 00H 00H 00H 01H 00H 03H 00H 00H 01H FFH 00H FFH 00H 00H FFH 01H FFH 00H FFH 00H 00H FFH
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Address Function Register Name Symbol R/W Operable Bit Unit After Reset 1 FFFFFB00H FFFFFB04H FFFFFC00H FFFFFC06H FFFFFC13H FFFFFC20H FFFFFC26H FFFFFC33H FFFFFC40H FFFFFC46H FFFFFC48H FFFFFC4AH FFFFFC52H FFFFFC52H FFFFFC53H FFFFFC67H FFFFFC68H FFFFFC73H FFFFFD00H FFFFFD01H FFFFFD02H FFFFFD02H FFFFFD04H FFFFFD04H FFFFFD06H FFFFFD06H FFFFFD08H FFFFFD08H FFFFFD0AH FFFFFD0AH FFFFFD10H FFFFFD11H FFFFFD12H FFFFFD12H FFFFFD14H FFFFFD14H FFFFFD16H FFFFFD16H FFFFFD18H FFFFFD18H TIP00 noise elimination control register TIP01 noise elimination control register External interrupt falling edge specification register 0 External interrupt falling edge specification register 3 External interrupt falling edge specification register 9H External interrupt rising edge specification register 0 External interrupt rising edge specification register 3 External interrupt rising edge specification register 9H Pull-up resistor option register 0 Pull-up resistor option register 3 Pull-up resistor option register 4 Pull-up resistor option register 5 Pull-up resistor option register 9 Pull-up resistor option register 9L Pull-up resistor option register 9H Port 3 function register H Port 4 function register Port 9 function register H Clocked serial interface mode register 00 Clocked serial interface clock selection register 0 Clocked serial interface receive buffer register 0 Clocked serial interface receive buffer register 0L Clocked serial interface transmit buffer register 0 Clocked serial interface transmit buffer register 0L Clocked serial interface read-only receive buffer register 0 Clocked serial interface read-only receive buffer register 0L Clocked serial interface initial transmit buffer register 0 Clocked serial interface initial transmit buffer register 0L Serial I/O shift register 0 Serial I/O shift register 0L Clocked serial interface mode register 01 Clocked serial interface clock selection register 1 Clocked serial interface receive buffer register 1 Clocked serial interface receive buffer register 1L Clocked serial interface transmit buffer register 1 Clocked serial interface transmit buffer register 1L Clocked serial interface read-only receive buffer register 1 Clocked serial interface read-only receive buffer register 1L Clocked serial interface initial transmit buffer register 1 Clocked serial interface initial transmit buffer register 1L P0NFC P1NFC INTF0 INTF3 INTF9H INTR0 INTR3 INTR9H PU0 PU3 PU4 PU5 PU9 PU9L PU9H PF3H PF4 PF9H CSIM00 CSIC0 SIRB0 SIRB0L SOTB0 SOTB0L SIRBE0 SIRBE0L SOTBF0 SOTBF0L SIO00 SIO00L CSIM01 CSIC1 SIRB1 SIRB1L SOTB1 SOTB1L SIRBE1 SIRBE1L SOTBF1 SOTBF1L R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R R R/W R/W R/W R/W R/W R/W R R R/W R/W R R R/W R/W 8 16 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0000H 00H 00H 00H 00H 00H 00H 00H 0000H 00H 0000H 00H 0000H 00H 0000H 00H 00H 0000H 00H 00H 0000H 00H 0000H 00H 0000H 00H 0000H 00H
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Address Function Register Name Symbol R/W Operable Bit Unit After Reset 1 FFFFFD1AH FFFFFD1AH FFFFFD80H FFFFFD82H FFFFFD83H FFFFFD84H FFFFFD85H FFFFFD86H FFFFFD8AH FFFFFF44H FFFFFF4CH Serial I/O shift register 1 Serial I/O shift register 1L IIC shift register 0 IIC control register 0 Slave address register 0 IIC clock selection register 0 IIC function expansion register 0 IIC status register 0 IIC flag register 0 Pull-up resistor option register DL Pull-up resistor option register CM SIO01 SIO01L IIC0 IICC0 SVA0 IICCL0 IICX0 IICS0 IICF0 PUDL PUCM R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W 8 16 00H 0000H 00H 00H 00H 00H 00H 00H 00H 00H 00H
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3.4.7 Special registers Special registers are registers that prevent invalid data from being written when an inadvertent program loop occurs. The V850ES/KE2 has the following three special registers. * Power save control register (PSC) * Processor clock control register (PCC) * Watchdog timer mode register (WDTM1) Moreover, there is also the PRCMD register, which is a protection register for write operations to the special registers that prevents the application system from unexpectedly stopping due to an inadvertent program loop. Write access to the special registers is performed with a special sequence and illegal store operations are notified to the SYS register. (1) Setting data to special registers Setting data to a special registers is done in the following sequence. <1> <2> <3> Prepare the data to be set to the special register in a general-purpose register. Write the data prepared in step <1> to the PRCMD register. Write the setting data to the special register (using following instructions). * Store instruction (ST/SST instruction) * Bit manipulation instruction (SET1/CLR1/NOT1 instruction) <4> to <8> Insert NOP instructions (5 instructions)Note. [Description Example] When using PSC register (standby mode setting) ST.B r11,PSMR[r0] <1> MOV 0x02,r10 <2> ST.B r10,PRCMD[r0] <3> ST.B r10,PSC[r0] <4> NOPNote <5> NOP <7> NOP
Note
; PSMR register setting (IDLE, STOP mode setting) ; PRCMD register write ; PSC register setting ; Dummy instruction ; Dummy instruction ; Dummy instruction ; Dummy instruction ; Dummy instruction
<6> NOPNote
Note
<8> NOPNote (next instruction)
No special sequence is required to read special registers. Note When switching to the IDLE mode or the STOP mode (PSC.STP bit = 1), 5 NOP instructions must be inserted immediately after switching is performed. Cautions 1. Interrupts are not acknowledged for the store instruction for the PRCMD register. This is because continuous execution of store instructions by the program in steps <2> and <3> above is assumed. If another instruction is placed between step <2> and <3>, the above sequence may not be realized when an interrupt is acknowledged for that instruction, which may cause malfunction. 2. The data written to the PRCMD register is dummy data, but use the same register as the general-purpose register used for setting data to the special register (step <3>) when writing to the PRCMD register (step <2>). The same applies to when using a generalpurpose register for addressing.
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(2) Command register (PRCMD) The PRCMD register is an 8-bit register used to prevent data from being written to registers that may have a large influence on the system, possibly causing the application system to unexpectedly stop, when an inadvertent program loop occurs. Only the first write operation to the special register following the execution of a previously executed write operation to the PRCMD register, is valid. As a result, register values can be overwritten only using a preset sequence, preventing invalid write operations. This register can only be written in 8-bit units (if it is read, an undefined value is returned).
After reset: Undefined 7 PRCMD REG7 6
W
Address: FFFFF1FCH 5 REG5 4 REG4 3 REG3 2 REG2 1 REG1 0 REG0
REG6
(3) System status register (SYS) This register is allocated with status flags showing the operating state of the entire system. This register can be read or written in 8-bit or 1-bit units.
After reset: 00H
R/W
Address: FFFFF802H <>
SYS
0
0
0
0
0
0
0
PRERR
PRERR 0 1
Detection of protection error Protection error has not occurred Protection error has occurred
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The operation conditions of the PRERR flag are described below. (a) Set conditions (PRERR = 1) (i) When a write operation to the special register takes place without write operation being performed to the PRCMD register (when step <3> is performed without performing step <2> as described in 3.4.7 (1) Setting data to special registers). (ii) When a write operation (including bit manipulation instruction) to an on-chip peripheral I/O register other than a special register is performed following write to the PRCMD register (when <3> in 3.4.7 (1) Setting data to special registers is not a special register). Remark Regarding the special registers other than the WDTM register (PCC and PSC registers), even if on-chip peripheral I/O register read (except bit manipulation instruction) (internal RAM access, etc.) is performed in between write to the PRCMD register and write to a special register, the PRERR flag is not set and setting data can be written to the special register. (b) Clear conditions (PRERR = 0) (i) When 0 is written to the PRERR flag (ii) When system reset is performed Cautions 1. If 0 is written to the PRERR bit of the SYS register that is not a special register immediately following write to the PRCMD register, the PRERR bit becomes 0 (write priority). 2. If data is written to the PRCMD register that is not a special register immediately following write to the PRCMD register, the PRERR bit becomes 1.
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3.4.8 Cautions (1) Waits on register access Be sure to set the following register before using the V850ES/KE2. * System wait control register (VSWC) After setting the VSWC register, set the other registers as required. When using an external bus, set the VSWC register and then set the various pins to the control mode by setting the port-related registers. (a) System wait control register (VSWC) The VSWC register controls the bus access wait time for the on-chip peripheral I/O registers. Access to the on-chip peripheral I/O register lasts 3 clocks (during no wait), but in the V850ES/KE2, waits are required according to the internal system clock frequency. Set the values shown below to the VSWC register according to the internal system clock frequency that is used. This register can be read or written in 8-bit units (Address: FFFFF06EH, After reset: 77H).
Operation Conditions 4.5 V VDD 5.5 V Internal System Clock Frequency (fCLK) 32 kHz fCLK < 16.6 MHz 16.6 MHz fCLK 20 MHz 4.0 V VDD < 4.5 V 2.7 V VDD < 4.0 V 32 kHz fCLK 16 MHz 32 kHz fCLK < 8.3 MHz 8.3 MHz fCLK 10 MHz 00H 01H 00H 00H 01H 0 (no waits) 1 0 (no waits) 0 (no waits) 1 VSWC Register Setting Number of Waits
(b) Access to special on-chip peripheral I/O register This product has two types of internal system buses. One type is for the CPU bus and the other is for the peripheral bus to interface with low-speed peripheral hardware. Since the CPU bus clock and peripheral bus clock are asynchronous, if a conflict occurs during access between the CPU and peripheral hardware, illegal data may be passed unexpectedly. Therefore, when accessing peripheral hardware that may cause a conflict, the number of access cycles is changed so that the data is received/passed correctly in the CPU. As a result, the CPU does not shift to the next instruction processing and enters the wait status. When this wait status occurs, the number of execution clocks of the instruction is increased by the number of wait clocks. Note this with caution when performing real-time processing. When accessing a special on-chip peripheral I/O register, additional waits may be required further to the waits set by the VSWC register. The access conditions at that time and the method to calculate the number of waits to be inserted (number of CPU clocks) are shown below. Number of waits to be inserted = (2 + m) x k (clocks) Number of accesses to specific on-chip peripheral I/O register = 3 + m + (2 + m) x k (clocks)
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Peripheral Function Watchdog timer 1 (WDT1)
Register Name WDTM1 Write
Note
Access 1 to 5
k
>
fX: Main clock oscillation frequency Watchdog timer 2 (WDT2) 16-bit timer/event counter P0 (TMP0) WDTM2 TP0CCR0, TP0CCR1, TP0CNT 2 Note
Write Read
3 (fixed) 1
>
Write
Note
0 to 2
>
TMC01
Read-modify-write
1 (fixed) A wait occurs during write
I C0
IICS0
Read Read
1 (fixed) 1 (fixed)
Asynchronous serial interfaces 0 and 1 ASIS0, ASIS1 (UART0, UART1) Real-time output function 0 (RTO0) RTBL0, RTBH0
Write (when RTPC0.RTPOE0 bit = 0)
1
A/D converter
ADM, ADS, PFM, PFT ADCR, ADCRH
Write Read
Note
1 or 2 1 or 2
>
Note In the calculation of number of waits, the fractional part of its result must be multiplied by (1/fCPU) and rounded down if (1/fCPU)/(2 + m) or lower, and rounded up if (1/fCPU)/(2 + m) is exceeded. Cautions 1. If fetched from the internal ROM or internal RAM, the number of waits is as shown above. If fetched from the external memory, the number of waits may be decreased below these. The effect of the external memory access cycles varies depending on the wait settings and the like. However, the number of waits shown above is the maximum value, so no higher value is generated. 2. When the CPU operates on the subclock and no clock is input to the X1 pin, do not access a register in which a wait occurs. If a wait occurs, it can only be released by a reset. Remark In the calculation for the number of waits:
fCPU: CPU clock frequency
fXX: Main clock frequency m: Set value of bits 2 to 0 of the VSWC register When the VSWC register = 00H: m = 0 When the VSWC register = 01H: m = 1
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(2) Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of the instruction in <1> may not be stored in a register. Instruction <1> * ld instruction: * sld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu sld.b, sld.h, sld.w, sld.bu, sld.hu
* Multiplication instruction: mul, mulh, mulhi, mulu Instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 ld.w [r11], r10
* * *
not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2
satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2
satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2
If the decode operation of the mov instruction immediately before the sld instruction and an interrupt request conflict before execution of the ld instruction is complete, the execution result of instruction may not be stored in a register.
mov r10, r28 sld.w 0x28, r10 (b) Countermeasure <1> When compiler (CA850) is used Use CA850 Ver. 2.61 or later because generation of the corresponding instruction sequence can be automatically suppressed. <2> Countermeasure by assembler When executing the sld instruction immediately after instruction , avoid the above operation using either of the following methods. * Insert a nop instruction immediately before the sld instruction. * Do not use the same register as the sld instruction destination register in the above instruction executed immediately before the sld instruction.
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4.1 Features
Input-only ports: 8 pins I/O ports: 43 pins * Fixed to N-ch open-drain output: 2 * Switchable to N-ch open-drain output: 6 Input/output can be specified in 1-bit units
4.2 Basic Port Configuration
The V850ES/KE2 incorporates a total of 51 I/O port pins consisting of ports 0, 3 to 5, 7, 9, CM, and DL (including 8 input-only port pins). The port configuration is shown below.
P00 Port 0 P06 P30 Port 3 P35 P38 P39 P40 Port 4 P42 P50 Port 5 P55 P70 Port 7 P77
P90 P91 P96 P99 P913 P915 PCM0 PCM1 PDL0 Port DL PDL7 Port CM Port 9
Table 4-1. Pin I/O Buffer Power Supplies of V850ES/KE2
Power Supply AVREF0 EVDD Port 7 RESET, ports 0, 3 to 5, 9, CM, DL Corresponding Pins
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4.3 Port Configuration
Table 4-2. Port Configuration
Item Control registers Configuration Port n register (Pn: n = 0, 3 to 5, 7, 9, CM, DL) Port n mode register (PMn: n = 0, 3 to 5, 9, CM, DL) Port n mode control register (PMCn: n = 0, 3 to 5, 9, CM) Port n function control register (PFCn: n = 3, 5, 9) Port n function register (PFn: n = 3, 4, 9) Port 3 function control expansion register (PFCE3) Pull-up resistor option register (PUn: n = 0, 3 to 5, 9, CM, DL) Ports Input only: 8 I/O: 43 Pull-up resistors Software control: 41
(1) Port n register (Pn) Data I/O with external devices is performed by writing to and reading from the Pn register. The Pn register is configured of a port latch that retains the output data and a circuit that reads the pin status. Each bit of the Pn register corresponds to one pin of port n and can be read or written in 1-bit units.
After reset: 00HNote (output latch)
7 6 5
R/W
7 3 2 1 0
Pn
Pn7
Pn6
Pn5
Pn4
Pn3
Pn2
Pn1
Pn0
Pnm 0 1 0 is output 1 is output
Control of output data (in output mode)
Note Input-only port pins are undefined.
Writing to and reading from the Pn register are executed as follows depending on the setting of each register.
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Table 4-3. Reading to/Writing from Pn Register
Setting of PMCn Register Port mode (PMCnm bit = 0) Setting of PMn Register Output mode (PMnm bit = 0) Writing to Pn Register Write to the output latch from the pin. Input mode (PMnm bit = 1) Alternate-function mode (PMCnm bit = 1) Output mode (PMnm bit = 0) Write to the output latch
Note Note
Reading from Pn Register The value of the output latch is read.
.
The contents of the output latch are output
.
The pin status is read. * When alternate function is output The output status of the alternate function is read. * When alternate function is input The output latch value is read.
The status of the pin is not affected. Write to the output latch
Note
.
The status of the pin is not affected. The pin operates as an alternate-function pin.
Input mode (PMnm bit = 1)
Write to the output latch
Note
.
The pin status is read.
The status of the pin is not affected. The pin operates as an alternate-function pin.
Note The value written to the output latch is retained until a new value is written to the output latch. (2) Port n mode register (PMn) PMn specifies the input mode/output mode of the port. Each bit of the PMn register corresponds to one pin of port n and can be specified in 1-bit units.
After reset: FFH
R/W
PMn
PMn7
PMn6
PMn5
PMn4
PMn3
PMn2
PMn1
PMn0
PMnm 0 1 Output mode Input mode
Control of I/O mode
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(3) Port n mode control register (PMCn) PMCn specifies the port mode/alternate function. Each bit of the PMCn register corresponds to one pin of port n and can be specified in 1-bit units.
After reset: 00H
R/W
PMCn
PMCn7
PMCn6
PMCn5
PMCn4
PMCn3
PMCn2
PMCn1
PMCn0
PMCnm 0 1 Port mode
Specification of operation mode
Alternate function mode
(4) Port n function control register (PFCn) PFCn is a register that specifies the alternate function to be used when one pin has two or more alternate functions. Each bit of the PFCn register corresponds to one pin of port n and can be specified in 1-bit units.
After reset: 00H
R/W
PFCn
PFCn7
PFCn6
PFCn5
PFCn4
PFCn3
PFCn2
PFCn1
PFCn0
PFCnm 0 1 Alternate function 1 Alternate function 2
Specification of alternate function
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(5) Port n function control expansion register (PFCEn) PFCEn is a register that specifies the alternate function to be used when one pin has three or more alternate functions. Each bit of the PFCEn register corresponds to one pin of port n and can be specified in 1-bit units.
After reset: 00H
R/W
PFCEn
PFCEn7 PFCEn6
PFCEn5 PFCEn4
PFCEn3 PFCEn2
PFCEn1
PFCEn0
PFCn
PFCn7
PFCn6
PFCn5
PFCn4
PFCn3
PFCn2
PFCn1
PFCn0
PFCEnm 0 0 1 1
PFCnm 0 1 0 1
Specification of alternate function Alternate function 1 Alternate function 2 Alternate function 3 Alternate function 4
(6) Port n function register (PFn) PFn is a register that specifies normal output/N-ch open-drain output. Each bit of the PFn register corresponds to one pin of port n and can be specified in 1-bit units.
After reset: 00H
R/W
PFn
PFn7
PFn6
PFn5
PFn4
PFn3
PFn2
PFn1
PFn0
PFnmNote 0 1
Control of normal output/N-ch open-drain output Normal output (CMOS output) N-ch open-drain output
Note The PFnm bit is valid only when the PMn.PMnm bit is 0 (output mode) regardless of the setting of the PMCn register. When the PMnm bit is 1 (input mode), the set value in the PFn register is invalid. Example <1> When the value of the PFn register is valid PFnm bit = 1 ... N-ch open-drain output is specified. PMnm bit = 0 ... Output mode is specified. PMCnm bit = 0 or 1 <2> When the value of the PFn register is invalid PFnm bit = 0 ... N-ch open-drain output is specified. PMnm bit = 1 ... Input mode is specified. PMCnm bit = 0 or 1
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(7) Pull-up resistor option register (PUn) PUn is a register that specifies the connection of an on-chip pull-up resistor. Each bit of the PUn register corresponds to one pin of port n and can be specified in 1-bit units.
After reset: 00H
R/W
PUn
PUn7
PUn6
PUn5
PUn4
PUn3
PUn2
PUn1
PUn0
PUnm 0 1 Not connected Connected
Control of on-chip pull-up resistor connection
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(8) Port settings Set the ports as follows. Figure 4-1. Register Settings and Pin Functions
Port mode
Output mode Input mode
"0" PMn register "1"
Alternate function (when two alternate functions are available)
"0" "0" PFCn register PMCn register
Alternate function 1 Alternate function 2
"1"
Alternate function (when three or more alternate functions are available)
"1"
Alternate function 1 Alternate function 2 Alternate function 3
(a) (b) (c) PFCEn register (d) (a) (b) (c) (d) PFCn register PFCEnm 0 0 1 1 PFCnm 0 1 0 1
Alternate function 4
Remark
Switch to the alternate function using the following procedure. <1> Set the PFCn and PFCEn registers. <2> Set the PMCn register. <3> Set the INTRn or INTFn register (to specify an external interrupt pin). If the PMCn register is set first, an unintended function may be set while the PFCn and PFCEn registers are being set.
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4.3.1 Port 0 Port 0 is a 7-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate functions. Table 4-4. Alternate-Function Pins of Port 0
Pin No. 12 13 14 15 16 17 18 Pin Name P00 P01 P02 P03 P04 P05 P06 Alternate Function TOH0 TOH1 NMI INTP0 INTP1 INTP2 INTP3 I/O Output Output Input Input Input Input Input Analog/digital noise elimination Analog noise elimination PULL Yes
Note
Remark -
Block Type D0-U D0-U D1-SUIL D1-SUIL D1-SUIL D1-SUIL D1-SUIL
Note Software pull-up function Caution P02 to P06 have hysteresis characteristics when the alternate function is input, but not in the port mode. (1) Port 0 register (P0)
After reset: 00H (output latch)
R/W
Address: FFFFF400H
P0
0
P06
P05
P04
P03
P02
P01
P00
P0n 0 1 0 is output 1 is output
Control of output data (in output mode) (n = 0 to 6)
(2) Port 0 mode register (PM0)
After reset: FFH
R/W
Address: FFFFF420H
PM0
1
PM06
PM05
PM04
PM03
PM02
PM01
PM00
PM0n 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 6)
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(3) Port 0 mode control register (PMC0)
After reset: 00H
R/W
Address: FFFFF440H
PMC0
0
PMC06
PMC05
PMC04
PMC03
PMC02
PMC01
PMC00
PMC06 0 1 PMC05 0 1 PMC04 0 1 PMC03 0 1 PMC02 0 1 PMC01 0 1 PMC00 0 1 I/O port TOH0 output I/O port TOH1 output I/O port NMI input I/O port INTP0 input I/O port INTP1 input I/O port INTP2 input I/O port INTP3 input
Specification of P06 pin operation mode
Specification of P05 pin operation mode
Specification of P04 pin operation mode
Specification of P03 pin operation mode
Specification of P02 pin operation mode
Specification of P01 pin operation mode
Specification of P00 pin operation mode
(4) Pull-up resistor option register 0 (PU0)
After reset: 00H
R/W
Address: FFFFFC40H
PU0
0
PU06
PU05
PU04
PU03
PU02
PU01
PU00
PU0n 0 1
Control of on-chip pull-up resistor connection (n = 0 to 6) Not connected Connected
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4.3.2 Port 3 Port 3 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 3 includes the following alternate functions. Table 4-5. Alternate-Function Pins of Port 3
Pin No. 22 23 24 25 26 27 55 56 Pin Name P30 P31 P32 P33 P34 P35 P38 P39 Alternate Function TXD0 RXD0/INTP7 ASCK0/ADTRG/TO01 TIP00/TOP00 TIP01/TOP01 TI010/TO01 SDA0 SCL0 I/O Output Input I/O I/O I/O I/O I/O I/O No N-ch open-drain output PULL Yes
Note
Remark -
Block Type D-U D1-SUIHL E10-SUL Gxx10-SUL Gxx10-SUL E10-SUL D2-SNFH D2-SNFH
Note Software pull-up function Caution P31 to P35, P38, and P39 have hysteresis characteristics when the alternate function is input, but not in the port mode.
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(1) Port 3 register (P3)
After reset: 00H (output latch)
R/W
Address: P3 FFFFF406H, P3L FFFFF406H, P3H FFFFF407H
12 11 10 9 8
15
14
13
P3 (P3HNote)
0
0
0
0
0
0
P39
P38
(P3L)
0
0
P35
P34
P33
P32
P31
P30
P3n 0 1
Control of output data (in output mode) (n = 0 to 5, 8, 9) 0 is output 1 is output
Note When reading from or writing to bits 8 to 15 of the P3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the P3H register. Remark The P3 register can be read or written in 16-bit units. However, when the higher 8 bits and the lower 8 bits of the P3 register are used as the P3H register and as the P3L register, respectively, this register can be read or written in 8-bit or 1-bit units.
(2) Port 3 mode register (PM3)
After reset: FFFFH
R/W
Address: PM3 FFFFF426H, PM3L FFFFF426H, PM3H FFFFF427H
13 12 11 10 9 8
15
14
PM3 (PM3H
Note
)
1
1
1
1
1
1
PM39
PM38
(PM3L)
1
1
PM35
PM34
PM33
PM32
PM31
PM30
PM3n 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 5, 8, 9)
Note When reading from or writing to bits 8 to 15 of the PM3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PM3H register. Remark The PM3 register can be read or written in 16-bit units. When the higher 8 bits and the lower 8 bits of the PM3 register are used as the PM3H register and as the PM3L register, respectively, this register can be read or written in 8-bit or 1-bit units.
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(3) Port 3 mode control register (PMC3)
After reset: 0000H
R/W
Address: PMC3 FFFFF446H, PMC3L FFFFF446H, PMC3H FFFFF447H
13 12 11 10 9 8
15
14
PMC3 (PMC3H
Note 1
)
0
0
0
0
0
0
PMC39
PMC38
(PMC3L)
0
0
PMC35
PMC34
PMC33
PMC32
PMC31
PMC30
PMC39 0 1 PMC38 0 1 PMC35 0 1 PMC34 0 1 PMC33 0 1 PMC32 0 1 PMC31 0 1 PMC30 0 1 I/O port TXD0 output I/O port I/O port I/O port I/O port I/O port I/O port SDA0 I/O I/O port SCL0 I/O
Specification of P39 pin operation mode
Specification of P38 pin operation mode
Specification of P35 pin operation mode
TI010 input/TO01 output Specification of P34 pin operation mode
TIP01 input/TOP01 output Specification of P33 pin operation mode
TIP00 input/TOP00 output Specification of P32 pin operation mode
ASCK0 input/ADTRG input/TO01 output Specification of P31 pin operation mode
RXD0 input/INTP7 inputNote 2 Specification of P30 pin operation mode
Notes 1. When reading from or writing to bits 8 to 15 of the PMC3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PMC3H register. 2. The INTP7 and RXD0 pins are alternate-function pins. When using the pin as the RXD0 pin, disable edge detection of the alternate-function INTP7 pin (clear the INTF3.INTF31 and INTR3.INTR31 bits to 0). When using the pin as the INTP7 pin, stop the UART0 receive operation (clear the ASIM0.RXE0 bit to 0). Remark The PMC3 register can be read or written in 16-bit units. When the higher 8 bits and the lower 8 bits of the PMC3 register are used as the PMC3H register and as the PMC3L register, respectively, this register can be read or written in 8-bit or 1-bit units.
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(4) Port 3 function register H (PF3H)
After reset: 00H
R/W
Address: FFFFFC67H
PF3H
0
0
0
0
0
0
PF39
PF38
PF3n 0 1
Specification of normal port/alternate function (n = 8, 9) When used as normal port (N-ch open-drain output) When used as alternate-function (N-ch open-drain output)
Caution When using P38 and P39 as N-ch open-drain-output alternate-function pins, set in the following sequence. Be sure to set the port latch to 1 before setting the pin to N-ch open-drain output. P3n bit = 1 PF3n bit = 1 PMC3n bit = 1
(5) Port 3 function control register (PFC3)
After reset: 00H
R/W
Address: FFFFF466H
PFC3
0
0
PFC35
PFC34
PFC33
PFC32
0
0
Remark For details of specification of alternate-function pins, refer to 4.3.2 (7) Specifying alternate-function pins of port 3.
(6) Port 3 function control expansion register (PFCE3)
After reset: 00H
R/W
Address: FFFFF706H
PFCE3
0
0
0
PFCE34
PFCE33
0
0
0
Remark For details of specification of alternate-function pins, refer to 4.3.2 (7) Specifying alternate-function pins of port 3.
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(7) Specifying alternate-function pins of port 3
PFC35 0 1 TI010 input TO01 output Specification of Alternate-Function Pin of P35 Pin
PFCE34 0 0 1 1
PFC34 0 1 0 1
Specification of Alternate-Function Pin of P34 Pin Setting prohibited Setting prohibited TIP01 input TOP01 output
PFCE33 0 0 1 1
PFC33 0 1 0 1
Specification of Alternate-Function Pin of P33 Pin Setting prohibited Setting prohibited TIP00 input TOP00 output
PFC32 0 1
Specification of Alternate-Function Pin of P32 Pin ASCK0/ADTRG TO01 output
Note
input
Note The ASCK0 and ADTRG pins are alternate-function pins. When using the pin as the ASCK0 pin, disable the trigger input of the alternate-function ADTRG pin (clear the ADS.TRG bit to 0 or set the ADS.ADTMD bit to 1). When using the pin as the ADTRG pin, do not set the UART0 operation clock to external input (set the CKSR0.TPS03 to CKSR0.TPS00 bits to other than 1011). Caution When the P3n pin is specified as an alternate function by the PMC3.PMC3n bit with the PFC3n and PFCE3n bits maintaining the initial value (0), output becomes undefined. set the PMC3n bit to 1 (n = 3, 4). Therefore, to specify the P3n pin as an alternate function, set the PFC3n and PFCE3n bits to 1 first and then
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(8) Pull-up resistor option register 3 (PU3)
After reset: 00H
R/W
Address: FFFFFC46H
PU3
0
0
PU35
PU34
PU33
PU32
PU31
PU30
PU3n 0 1
Control of on-chip pull-up resistor connection (n = 0 to 5) Not connected Connected
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4.3.3 Port 4 Port 4 is a 3-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 4 includes the following alternate functions. Table 4-6. Alternate-Function Pins of Port 4
Pin No. 19 20 21 Pin Name P40 P41 P42 Alternate Function SI00 SO00 SCK00 I/O Input Output I/O PULL Yes
Note
Remark - N-ch open-drain output can be selected.
Block Type D1-SUL D0-UF D2-SUFL
Note Software pull-up function Caution P40 and P42 have hysteresis characteristics when the alternate function is input, but not in the port mode. (1) Port 4 register (P4)
After reset: 00H (output latch)
R/W
Address: FFFFF408H
P4
0
0
0
0
0
P42
P41
P40
P4n 0 1 0 is output 1 is output
Control of output data (in output mode) (n = 0 to 2)
(2) Port 4 mode register (PM4)
After reset: FFH
R/W
Address: FFFFF428H
PM4
1
1
1
1
1
PM42
PM41
PM40
PM4n 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 2)
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(3) Port 4 mode control register (PMC4)
After reset: 00H
R/W
Address: FFFFF448H
PMC4
0
0
0
0
0
PMC42
PMC41
PMC40
PMC42 0 1 PMC41 0 1 PMC40 0 1 I/O port SI00 input I/O port SO00 output I/O port SCK00 I/O
Specification of P42 pin operation mode
Specification of P41 pin operation mode
Specification of P40 pin operation mode
(4) Port 4 function register (PF4)
After reset: 00H
R/W
Address: FFFFFC68H
PF4
0
0
0
0
0
PF42
PF41
0
PF4n 0 1
Control of normal output/N-ch open-drain output (n = 1, 2) Normal output N-ch open-drain output
Caution When using P41 and P42 as N-ch open-drain-output alternate-function pins, set in the following sequence. Be sure to set the port latch to 1 before setting the pin to N-ch open-drain output. P4n bit = 1 PF4n bit = 1 PMC4n bit = 1
(5) Pull-up resistor option register 4 (PU4)
After reset: 00H
R/W
Address: FFFFFC48H
PU4
0
0
0
0
0
PU42
PU41
0
PU4n 0 1
Control of on-chip pull-up resistor connection (n = 1, 2) Not connected Connected
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4.3.4 Port 5 Port 5 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 5 includes the following alternate functions. Table 4-7. Alternate-Function Pins of Port 5
Pin No. 28 29 30 31 34 35 Pin Name P50 P51 P52 P53 P54 P55 Alternate Function TI011/RTP00/KR0 TI50/RTP01/KR1 TO50/RTP02/KR2 RTP03/KR3 RTP04/KR4 RTP05/KR5 I/O I/O I/O I/O I/O I/O I/O PULL Yes
Note
Remark -
Block Type E10-SULT E10-SULT E00-SUT Ex0-SUT Ex0-SUT Ex0-SUT
Note Software pull-up function (1) Port 5 register (P5)
After reset: 00H (output latch)
R/W
Address: FFFFF40AH
P5
0
0
P55
P54
P53
P52
P51
P50
P5n 0 1 0 is output 1 is output
Control of output data (in output mode) (n = 0 to 5)
(2) Port 5 mode register (PM5)
After reset: FFH
R/W
Address: FFFFF42AH
PM5
1
1
PM55
PM54
PM53
PM52
PM51
PM50
PM5n 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 5)
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(3) Port 5 mode control register (PMC5)
After reset: 00H
R/W
Address: FFFFF44AH
PMC5
0
0
PMC55
PMC54
PMC53
PMC52
PMC51
PMC50
PMC55 0 1 PMC54 0 1 PMC53 0 1 PMC52 0 1 PMC51 0 1 PMC50 0 1
Specification of P55 pin operation mode I/O port/KR5 input RTP05 output Specification of P54 pin operation mode I/O port/KR4 input RTP04 output Specification of P53 pin operation mode I/O port/KR3 input RTP03 output Specification of P52 pin operation mode I/O port/KR2 input TO50 output/RTP02 output Specification of P51 pin operation mode I/O port/KR1 input TI50 input/RTP01 output Specification of P50 pin operation mode I/O port/KR0 input TI011 input/RTP00 output
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(4) Port 5 function control register (PFC5) Caution When the P5n pin is specified as an alternate function by the PMC5.PMC5n bit with the PFC5n bit maintaining the initial value (0), output becomes undefined. Therefore, to specify the P5n pin as alternate function 2, set the PFC5n bit to 1 first and then set the PMC5n bit to 1 (n = 3 to 5).
After reset: 00H
R/W
Address: FFFFF46AH
PFC5
0
0
PFC55
PFC54
PFC53
PFC52
PFC51
PFC50
PFC55 1
Specification of alternate-function pin of P55 pin RTP05 output
PFC54 1 PFC53 1 PFC52 0 1 PFC51 0 1 PFC50 0 1 TI011 input TI50 input TO50 output
Specification of alternate-function pin of P54 pin RTP04 output Specification of alternate-function pin of P53 pin RTP03 output Specification of alternate-function pin of P52 pin
RTP02 output Specification of alternate-function pin of P51 pin
RTP01 output Specification of alternate-function pin of P50 pin
RTP00 output
(5) Pull-up resistor option register 5 (PU5)
After reset: 00H
R/W
Address: FFFFFC4AH
PU5
0
0
PU55
PU54
PU53
PU52
PU51
PU50
PU5n 0 1
Control of on-chip pull-up resistor connection (n = 0 to 5) Not connected Connected
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4.3.5 Port 7 Port 7 is an 8-bit input-only port for which all the pins are fixed to input. Port 7 includes the following alternate functions. Table 4-8. Alternate-Function Pins of Port 7
Pin No. 64 63 62 61 60 59 58 57 Pin Name P70 P71 P72 P73 P74 P75 P76 P77 Alternate Function ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 I/O Input Input Input Input Input Input Input Input PULL No
Note
Remark -
Block Type A-A A-A A-A A-A A-A A-A A-A A-A
Note Software pull-up function (1) Port 7 register (P7)
After reset: Undefined
R
Address: FFFFF40EH
P7
P77
P76
P75
P74
P73
P72
P71
P70
P7n 0 1 Input low level Input high level
Input data read (n = 0 to 7)
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4.3.6 Port 9 Port 9 is a 9-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate functions. Table 4-9. Alternate-Function Pins of Port 9
Pin No. 36 37 38 39 40 41 42 43 44 Pin Name P90 P91 P96 P97 P98 P99 P913 P914 P915 Alternate Function TXD1/KR6 RXD1/KR7 TI51/TO51 SI01 SO01 SCK01 INTP4 INTP5 INTP6 I/O I/O Input I/O Input Output I/O Input Input Input N-ch open-drain output can be specified. Analog noise elimination PULL Yes
Note
Remark -
Block Type Ex0-SUT Ex1-SUHT Ex0-SUT Ex1-SUL Ex0-UF Ex2-SUFL Ex1-SUILZ Ex1-SUILZ Ex1-SUILZ
Note Software pull-up function Caution P97, P99, and P913 to P915 have hysteresis characteristics when the alternate function is input, but not in the port mode.
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(1) Port 9 register (P9)
After reset: 00H (output latch)
R/W
Address: P9 FFFFF412H, P9L FFFFF412H, P9H FFFFF413H
12 11 10 9 8
15
14
13
P9 (P9HNote)
P915
P914
P913
0
0
0
P99
P98
(P9L)
P97
P96
0
0
0
0
P91
P90
P9n 0 1
Control of output data (in output mode) (n = 0, 1, 6 to 9, 13 to 15) 0 is output 1 is output
Note When reading from or writing to bits 8 to 15 of the P9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the P9H register. Remark The P9 register can be read or written in 16-bit units. However, when the higher 8 bits and the lower 8 bits of the P9 register are used as the P9H register and as the P9L register, respectively, these registers can be read or written in 8-bit or 1-bit units.
(2) Port 9 mode register (PM9)
After reset: FFFFH
R/W
Address: PM9 FFFFF432H, PM9L FFFFF432H, PM9H FFFFF433H
13 12 11 10 9 8
15
14
PM9 (PM9H
Note
)
PM915
PM914
PM913
1
1
1
PM99
PM98
(PM9L)
PM97
PM96
1
1
1
1
PM91
PM90
PM9n 0 1 Output mode Input mode
Control of I/O mode (n = 0, 1, 6 to 9, 13 to 15)
Note When reading from or writing to bits 8 to 15 of the PM9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PM9H register. Remark The PM9 register can be read or written in 16-bit units. However, when the higher 8 bits and the lower 8 bits of the PM9 register are used as the PM9H register and as the PM9L register, respectively, this register can be read or written in 8-bit or 1-bit units.
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(3) Port 9 mode control register (PMC9)
After reset: 0000H
R/W
Address: PMC9 FFFFF452H, PMC9L FFFFF452H, PMC9H FFFFF453H
13 12 11 10 9 8
15
14
PMC9 (PMC9HNote)
PMC915 PMC914 PMC913
0
0
0
PMC99
PMC98
(PMC9L)
PMC97
PMC96
0
0
0
0
PMC91
PMC90
PMC915 0 1 PMC914 0 1 PMC913 0 1 PMC99 0 1 PMC98 0 1 PMC97 0 1 PMC96 0 1 PMC91 0 1 PMC90 0 1 I/O port SI01 input I/O port SO01 output I/O port SCK01 I/O I/O port INTP4 input I/O port INTP5 input I/O port INTP6 input
Specification of P915 pin operation mode
Specification of P914 pin operation mode
Specification of P913 pin operation mode
Specification of P99 pin operation mode
Specification of P98 pin operation mode
Specification of P97 pin operation mode
Specification of P96 pin operation mode I/O port/TI51 input TO51 output Specification of P91 pin operation mode I/O port/KR7 input RXD1 input Specification of P90 pin operation mode I/O port/KR6 input TXD1 output
Note When reading from or writing to bits 8 to 15 of the PMC9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PMC9H register. Remark The PMC9 register can be read or written in 16-bit units. However, when the higher 8 bits and the lower 8 bits of the PMC9 register are used as the PMC9H register and as the PMC9L register, respectively, these registers can be read or written in 8-bit or 1-bit units.
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(4) Port 9 function register H (PF9H)
After reset: 00H
R/W
Address: FFFFFC73H
PF9H
0
0
0
0
0
0
PF99
PF98
PF9n 0 1
Control of normal output/N-ch open-drain output (n = 8, 9) Normal output N-ch open-drain output
Caution When using P98 and P99 as N-ch open-drain-output alternate-function pins, set in the following sequence. Be sure to set the port latch to 1 before setting the pin to N-ch open-drain output. P9n bit = 1 PFC9n bit = 0/1 PF9n bit = 1 PMC9n bit = 1
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(5) Port 9 function control register (PFC9) Caution When port 9 is specified as an alternate function by the PMC9.PMC9n bit with the PFC9n bit maintaining the initial value (0), output becomes undefined. Therefore, to specify port 9 as alternate function 2, set the PFC9n bit to 1 first and then set the PMC9n bit to 1 (n = 0, 1, 6 to 9, 13 to 15).
After reset: 0000H
R/W
Address: PFC9 FFFFF472H, PFC9L FFFFF472H, PFC9H FFFFF473H
13 12 11 10 9 8
15
14
PFC9 (PFC9HNote)
PFC915
PFC914
PFC913
0
0
0
PFC99
PFC98
(PFC9L)
PFC97
PFC96
0
0
0
0
PFC91
PFC90
PFC915 1 PFC914 1 PFC913 1 PFC99 1 PFC98 1 PFC97 1 PFC96 1 PFC91 1 PFC90 1 RXD1 input TO51 output SI01 input SCK01 I/O INTP4 input INTP5 input INTP6 input
Specification of alternate-function pin of P915 pin
Specification of alternate-function pin of P914 pin
Specification of alternate-function pin of P913 pin
Specification of alternate-function pin of P99 pin
Specification of alternate-function pin of P98 pin SO01 output Specification of alternate-function pin of P97 pin
Specification of alternate-function pin of P96 pin
Specification of alternate-function pin of P91 pin
Specification of alternate-function pin of P90 pin TXD1 output
Note When reading from or writing to bits 8 to 15 of the PFC9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PFC9H register. Remark The PFC9 register can be read or written in 16-bit units. However, when the higher 8 bits and the lower 8 bits of the PFC9 register are used as the PFC9H register and as the PFC9L register, respectively, these registers can be read or written in 8-bit or 1-bit units.
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(6) Pull-up resistor option register 9 (PU9)
After reset: 0000H
R/W
Address: PU9 FFFFFC52H, PU9L FFFFFC52H, PU9H FFFFFC53H
15
14
13
12
11
10
9
8
PU9 (PU9H
Note
)
PU915
PU914
PU913
0
0
0
PU99
PU98
(PU9L)
PU97
PU96
0
0
0
0
PU91
PU90
PU9n 0 1
Control of on-chip pull-up resistor connection (n = 0, 1, 6 to 9, 13 to 15) Not connected Connected
Note When reading from or writing to bits 8 to 15 of the PU9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PU9H register. Remark The PU9 register can be read or written in 16-bit units. However, when the higher 8 bits and the lower 8 bits of the PU9 register are used as the PU9H register and as the PU9L register, respectively, these registers can be read or written in 8-bit or 1-bit units.
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4.3.7 Port CM Port CM is a 2-bit I/O port for which I/O settings can be controlled in 1-bit units. Port CM includes the following alternate functions. Table 4-10. Alternate-Function Pins of Port CM
Pin No. 45 46 Pin Name PCM0 PCM1 CLKOUT Alternate Function - I/O - Output PULL Yes
Note
Remark -
Block Type C-U D0-U
Note Software pull-up function (1) Port CM register (PCM)
After reset: 00H (output latch)
R/W
Address: FFFFF00CH
PCM
0
0
0
0
0
0
PCM1
PCM0
PCMn 0 1 0 is output 1 is output
Control of output data (in output mode) (n = 0, 1)
(2) Port CM mode register (PMCM)
After reset: FFH
R/W
Address: FFFFF02CH
PMCM
1
1
1
1
1
1
PMCM1
PMCM0
PMCMn 0 1 Output mode Input mode
Control of I/O mode (n = 0, 1)
(3) Port CM mode control register (PMCCM)
After reset: 00H
R/W
Address: FFFFF04CH
PMCCM
0
0
0
0
0
0
PMCCM1
0
PMCCM1 0 1 I/O port CLKOUT output
Specification of PCM1 pin operation mode
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(4) Pull-up resistor option register CM (PUCM)
After reset: 00H
R/W
Address: FFFFFF4CH
PUCM
0
0
0
0
0
0
PUCM1
PUCM0
PUCMn 0 1
Control of on-chip pull-up resistor connection (n = 0, 1) Not connected Connected
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4.3.8 Port DL Port DL is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. Port DL includes the following alternate functions. Table 4-11. Alternate-Function Pins of Port DL
Pin No. 47 48 49 50 51 52 53 54 Pin Name PDL0 PDL1 PDL2 PDL3 PDL4 PDL5 PDL6 PDL7 Alternate Function - - - - - - - - I/O - - - - - - - - PULL Yes
Note
Remark -
Block Type C-U C-U C-U C-U C-U C-U C-U C-U
Note Software pull-up function
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(1) Port DL register (PDL)
After reset: 00H (output latch)
R/W
Address: FFFFF004H
PDL
PDL7
PDL6
PDL5
PDL4
PDL3
PDL2
PDL1
PDL0
PDLn 0 1 0 is output 1 is output
Control of output data (in output mode) (n = 0 to 7)
(2) Port DL mode register (PMDL)
After reset: FFH
R/W
Address: FFFFF024H
PMDL
PMDL7
PMDL6
PMDL5
PMDL4
PMDL3
PMDL2
PMDL1
PMDL0
PMDLn 0 1 Output mode Input mode
Control of I/O mode (n = 0 to 7)
(3) Pull-up resistor option register DL (PUDL)
After reset: 00H
R/W
Address: FFFFFF44H
PUDL
PUDL7
PUDL6
PUDL5
PUDL4
PUDL3
PUDL2
PUDL1
PUDL0
PUDLn 0 1
Control of on-chip pull-up resistor connection (n = 0 to 7) Not connected Connected
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4.4 Block Diagrams
Figure 4-2. Block Diagram of Type A-A
Internal bus
Pmn
RD A/D input signal
P-ch N-ch
Figure 4-3. Block Diagram of Type C-U
EVDD WRPU
PUmn WRPM
P-ch
PMmn WRPORT
Internal bus
Output latch (Pmn)
Pmn
Selector
Address
RD
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Figure 4-4. Block Diagram of Type D0-U
EVDD WRPU
PUmn WRPMC
P-ch
PMCmn WRPM
Internal bus
PMmn
Selector
WRPORT
Output signal of alternate function 1 Output latch (Pmn)
Pmn
Selector
Address
RD
Selector
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Figure 4-5. Block Diagram of Type D0-UF
EVDD WRPU
PUmn WRPF
P-ch
PFmn WRPMC
PMCmn WRPM
Internal bus
PMmn
EVDD
Selector
WRPORT
Output signal of alternate function 1 Output latch (Pmn)
P-ch Pmn N-ch
Selector
Selector
EVSS
Address
RD
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Figure 4-6. Block Diagram of Type D1-SUIL
EVDD WRPU
PUmn WRINTR
P-ch
INTRmnNote 1 WRINTF
INTFmnNote 1 WRPMC
Internal bus
PMCmn WRPM
PMmn
WRPORT
Output latch (Pmn)
Pmn
Selector
Selector
Note 2
Address
RD Input signal of alternate function 1 Detection of noise elimination edge
Notes 1. Refer to 17.4 External Interrupt Request Input Pins (NMI, INTP0 to INTP7). 2. There are no hysteresis characteristics in the port mode.
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Figure 4-7. Block Diagram of Type D1-SUIHL
EVDD WRPU
PUmn WRINTR
P-ch
INTRmnNote 1 WRINTF
INTFmnNote 1 WRPMC
Internal bus
PMCmn WRPM
PMmn
WRPORT
Output latch (Pmn)
Pmn
Selector
Selector
Note 2
Address
RD
Detection of noise Input signal of alternate function 1-2 elimination edge Input signal of alternate function 1-1
Notes 1. Refer to 17.4 External Interrupt Request Input Pins (NMI, INTP0 to INTP7). 2. There are no hysteresis characteristics in the port mode.
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Figure 4-8. Block Diagram of Type D1-SUL
EVDD WRPU
PUmn WRPMC
P-ch
Internal bus
PMCmn WRPM
PMmn WRPORT
Output latch (Pmn)
Pmn
Selector
Selector
Note
Address
RD Input signal of alternate function 1
Note There are no hysteresis characteristics in the port mode.
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Figure 4-9. Block Diagram of Type D2-SNFH
WRPF
PFmn WRPMC
PMCmn WRPM
Internal bus
PMmn Pmn
Selector
WRPORT
Output signal of alternate function 1 Output latch (Pmn)
N-ch
EVSS
Selector
Selector
Note
Address
RD
Input signal of alternate function 1
Note There are no hysteresis characteristics in the port mode.
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Figure 4-10. Block Diagram of Type D2-SUFL
EVDD WRPU
PUmn WRPF
P-ch
PFmn
WRPMC
Output enable signal of alternate function 1
PMCmn WRPM
Internal bus
PMmn
EVDD
WRPORT
Selector
Output signal of alternate function 1 Output latch (Pmn)
P-ch Pmn N-ch
Selector
Selector
Note
EVSS
Address
RD
Input signal of alternate function 1
Note There are no hysteresis characteristics in the port mode.
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Figure 4-11. Block Diagram of Type E00-SUT
EVDD WRPU
PUmn WRPFC
P-ch
PFCmn WRPMC
PMCmn WRPM
Internal bus
PMmn
Selector
WRPORT
Selector
Output signal of alternate function 2 Output signal of alternate function 1
Pmn
Output latch (Pmn)
Selector
RD Address
Alternate-function input signal in port mode
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Figure 4-12. Block Diagram of Type E10-SUL
EVDD WRPU
PUmn WRPFC
P-ch
PFCmn WRPMC
PMCmn WRPM
Internal bus
PMmn
WRPORT
Selector
Output signal of alternate function 2 Output latch (Pmn)
Pmn
Selector
Selector
Note
Address
RD Input signal of alternate function 1
Note There are no hysteresis characteristics in the port mode.
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Figure 4-13. Block Diagram of Type E10-SULT
EVDD WRPU
PUmn WRPFC
P-ch
PFCmn WRPMC
PMCmn WRPM
Internal bus
PMmn
Selector
Output signal of WRPORT alternate function 2
Pmn
Output latch (Pmn)
Selector
RD Address
Input signal of alternate function 1 Alternate-function input signal in port mode
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Figure 4-14. Block Diagram of Type Ex0-SUT
EVDD WRPU
PUmn WRPFC
P-ch
PFCmn WRPMC
PMCmn
Internal bus
WRPM PMmn Output signal of alternate function 2
WRPORT
Selector
Pmn
Output latch (Pmn)
Selector
RD Address
Alternate-function input signal in port mode
Selector
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Figure 4-15. Block Diagram of Type Ex0-UF
EVDD WRPU
PUmn WRPF
P-ch
PFmn WRPFC
PFCmn WRPMC
PMCmn WRPM
Internal bus
PMmn EVDD
Selector
Output signal of WRPORT alternate function 2
P-ch Pmn N-ch
Output latch (Pmn)
Selector
Selector
EVSS
Address
RD
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Figure 4-16. Block Diagram of Type Ex1-SUHT
EVDD WRPU
PUmn
P-ch
WRPFC
PFCmn WRPMC
PMCmn
Internal bus
WRPM
PMmn WRPORT
Output latch (Pmn)
Pmn
Selector
RD Address
Input signal of alternate function 2 Alternate-function input signal in port mode
Selector
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Figure 4-17. Block Diagram of Type Ex1-SUIL
EVDD WRPU
PUmn WRINTR
P-ch
INTRmnNote 1 WRINTF
INTFmnNote 1 WRPFC
PFCmn
Internal bus
WRPMC
PMCmn WRPM
PMmn WRPORT
Output latch (Pmn)
Pmn
Selector
Selector
Note 2
Address
RD
Input signal of alternate function 2
Detection of noise elimination edge
Notes 1. Refer to 17.4 External Interrupt Request Input Pins (NMI, INTP0 to INTP7). 2. There are no hysteresis characteristics in the port mode.
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Figure 4-18. Block Diagram of Type Ex1-SUL
EVDD WRPU
PUmn WRPFC
P-ch
PFCmn WRPMC
PMCmn WRPM
Internal bus
PMmn
WRPORT
Output latch (Pmn)
Pmn
Selector
RD Address
Input signal of alternate function 2
Selector
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Figure 4-19. Block Diagram of Type Ex2-SUFL
EVDD WRPU
PUmn WRPF
P-ch
PFmn
WRPFC
Output enable signal of alternate function 2
PFCmn WRPMC
Internal bus
PMCmn WRPM
PMmn EVDD
Selector
Output signal of WRPORT alternate function 2
P-ch Pmn N-ch
Output latch (Pmn)
Selector
EVSS
Selector
Note
Address
RD
Input signal of alternate function 2
Note There are no hysteresis characteristics in the port mode.
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Figure 4-20. Block Diagram of Type Gxx10-SUL
EVDD WRPU
PUmn WRPFCE
P-ch
PFCEmn WRPFC
PFCmn WRPMC
Internal bus
PMCmn WRPM
PMmn
WRPORT
Output signal of alternate function 4
Selector
Pmn
Output latch (Pmn)
Selector
Selector
Note
Address
RD Input signal of alternate function 3
Note There are no hysteresis characteristics in the port mode.
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4.5 Port Register Setting When Alternate Function Is Used
Table 4-12 shows the port register settings when each port is used for an alternate function. When using a port pin as an alternate-function pin, refer to description of each pin.
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Table 4-12. Settings When Port Pins Are Used for Alternate Functions (1/3)
Pin Name Alternate Function Function Name P00 P01 P02 P03 P04 P05
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Pnx Bit of Pn Register
PMnx Bit of PMn Register
PMCnx Bit of PMCn Register
PFCEnx Bit of PFCEn Register - - - - - - - - - - - - - PFCE33 = 1 PFCE33 = 1 PFCE34 = 1 PFCE34 = 1 - -
PFCnx Bit of PFCn Other Bits (Registers) Register - - - PFC03 = 0 - - - PFC30 = 0 Note 1, PFC31 = 0 Note 1, PFC31 = 0 Note 2, PFC32 = 0 Note 2, PFC32 = 0 PFC32 = 1 PFC33 = 0 PFC33 = 1 PFC34 = 0 PFC34 = 1 PFC35 = 0 PFC35 = 1 - - - - - - - - - - - - - - - - - - - CHAPTER 4 PORT FUNCTIONS
I/O Output Output Input Input Input Input Input Output Input Input Input Input Output Input Output Input Output Input Output P00 = Setting not required P01 = Setting not required P02 = Setting not required P03 = Setting not required P04 = Setting not required P05 = Setting not required P06 = Setting not required P30 = Setting not required P31 = Setting not required P31 = Setting not required P32 = Setting not required P32 = Setting not required P32 = Setting not required P33 = Setting not required P33 = Setting not required P34 = Setting not required P34 = Setting not required P35 = Setting not required P35 = Setting not required PM00 = Setting not required PM01 = Setting not required PM02 = Setting not required PM03 = Setting not required PM04 = Setting not required PM05 = Setting not required PM06 = Setting not required PM30 = Setting not required PM31 = Setting not required PM31 = Setting not required PM32 = Setting not required PM32 = Setting not required PM32 = Setting not required PM33 = Setting not required PM33 = Setting not required PM34 = Setting not required PM34 = Setting not required PM35 = Setting not required PM35 = Setting not required
TOH0 TOH1 NMI INTP0 INTP1 INTP2 INTP3 TXD0 RXD0 INTP7
PMC00 = 1 PMC01 = 1 PMC02 = 1 PMC03 = 1 PMC04 = 1 PMC05 = 1 PMC06 = 1 PMC30 = 1 PMC31 = 1 PMC31 = 1 PMC32 = 1 PMC32 = 1 PMC32 = 1 PMC33 = 1 PMC33 = 1 PMC34 = 1 PMC34 = 1 PMC35 = 1 PMC35 = 1
P06 P30 P31
P32
ASCK0 ADTRG TO01
P33
TIP00 TOP00
P34
TIP10 TOP10
P35
TI010 TO01
Notes 1. The INTP7 and RXD0 pins are alternate-function pins. When using the pin as the RXD0 pin, disable edge detection of the alternate-function INTP7 pin (clear the INTF3.INTF31 and INTR3.INTR31 bits to 0). When using the pin as the INTP7 pin, stop the UART0 receive operation (clear the ASIM0.RXE0 bit to 0). 2. The ASCK0 and ADTRG pins are alternate-function pins. When using the pin as the ASCK0 pin, disable the trigger input of the alternate-function ADTRG pin (clear the ADS.TRG bit to 0 or set the ADS.ADTMD bit to 1). When using the pin as the ADTRG pin, do not set the UART0 operation clock to external input (set the CKSR0.TPS03 to CKSR0.TPS00 bits to other than 1011).
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Pin Name Alternate Function Function Name P38 P39 P40 P41 P42 P50
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Table 4-12. Settings When Port Pins Are Used for Alternate Functions (2/3)
Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PMCn Register P38 = Setting not required P39 = Setting not required P40 = Setting not required P41 = Setting not required P42 = Setting not required P50 = Setting not required P50 = Setting not required P50 = Setting not required P51 = Setting not required P51 = Setting not required P51 = Setting not required P52 = Setting not required P52 = Setting not required P52 = Setting not required P53 = Setting not required P53 = Setting not required P54 = Setting not required P54 = Setting not required P55 = Setting not required P55 = Setting not required PM38 = Setting not required PM39 = Setting not required PM40 = Setting not required PM41 = Setting not required PM42 = Setting not required PM50 = Setting not required PM50 = Setting not required PM50 = 1 PM51 = Setting not required PM51 = Setting not required PM51 = 1 PM52 = Setting not required PM52 = Setting not required PM52 = 1 PM53 = Setting not required PM53 = 1 PM54 = Setting not required PM54 = 1 PM55 = Setting not required PM55 = 1 PMC38 = 1 PMC39 = 1 PMC40 = 1 PMC41 = 1 PMC42 = 1 PMC50 = 1 PMC50 = 1 PMC50 = 0 PMC51 = 1 PMC51 = 1 PMC51 = 0 PMC52 = 1 PMC52 = 1 PMC52 = 0 PMC53 = 1 PMC53 = 0 PMC54 = 1 PMC54 = 0 PMC55 = 1 PMC55 = 0 PFC50 = 0 PFC50 = 1 PFC50 = Setting not required KRM0 (KRM) = 1 PFC51 = 0 PFC51 = 1 PFC51 = Setting not required KRM1 (KRM) = 1 PFC52 = 0 PFC52 = 1 PFC52 = Setting not required KRM2 (KRM) = 1 PFC53 = 1 PFC53 = Setting not required KRM3 (KRM) = 1 PFC54 = 1 PF54 (PF5) = 0 - - - - - PFC40 = 0 PFC41 = 0 - PFCnx Bit of PFCn Register - - PF38 (PF3H) = 1 PF39 (PF3H) = 1 - PF41 (PF4) = Don't care PF42 (PF4) = Don't care - - Other Bits (Registers)
I/O I/O I/O Input Output I/O Input Output Input Input Output Input Output Output Input Output Input Output Input Output Input
SDA0 SCL0 SI00 SO00 SCK00 TI011 RTP00 KR0
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P51
TI50 RTP01 KR1
P52
TO50 RTP02 KR2
P53
RTP03 KR3
P54
RTP04 KR4
PFC54 = Setting not required PF54 (PF5) = 0, KRM4 (KRM) = 1 PFC55 = 1 PF55 (PF5) = 0
P55
RTP05 KR5
PFC55 = Setting not required PF55 (PF5) = 0, KRM5 (KRM) = 1
Table 4-12. Settings When Port Pins Are Used for Alternate Functions (3/3)
Pin Name Alternate Function Function Name P70 P71 P72 P73 P74 P75 P76 P77 P90
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Pnx Bit of Pn Register
PMnx Bit of PMn Register
PMCnx Bit of PMCn Register
PFCnx Bit of PFCn Register - - - - - - - - PFC90 = 1
Other Bits (Registers)
I/O Input Input Input Input Input Input Input Input Output Input Input Input Input Output Input Output I/O Input Input Input Output P70 = Setting not required P71 = Setting not required P72 = Setting not required P73 = Setting not required P74 = Setting not required P75 = Setting not required P76 = Setting not required P77 = Setting not required P90 = Setting not required P90 = Setting not required P91 = Setting not required P91 = Setting not required P96 = Setting not required P96 = Setting not required P97 = Setting not required P98 = Setting not required P99 = Setting not required - - - - - - - - PM90 = Setting not required PM90 = 1 PM91 = Setting not required PM91 = 1 PM96 = 1 PM96 = Setting not required PM97 = Setting not required PM98 = Setting not required PM99 = Setting not required
ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 TXD1 KR6
- - - - - - - - PMC90 = 1 PMC90 = 0 PMC91 = 1 PMC91 = 0 PMC96 = 0 PMC96 = 1 PMC97 = 1 PMC98 = 1 PMC99 = 1
- - - - - - -
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- -
PFC90 = Setting not required KRM6 (KRM) = 1 PFC91 = 1 PFC91 = Setting not required KRM7 (KRM) = 1 PFC96 = Setting not required PFC96 = 1 PFC97 = 1 PFC98 = 1 PFC99 = 1 PFC913 = 1 PFC914 = 1 PFC915 = 1 - - - - PF98 (PF9) = Don't care PF99 (PF9) = Don't care - - - - -
P91
RXD1 KR7
P96
TI51 TO51
P97 P98 P99 P913 P914 P915 PCM1
SI01 SO01 SCK01 INTP4 INTP5 INTP6 CLKOUT
P913 = Setting not required PM913 = Setting not required PMC913 = 1 P914 = Setting not required PM914 = Setting not required P915 = Setting not required PM915 = Setting not required PMC914 = 1 PMC915 = 1
PCM1 = Setting not required PMCM1 = Setting not required PMCCM1 = 1
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4.6 Cautions
4.6.1 Cautions on bit manipulation instruction for port n register (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode. When PDL0 is an output port, PDL1 to PDL7 are input ports (all pin statuses are high level), and the value of the port latch is 00H, if the output of output port PDL0 is changed from low level to high level via a bit manipulation instruction, the value of the port latch is FFH. Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output latch and pin status, respectively. A bit manipulation instruction is executed in the following order in the V850ES/KE2. <1> The Pn register is read in 8-bit units. <2> The targeted one bit is manipulated. <3> The Pn register is written in 8-bit units. In step <1>, the value of the output latch (0) of PDL0, which is an output port, is read, while the pin statuses of PDL1 to PDL7, which are input ports, are read. If the pin statuses of PDL1 to PDL7 are high level at this time, the read value is FEH. The value is changed to FFH by the manipulation in <2>. FFH is written to the output latch by the manipulation in <3>. Figure 4-21. Bit Manipulation Instruction (PDL0)
PDL0 Low-level output PDL1 to PDL7 Pin status: High level Port DL latch 0 0 0 0 0 0 0 0
Bit manipulation instruction (set1 0, PDL[r0]) is executed for PDL0 bit.
PDL0 Low-level output PDL1 to PDL7 Pin status: High level Port DL latch 1 1 1 1 1 1 1 1
Bit manipulation instruction for PDL0 bit <1> The PDL register is read in 8-bit units. * In the case of PDL0, an output port, the value of the port latch (0) is read. * In the case of PDL1 to PDL7, input ports, the pin status (1) is read. <2> Set PDL0 bit to 1. <3> Write the results of <2> to the output latch of the PDL register in 8-bit units.
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4.6.2 Hysteresis characteristics In port mode, the following ports do not have hysteresis characteristics. P02 to P06 P31 to P35, P38, P39 P40, P42 P97, P99, P913 to P915
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CHAPTER 5 CLOCK GENERATION FUNCTION
5.1 Overview
The following clock generation functions are available. Main clock oscillator * fX = 2 to 5 MHz (fXX = 8 to 20 MHz: 4.5 V VDD 5.5 V) * fX = 2 to 4 MHz (fXX = 8 to 16 MHz: 4.0 V VDD 5.5 V) * fX = 2 to 2.5 MHz (fXX = 8 to 10 MHz: 2.7 V VDD 5.5 V) * fX = 2 to 10 MHz (fXX = 2 to 10 MHz: 2.7 V VDD 5.5 V) Subclock oscillator * fXT = 32.768 kHz Multiplication (x4) function by PLL (Phase Locked Loop) * Clock-through mode/PLL mode selectable * Usable voltage: VDD = 2.7 to 5.5 V Internal system clock generation * 7 steps (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT) Peripheral clock generation Clock output function Remark fX: Main clock oscillation frequency fXX: Main clock frequency fXT: Subclock frequency
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5.2 Configuration
Figure 5-1. Clock Generator
FRC bit XT1 XT2 Subclock oscillator fXT fXT fBRG = fX/2 to fX/212 Interval timer BRG MCK MFRC bit bit X1 X2 Main clock oscillator Main clock oscillator stop control STOP mode SELPLL bit fX IDLE control CK2 to CK0 bits
Selector
Watch timer clock, watchdog timer clock Watch timer clock
IDLE mode
PLLON bit
IDLE mode
CLS bit, CK3 bit
PLL
IDLE fXX control
Prescaler 2 fXX/32 fXX/16 fXX/8 fXX/4 fXX/2 fXX HALT mode
Selector Selector
HALT fCPU control fCLK
CPU clock Internal system clock
IDLE mode
Prescaler 1
fXX to fXX/1024 Peripheral clock, watchdog timer 2 clock fXW Watchdog timer 1 clock
IDLE control CLKOUT Port CM
Remark
fX: fXX: fXT:
Main clock oscillation frequency Main clock frequency Subclock frequency
fCLK: Internal system clock frequency fCPU: CPU clock frequency fBRG: Watch timer clock frequency fXW: Watchdog timer 1 clock frequency
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(1) Main clock oscillator The main clock oscillator oscillates the following frequencies (fX): * fX = 2 to 5 MHz (VDD = 4.5 to 5.5 V, in PLL mode) * fX = 2 to 4 MHz (VDD = 4.0 to 5.5 V, in PLL mode) * fX = 2 to 2.5 MHz (VDD = 2.7 to 5.5 V, in PLL mode) * fX = 2 to 10 MHz (VDD = 2.7 to 5.5 V, in clock through mode) (2) Subclock oscillator The subclock oscillator oscillates a frequency of 32.768 kHz (fXT). (3) Main clock oscillator stop control This circuit generates a control signal that stops oscillation of the main clock oscillator. Oscillation of the main clock oscillator is stopped in the STOP mode or when the PCC.MCK bit = 1 (valid only when the PCC.CLS bit = 1). (4) Prescaler 1 This prescaler generates the clock (fXX to fXX/1024) to be supplied to the following on-chip peripheral functions: TMP0, TM01, TM50, TM51, TMH0, TMH1, CSI00, CSI01, UART0, UART1, I2C0, ADC, and WDT2 (5) Prescaler 2 This circuit divides the main clock (fXX). The clock generated by prescaler 2 (fXX to fXX/32) is supplied to the selector that generates the CPU clock (fCPU) and internal system clock (fCLK). fCLK is the clock supplied to the INTC, ROM, and RAM blocks, and can be output from the CLKOUT pin. (6) Interval timer BRG This circuit divides the clock (fX) generated by the main clock oscillator to a specific frequency (32.768 kHz) and supplies that clock to the watch timer block. For details, refer to CHAPTER 10 INTERVAL TIMER, WATCH TIMER. (7) PLL This circuit multiplies the clock (fX) generated by the main clock oscillator. It operates in two modes: clock-through mode in which fX is output as is, and PLL mode in which a multiplied clock is output. These modes can be selected by using the PLLCTL.SELPLL bit. Operation of the PLL can be started or stopped by the PLLCTL.PLLON bit.
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5.3 Registers
(1) Processor clock control register (PCC) The PCC register is a special register. Data can be written to this register only in combination of specific sequences (refer to 3.4.7 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 03H. (1/2)
After reset: 03H R/W <> PCC FRC MCK MFRC After reset: FFFFF828H <> CLS
Note
<> CK3 CK2 CK1 CK0
FRC 0 1 Used Not used
Use of subclock on-chip feedback resistor
MCK 0 1 Oscillation enabled Oscillation stopped
Control of main clock oscillator
* Even if the MCK bit is set to 1 while the system is operating with the main clock as the CPU clock, the operation of the main clock does not stop. It stops after the CPU clock has been changed to the subclock. * When the main clock is stopped and the device is operating on the subclock, clear the MCK bit to 0 and wait until the oscillation stabilization time has been secured by the program before switching back to the main clock.
MFRC 0 1 Used Not used
Use of main clock on-chip feedback resistor
CLSNote 0 1 Main clock operation Subclock operation
Status of CPU clock (fCPU)
Note The CLS bit is a read-only bit.
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(2/2)
CK3 0 0 0 0 0 0 0 1 CK2 0 0 0 0 1 1 1 x CK1 0 0 1 1 0 0 1 x CK0 0 1 0 1 0 1 x x fXX fXX/2 fXX/4 fXX/8 (default value) fXX/16 fXX/32 Setting prohibited fXT Clock selection (fCLK/fCPU)
Cautions 1. Do not change the CPU clock (by using the CK3 to CK0 bits) while CLKOUT is being output. 2. Use a bit manipulation instruction to manipulate the CK3 bit. When using an 8-bit manipulation instruction, do not change the set values of the CK2 to CK0 bits. 3. When the CPU operates on the subclock and no clock is input to the X1 pin, do not access a register in which a wait occurs (refer to 3.4.8 (1) (b) Access to special on-chip peripheral I/O register for details of the access methods). If a wait occurs, it can only be released by a reset. Remark x: don't care
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(a) Example of setting main clock operation subclock operation <1> CK3 bit 1: Use of a bit manipulation instruction is recommended. Do not change the CK2 to CK0 bits. <2> Subclock operation: Read the CLS bit to check if subclock operation has started. It takes the following time after the CK3 bit is set until subclock operation is started. Max.: 1/fXT (1/subclock frequency) <3> MCK bit 1: Set the MCK bit to 1 only when stopping the main clock.
Cautions 1. When stopping the main clock, stop the PLL. 2. If the following conditions are not satisfied, change the CK2 to CK0 bits so that the conditions are satisfied, then change to the subclock operation mode. Internal system clock (fCLK) > Subclock (fXT: 32.768 kHz) x 4 Remark Internal system clock (fCLK): Clock generated from the main clock (fXX) by setting bits CK2 to CK0 [Description example] <1> _SET_SUB_RUN : st.b set1 tst1 bz st.b set1 Remark r0, PRCMD[r0] 3, PCC[r0] 4, PCC[r0] _CHECK_CLS r0, PRCMD[r0] 6, PCC[r0] -- MCK bit 1, main clock is stopped -- CK3 bit 1 -- Wait until subclock operation starts.
<2> _CHECK_CLS :
<3> _STOP_MAIN_CLOCK :
The above description is an example. Note with caution that the CLS bit is read in a closed loop in <2>.
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(b) Example of setting subclock operation main clock operation <1> MCK bit 0: <3> CK3 bit 0: <4> Main clock operation: Main clock starts oscillating Use of a bit manipulation instruction is recommended. Do not change the CK2 to CK0 bits. It takes the following time after the CK3 bit is set until main clock operation is started. Max.: 1/fXT (1/subclock frequency) Therefore, insert one NOP instruction immediately after setting the CK3 bit to 0 or read the CLS bit to check if main clock operation has started. [Description example] <1> _START_MAIN_OSC : st.b clr1 <2> movea _WAIT_OST : nop nop nop addi mp bne <3> st.b clr1 tst1 bnz Remark -1, r11, r11 r0, r11 _PROGRAM_WAIT r0, PRCMD[r0] 3, PCC[r0] 4, PCC[r0] _CHECK_CLS The above description is an example. Note with caution that the CLS bit is read in a closed loop in <4>. -- CK3 0 -- Wait until main clock operation starts r0, PRCMD[r0] 6, PCC[r0] 0x55, r0, r11 -- Release of protection of special registers -- Main clock starts oscillating -- Wait for oscillation stabilization time <2> Insert waits by the program and wait until the oscillation stabilization time of the main clock elapses.
<4> _CHECK_CLS :
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5.4 Operation
5.4.1 Operation of each clock The following table shows the operation status of each clock. Table 5-1. Operation Status of Each Clock
Register Setting and Operation Status CLS bit = 0, MCK bit = 0 During reset Target Clock Main clock oscillator (fX) Subclock oscillator (fXT) CPU clock (fCPU) Internal system clock (fCLK) Peripheral clock (fXX to fXX/1024) WT clock (main) WT clock (sub) WDT1 clock (fXW) WDT2 clock (main) WDT2 clock (sub) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
During oscillation stabilization time count
PCC Register CLS bit = 1, MCK bit = 0 HALT mode IDLE mode STOP mode x CLS bit = 1, MCK bit = 1
Subclock Sub-IDLE Subclock Sub-IDLE mode mode mode x mode x
Remark
O: Operable x: Stopped
5.4.2 Clock output function The clock output function is used to output the internal system clock (fCLK) from the CLKOUT pin. The internal system clock (fCLK) is selected by using the PCC.CK3 to PCC.CK0 bits. The CLKOUT pin functions alternately as the PCM1 pin and functions as a clock output pin if so specified by the control register of port CM. The status of the CLKOUT pin is the same as the internal system clock in Table 5-1 and the pin can output the clock when it is in the operable status. It outputs a low level in the stopped status. However, the port mode (PCM1: input mode) is selected until the CLKOUT pin output is set after reset. Consequently, the CLKOUT pin goes into a high-impedance state. 5.4.3 External clock input function An external clock can be directly input to the oscillator. Input the clock to the X1 pin and its inverse signal to the X2 pin. Set the PCC.MFRC bit to 1 (on-chip feedback resistor not used). Note, however, that oscillation stabilization time is inserted even in the external clock mode.
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5.5 PLL Function
5.5.1 Overview The PLL function is used to output the operating clock of the CPU and on-chip peripheral function at a frequency 4 times higher than the oscillation frequency, and select the clock-through mode. When PLL function is used: Input clock = 2 to 5 MHz (fXX: 8 to 20 MHz) Clock-through mode: 5.5.2 Register (1) PLL control register (PLLCTL) The PLLCTL register is an 8-bit register that controls the security function of PLL and RTO. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 01H. Input clock = 2 to 10 MHz (fXX: 2 to 10 MHz)
After reset: 01H
R/W
Address: FFFFF806H <> <>
Note
<> PLLON
PLLCTL
0
0
0
0
0
RTOST0
SELPLL
PLLON 0 1 PLL stopped PLL operating
PLL operation control
SELPLL 0 1 Clock-through operation PLL operation
PLL clock selection
Note For the RTOST0 bit, refer to CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO). Caution Be sure to clear bits 4 to 7 to "0". Changing bit 3 does not affect the operation.
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5.5.3 Usage (1) When PLL is used * After reset has been released, the PLL operates (PLLCTL.PLLON bit = 1), but because the default mode is the clock-through mode (PLLCTL.SELPLL bit = 0), select the PLL mode (SELPLL bit = 1). * To set the STOP mode in which the main clock is stopped, or to set the IDLE mode, first select the clockthrough mode and then stop the PLL. To return from the IDLE or STOP mode, first enable PLL operation (PLLON bit = 1), and then select the PLL mode (SELPLL bit = 1). * To enable the PLL operation, first set the PLLON bit to 1, wait for 200 s, and then set the SELPLL bit to 1. To stop the PLL, first select the clock-through mode (SELPLL bit = 0), wait for 8 clocks or more, and then stop the PLL (PLLON bit = 0). (2) When PLL is not used * The clock-through mode (SELPLL bit = 0) is selected after reset has been released, but the PLL is operating (PLLON bit = 1) and must therefore be stopped (PLLON bit = 0). Remark The PLL is operable in the IDLE mode. To realize low power consumption, stop the PLL. Be sure to stop the PLL when shifting to the STOP mode.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
Timer P (TMP) is a 16-bit timer/event counter.
6.1 Overview
An outline of TMP0 is shown below. * Clock selection: 8 ways * Capture trigger input pins: 2 * External event count input pins: 1 * External trigger input pins: 1 * Timer/counters: 1 * Capture/compare registers: 2 * Capture/compare match interrupt request signals: 2 * Timer output pins: 2
6.2 Functions
TMP0 has the following functions. * Interval timer * External event counter * External trigger pulse output * One-shot pulse output * PWM output * Free-running timer * Pulse width measurement
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6.3 Configuration
TMP0 includes the following hardware. Table 6-1. Configuration of TMP0
Item Timer register Registers 16-bit counter TMP0 capture/compare registers 0, 1 (TP0CCR0, TP0CCR1) TMP0 counter read buffer register (TP0CNT) CCR0, CCR1 buffer registers Timer inputs Timer outputs Control registers 2 (TIP00
Note
Configuration
, TIP01 pins)
2 (TOP00, TOP01 pins) TMP0 control registers 0, 1 (TP0CTL0, TP0CTL1) TMP0 I/O control registers 0 to 2 (TP0IOC0 to TP0IOC2) TMP0 option register 0 (TP0OPT0)
Note The TIP00 pin functions alternately as a capture trigger input signal, external event count input signal, and external trigger input signal. Figure 6-1. Block Diagram of TMP0
Internal bus
Output controller
fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128
TP0CNT
Selector
Selector
16-bit counter Clear
INTTP0OV TOP00 TOP01
Edge detector
CCR0 buffer register
CCR1 buffer register
INTTP0CC0 INTTP0CC1
TIP00 TIP01
Digital noise eliminator
Edge detector
TP0CCR0 TP0CCR1
Internal bus
Remark
fXX: Main clock frequency
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(1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TP0CNT register. When the TP0CTL0.TP0CE bit = 0, the value of the 16-bit counter is FFFFH. If the TP0CNT register is read at this time, 0000H is read. Reset sets the TP0CE bit to 0. Therefore, the 16-bit counter is set to FFFFH. (2) CCR0 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TP0CCR0 register is used as a compare register, the value written to the TP0CCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTP0CC0) is generated. The CCR0 buffer register cannot be read or written directly. The CCR0 buffer register is cleared to 0000H after reset, as the TP0CCR0 register is cleared to 0000H. (3) CCR1 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TP0CCR1 register is used as a compare register, the value written to the TP0CCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTP0CC1) is generated. The CCR1 buffer register cannot be read or written directly. The CCR1 buffer register is cleared to 0000H after reset, as the TP0CCR1 register is cleared to 0000H. (4) Edge detector This circuit detects the valid edges input to the TIP00 and TIP01 pins. No edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the TP0IOC1 and TP0IOC2 registers. (5) Output controller This circuit controls the output of the TOP00 and TOP01 pins. The output controller is controlled by the TP0IOC0 register. (6) Selector This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event can be selected as the count clock. (7) Digital noise eliminator This circuit is valid only when the TIP0a pin is used as a capture trigger input pin. This circuit is controlled by the TIP0a noise elimination register (PaNFC). Remark a = 0, 1
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6.4 Registers
(1) TMP0 control register 0 (TP0CTL0) The TP0CTL0 register is an 8-bit register that controls the operation of TMP0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TP0CTL0 register by software.
After reset: 00H
<7>
R/W 6 0
Address: FFFFF5A0H 5 0 4 0 3 0 2 1
0
TP0CTL0
TP0CE
TP0CKS2 TP0CKS1 TP0CKS0
TP0CE 0 1
TMP0 operation control TMP0 operation disabled (TMP0 reset asynchronouslyNote). TMP0 operation enabled. TMP0 operation started.
TP0CKS2 TP0CKS1 TP0CKS0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128
Internal count clock selection
Note TP0OPT0.TP0OVF bit, 16-bit counter, timer output (TOP00, TOP01 pins) Cautions 1. Set the TP0CKS2 to TP0CKS0 bits when the TP0CE bit = 0. When the value of the TP0CE bit is changed from 0 to 1, the TP0CKS2 to TP0CKS0 bits can be set simultaneously. 2. Be sure to clear bits 3 to 6 to "0". Remark fXX: Main clock frequency
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(2) TMP0 control register 1 (TP0CTL1) The TP0CTL1 register is an 8-bit register that controls the operation of TMP0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
After reset: 00H
7
R/W <6> TP0EST
Address: FFFFF5A1H <5> TP0EEE 4 0 3 0 2 1
0
TP0CTL1
0
TP0MD2 TP0MD1 TP0MD0
TP0EST 0 1
Software trigger control - Generate a valid signal for external trigger input. * In one-shot pulse output mode: A one-shot pulse is output with writing 1 to the TP0EST bit as the trigger. * In external trigger pulse output mode: A PWM waveform is output with writing 1 to the TP0EST bit as the trigger.
TP0EEE 0
Count clock selection Disable operation with external event count input. (Perform counting with the count clock selected by the TP0CTL0.TP0CK0 to TP0CTL0.TP0CK2 bits.) Enable operation with external event count input. (Perform counting at the valid edge of the external event count input signal.)
1
The TP0EEE bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input.
TP0MD2 TP0MD1 TP0MD0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Timer mode selection Interval timer mode External event count mode External trigger pulse output mode One-shot pulse output mode PWM output mode Free-running timer mode Pulse width measurement mode Setting prohibited
Cautions 1. The TP0EST bit is valid only in the external trigger pulse output mode or one-shot pulse output mode. In any other mode, writing 1 to this bit is ignored. 2. External event count input is selected in the external event count mode regardless of the value of the TP0EEE bit. 3. Set the TP0EEE and TP0MD2 to TP0MD0 bits when the TP0CTL0.TP0CE bit = 0. (The same value can be written when the TP0CE bit = 1.) The operation is not guaranteed when rewriting is performed with the TP0CE bit = 1. If rewriting was mistakenly performed, clear the TP0CE bit to 0 and then set the bits again. 4. Be sure to clear bits 3, 4, and 7 to "0".
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(3) TMP0 I/O control register 0 (TP0IOC0) The TP0IOC0 register is an 8-bit register that controls the timer output (TOP00, TOP01 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
After reset: 00H
7
R/W 6 0
Address: FFFFF5A2H 5 0 4 0 3 <2> 1 TP0OL0
<0>
TP0IOC0
0
TP0OL1 TP0OE1
TP0OE0
TP0OL1 0 1
TOP01 pin output level setting TOP01 pin output inversion disabled TOP01 pin output inversion enabled
TP0OE1 0
TOP01 pin output setting Timer output disabled * When TP0OL1 bit = 0: Low level is output from the TOP01 pin * When TP0OL1 bit = 1: High level is output from the TOP01 pin Timer output enabled (a square wave is output from the TOP01 pin).
1
TP0OL0 0 1
TOP00 pin output level setting TOP00 pin output inversion disabled TOP00 pin output inversion enabled
TP0OE0 0
TOP00 pin output setting Timer output disabled * When TP0OL0 bit = 0: Low level is output from the TOP00 pin * When TP0OL0 bit = 1: High level is output from the TOP00 pin Timer output enabled (a square wave is output from the TOP00 pin).
1
Cautions 1. Rewrite the TP0OL1, TP0OE1, TP0OL0, and TP0OE0 bits when the TP0CTL0.TP0CE bit = 0. (The same value can be written when the TP0CE bit = 1.) set the bits again. 2. Even if the TP0OLa bit is manipulated when the TP0CE and TP0OEa bits are 0, the TOP0a pin output level varies (a = 0, 1). If rewriting was mistakenly performed, clear the TP0CE bit to 0 and then
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(4) TMP0 I/O control register 1 (TP0IOC1) The TP0IOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIP00, TIP01 pins). This register can be read or written in 8-bit units. Reset sets this register to 00H.
After reset: 00H
7
R/W 6 0
Address: FFFFF5A3H 5 0 4 0 3 TP0IS3 2 TP0IS2 1 TP0IS1
0
TP0IOC1
0
TP0IS0
TP0IS3 0 0 1 1
TP0IS2 0 1 0 1
Capture trigger input signal (TIP01 pin) valid edge setting No edge detection (capture operation invalid) Detection of rising edge Detection of falling edge Detection of both edges
TP0IS1 0 0 1 1
TP0IS0 0 1 0 1
Capture trigger input signal (TIP00 pin) valid edge setting No edge detection (capture operation invalid) Detection of rising edge Detection of falling edge Detection of both edges
Cautions 1. Rewrite
the
TP0IS3
to
TP0IS0
bits
when
the
TP0CTL0.TP0CE bit = 0. (The same value can be written when the TP0CE bit = 1.) again. 2. The TP0IS3 to TP0IS0 bits are valid only in the freerunning timer mode and the pulse width measurement mode. In all other modes, a capture operation is not possible. If rewriting was mistakenly performed, clear the TP0CE bit to 0 and then set the bits
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(5) TMP0 I/O control register 2 (TP0IOC2) The TP0IOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIP00 pin) and external trigger input signal (TIP00 pin). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
After reset: 00H
7
R/W 6 0
Address: FFFFF5A4H 5 0 4 0 3 2 1
0
TP0IOC2
0
TP0EES1 TP0EES0 TP0ETS1 TP0ETS0
TP0EES1 TP0EES0 External event count input signal (TIP00 pin) valid edge setting 0 0 1 1 0 1 0 1 No edge detection (external event count invalid) Detection of rising edge Detection of falling edge Detection of both edges
TP0ETS1 TP0ETS0 0 0 1 1 0 1 0 1
External trigger input signal (TIP00 pin) valid edge setting No edge detection (external trigger invalid) Detection of rising edge Detection of falling edge Detection of both edges
Cautions 1. Rewrite the TP0EES1, TP0EES0, TP0ETS1, and TP0ETS0 bits when the TP0CTL0.TP0CE bit = 0. (The same value can be written when the TP0CE bit = 1.) If rewriting was mistakenly performed, clear the TP0CE bit to 0 and then set the bits again. 2. The TP0EES1 and TP0EES0 bits are valid only when the TP0CTL1.TP0EEE bit = 1 or when the external event count mode (TP0CTL1.TP0MD2 to TP0CTL1.TP0MD0 bits = 001) has been set. 3. The TP0ETS1 and TP0ETS0 bits are valid only when the external trigger pulse output mode (TP0MD2 to TP0MD0 bits = 010) or the one-shot pulse output mode (TP0MD2 to TP0MD0 bits = 011) is set.
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(6) TMP0 option register 0 (TP0OPT0) The TP0OPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
After reset: 00H
7
R/W 6 0
Address: FFFFF5A5H 5 4 3 0 2 0 1 0
<0>
TP0OPT0
0
TP0CCS1 TP0CCS0
TP0OVF
TP0CCS1 0 1
TP0CCR1 register capture/compare selection Compare register selected Capture register selected
The TP0CCS1 bit setting is valid only in the free-running timer mode.
TP0CCS0 0 1
TP0CCR0 register capture/compare selection Compare register selected Capture register selected
The TP0CCS0 bit setting is valid only in the free-running timer mode.
TP0OVF Set (1) Reset (0)
TMP0 overflow detection flag Overflow occurred TP0OVF bit 0 written or TP0CTL0.TP0CE bit = 0
* The TP0OVF bit is reset when the 16-bit counter count value overflows from FFFFH to 0000H in the free-running timer mode or the pulse width measurement mode. * An interrupt request signal (INTTP0OV) is generated at the same time that the TP0OVF bit is set to 1. The INTTP0OV signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. * The TP0OVF bit is not cleared even when the TP0OVF bit or the TP0OPT0 register are read when the TP0OVF bit = 1. * The TP0OVF bit can be both read and written, but the TP0OVF bit cannot be set to 1 by software. Writing 1 has no influence on the operation of TMP0.
Cautions 1. Rewrite the TP0CCS1 and TP0CCS0 bits when the TP0CE bit = 0. (The same value can be written when the TP0CE bit = 1.) If rewriting was mistakenly performed, clear the TP0CE bit to 0 and then set the bits again. 2. Be sure to clear bits 1 to 3, 6, and 7 to "0".
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(7) TMP0 capture/compare register 0 (TP0CCR0) The TP0CCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TP0OPT0.TP0CCS0 bit. In the pulse width measurement mode, the TP0CCR0 register can be used only as a capture register. In any other mode, this register can be used only as a compare register. The TP0CCR0 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TP0CCR0 register is disabled during subclock operation with the main clock stopped. For details, refer to 3.4.8 (1) (b).
After reset: 0000H
15 14
R/W 13 12
Address: FFFFF5A6H 11 10 9 8 7 6 5 4 3 2
1 0
TP0CCR0
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(a) Function as compare register The TP0CCR0 register can be rewritten even when the TP0CTL0.TP0CE bit = 1. The set value of the TP0CCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTP0CC0) is generated. If TOP00 pin output is enabled at this time, the output of the TOP00 pin is inverted. When the TP0CCR0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, or PWM output mode, the value of the 16-bit counter is cleared (0000H) if its count value matches the value of the CCR0 buffer register. (b) Function as capture register When the TP0CCR0 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TP0CCR0 register if the valid edge of the capture trigger input pin (TIP00 pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the TP0CCR0 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIP00 pin) is detected. Even if the capture operation and reading the TP0CCR0 register conflict, the correct value of the TP0CCR0 register can be read. The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 6-2. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
Operation Mode Interval timer External event counter External trigger pulse output One-shot pulse output PWM output Free-running timer Pulse width measurement Capture/Compare Register Compare register Compare register Compare register Compare register Compare register Capture/compare register Capture register How to Write Compare Register Anytime write Anytime write Batch write Anytime write Batch write Anytime write -
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(8) TMP0 capture/compare register 1 (TP0CCR1) The TP0CCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TP0OPT0.TP0CCS1 bit. In the pulse width measurement mode, the TP0CCR1 register can be used only as a capture register. In any other mode, this register can be used only as a compare register. The TP0CCR1 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TP0CCR1 register is disabled during subclock operation with the main clock stopped. For details, refer to 3.4.8 (1) (b).
After reset: 0000H
15 14
R/W 13 12
Address: FFFFF5A8H 11 10 9 8 7 6 5 4 3 2
1 0
TP0CCR1
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(a) Function as compare register The TP0CCR1 register can be rewritten even when the TP0CTL0.TP0CE bit = 1. The set value of the TP0CCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTP0CC1) is generated. If TOP01 pin output is enabled at this time, the output of the TOP01 pin is inverted. (b) Function as capture register When the TP0CCR1 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TP0CCR1 register if the valid edge of the capture trigger input pin (TIP01 pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the TP0CCR1 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIP01 pin) is detected. Even if the capture operation and reading the TP0CCR1 register conflict, the correct value of the TP0CCR1 register can be read. The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 6-3. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
Operation Mode Interval timer External event counter External trigger pulse output One-shot pulse output PWM output Free-running timer Pulse width measurement Capture/Compare Register Compare register Compare register Compare register Compare register Compare register Capture/compare register Capture register How to Write Compare Register Anytime write Anytime write Batch write Anytime write Batch write Anytime write -
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(9) TMP0 counter read buffer register (TP0CNT) The TP0CNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TP0CTL0.TP0CE bit = 1, the count value of the 16-bit timer can be read. This register is read-only, in 16-bit units. The value of the TP0CNT register is cleared to 0000H when the TP0CE bit = 0. If the TP0CNT register is read at this time, the value of the 16-bit counter (FFFFH) is not read, but 0000H is read. The value of the TP0CNT register is cleared to 0000H after reset, as the TP0CE bit is cleared to 0. Caution Accessing the TP0CNT register is disabled during subclock operation with the main clock stopped. For details, refer to 3.4.8 (1) (b).
After reset: 0000H
15 14
R 13 12
Address: FFFFF5AAH 11 10 9 8 7 6 5 4 3 2
1 0
TP0CNT
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6.5 Operation
TMP0 can perform the following operations.
Operation TP0CTL1.TP0EST Bit TIP00 Pin Capture/Compare Register Setting Compare only Compare only Compare only Compare only Compare only Switching enabled Capture only Compare Register Write Anytime write Anytime write Batch write Anytime write Batch write Anytime write Not applicable
(Software Trigger Bit) (External Trigger Input) Interval timer mode External event count mode
Note 1
Invalid Invalid
Note 2
Invalid Invalid Valid Valid Invalid Invalid Invalid
External trigger pulse output mode One-shot pulse output mode PWM output mode Free-running timer mode Pulse width measurement mode
Note 2
Valid Valid Invalid Invalid
Note 2
Invalid
Notes 1. To use the external event count mode, specify that the valid edge of the TIP00 pin capture trigger input is not detected (by clearing the TP0IOC1.TP0IS1 and TP0IOC1.TP0IS0 bits to "00"). 2. When using the external trigger pulse output mode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the TP0CTL1.TP0EEE bit to 0).
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6.5.1 Interval timer mode (TP0MD2 to TP0MD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTP0CC0) is generated at the specified interval if the TP0CTL0.TP0CE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOP00 pin. Usually, the TP0CCR1 register is not used in the interval timer mode. Figure 6-2. Configuration of Interval Timer
Clear
Count clock selection
16-bit counter Match signal
Output controller
TOP00 pin
INTTP0CC0 signal
TP0CE bit
CCR0 buffer register
TP0CCR0 register
Figure 6-3. Basic Timing of Operation in Interval Timer Mode
FFFFH 16-bit counter 0000H TP0CE bit TP0CCR0 register TOP00 pin output INTTP0CC0 signal Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) D0 D0 D0 D0 D0
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When the TP0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOP00 pin is inverted. Additionally, the set value of the TP0CCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, the output of the TOP00 pin is inverted, and a compare match interrupt request signal (INTTP0CC0) is generated. The interval can be calculated by the following expression. Interval = (Set value of TP0CCR0 register + 1) x Count clock cycle Figure 6-4. Register Setting for Interval Timer Mode Operation (1/2)
(a) TMP0 control register 0 (TP0CTL0)
TP0CE TP0CTL0 0/1 0 0 0 0 TP0CKS2 TP0CKS1 TP0CKS0 0/1 0/1 0/1
Select count clock 0: Stop counting 1: Enable counting
(b) TMP0 control register 1 (TP0CTL1)
TP0EST TP0EEE TP0CTL1 0 0 0/1
Note
TP0MD2 TP0MD1 TP0MD0 0 0 0 0 0 0, 0, 0: Interval timer mode 0: Operate on count clock selected by TP0CKS0 to TP0CKS2 bits 1: Count with external event count input signal
(c) TMP0 I/O control register 0 (TP0IOC0)
TP0OL1 TP0IOC0 0 0 0 0 0/1 TP0OE1 TP0OL0 0/1 0/1 TP0OE0 0/1 0: Disable TOP00 pin output 1: Enable TOP00 pin output Setting of output level with operation of TOP00 pin disabled 0: Low level 1: High level 0: Disable TOP01 pin output 1: Enable TOP01 pin output Setting of output level with operation of TOP01 pin disabled 0: Low level 1: High level
Note This bit can be set to 1 only when the interrupt request signals (INTTP0CC0 and INTTP0CC1) are masked by the interrupt mask flags (TP0CCMK0 and TP0CCMK1) and timer output (TOP01) is performed at the same time. However, set the TP0CCR0 and TP0CCR1 registers to the same value (refer to 6.5.1 (2) (d) Operation of TP0CCR1 register).
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Figure 6-4. Register Setting for Interval Timer Mode Operation (2/2)
(d) TMP0 counter read buffer register (TP0CNT) By reading the TP0CNT register, the count value of the 16-bit counter can be read. (e) TMP0 capture/compare register 0 (TP0CCR0) If the TP0CCR0 register is set to D0, the interval is as follows. Interval = (D0 + 1) x Count clock cycle (f) TMP0 capture/compare register 1 (TP0CCR1) Usually, the TP0CCR1 register is not used in the interval timer mode. However, the set value of the TP0CCR1 register is transferred to the CCR1 buffer register. A compare match interrupt request signal (INTTP0CC1) is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. Therefore, mask the interrupt request by using the corresponding interrupt mask flag (TP0CCMK1). Remark TMP0 I/O control register 1 (TP0IOC1), TMP0 I/O control register 2 (TP0IOC2), and TMP0 option register 0 (TP0OPT0) are usually not used in the interval timer mode. However, set the TP0IOC2 register to use the external event count input.
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(1) Interval timer mode operation flow Figure 6-5. Software Processing Flow in Interval Timer Mode
FFFFH 16-bit counter 0000H TP0CE bit TP0CCR0 register TOP00 pin output INTTP0CC0 signal D0 D0 D0 D0
<1>
<2>
<1> Count operation start flow
START
Register initial setting TP0CTL0 register (TP0CKS0 to TP0CKS2 bits) TP0CTL1 register, TP0IOC0 register, TP0CCR0 register
Initial setting of these registers is performed before setting the TP0CE bit to 1.
TP0CE bit = 1
The TP0CKS0 to TP0CKS2 bits can be set at the same time when counting has been started (TP0CE bit = 1).
<2> Count operation stop flow
The counter is initialized and counting is stopped by clearing the TP0CE bit to 0.
TP0CE bit = 0
STOP
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(2) Interval timer mode operation timing (a) Operation if TP0CCR0 register is cleared to 0000H If the TP0CCR0 register is cleared to 0000H, the INTTP0CC0 signal is generated at each count clock, and the output of the TOP00 pin is inverted. The value of the 16-bit counter is always 0000H.
Count clock 16-bit counter TP0CE bit TP0CCR0 register TOP00 pin output INTTP0CC0 signal Interval time Interval time Interval time Count clock cycle Count clock cycle Count clock cycle 0000H FFFFH 0000H 0000H 0000H 0000H
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(b) Operation if TP0CCR0 register is set to FFFFH If the TP0CCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTP0CC0 signal is generated and the output of the TOP00 pin is inverted. At this time, an overflow interrupt request signal (INTTP0OV) is not generated, nor is the overflow flag (TP0OPT0.TP0OVF bit) set to 1.
FFFFH 16-bit counter 0000H TP0CE bit TP0CCR0 register TOP00 pin output INTTP0CC0 signal Interval time Interval time Interval time 10000H x 10000H x 10000H x count clock cycle count clock cycle count clock cycle FFFFH
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(c) Notes on rewriting TP0CCR0 register To change the value of the TP0CCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TP0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
FFFFH D1 16-bit counter 0000H TP0CE bit TP0CCR0 register TP0OL0 bit TOP00 pin output INTTP0CC0 signal L D1 D2 D2 D1 D2 D2
Interval time (1)
Interval time (NG)
Interval time (2)
Remark
Interval time (1): (D1 + 1) x Count clock cycle Interval time (NG): (10000H + D2 + 1) x Count clock cycle Interval time (2): (D2 + 1) x Count clock cycle
If the value of the TP0CCR0 register is changed from D1 to D2 while the count value is greater than D2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TP0CCR0 register has been rewritten. Consequently, the value of the 16-bit counter that is compared is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D2, the INTTP0CC0 signal is generated and the output of the TOP00 pin is inverted. Therefore, the INTTP0CC0 signal may not be generated at the interval time "(D1 + 1) x Count clock cycle" or "(D2 + 1) x Count clock cycle" originally expected, but may be generated at an interval of "(10000H + D2 + 1) x Count clock period".
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(d) Operation of TP0CCR1 register Figure 6-6. Configuration of TP0CCR1 Register
TP0CCR1 register
CCR1 buffer register Match signal Clear
Output controller
TOP01 pin
INTTP0CC1 signal
Count clock selection
16-bit counter Match signal
Output controller
TOP00 pin
INTTP0CC0 signal
TP0CE bit
CCR0 buffer register
TP0CCR0 register
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If the set value of the TP0CCR1 register is less than the set value of the TP0CCR0 register, the INTTP0CC1 signal is generated once per cycle. At the same time, the output of the TOP01 pin is inverted. The TOP01 pin outputs a square wave with the same cycle as that output by the TOP00 pin. Figure 6-7. Timing Chart When D01 D11
FFFFH D01 16-bit counter 0000H TP0CE bit TP0CCR0 register TOP00 pin output INTTP0CC0 signal TP0CCR1 register TOP01 pin output INTTP0CC1 signal D11 D01 D11 D11 D01 D11 D01 D11 D01
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If the set value of the TP0CCR1 register is greater than the set value of the TP0CCR0 register, the count value of the 16-bit counter does not match the value of the TP0CCR1 register. INTTP0CC1 signal is not generated, nor is the output of the TOP01 pin changed. Figure 6-8. Timing Chart When D01 < D11 Consequently, the
FFFFH D01 16-bit counter 0000H TP0CE bit TP0CCR0 register TOP00 pin output INTTP0CC0 signal TP0CCR1 register TOP01 pin output INTTP0CC1 signal L D11 D01 D01 D01 D01
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6.5.2 External event count mode (TP0MD2 to TP0MD0 bits = 001) In the external event count mode, the valid edge of the external event count input is counted when the TP0CTL0.TP0CE bit is set to 1, and an interrupt request signal (INTTP0CC0) is generated each time the specified number of edges have been counted. The timer output (TOP00, TOP01 pins) cannot be used. Usually, the TP0CCR1 register is not used in the external event count mode. Figure 6-9. Configuration in External Event Count Mode
Clear TIP00 pin (external event count input)
Edge detector
16-bit counter Match signal
INTTP0CC0 signal
TP0CE bit
CCR0 buffer register
TP0CCR0 register
Figure 6-10. Basic Timing in External Event Count Mode
FFFFH 16-bit counter 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal External event count interval (D0 + 1) External event count interval (D0 + 1) External event count interval (D0 + 1) D0 D0 D0 D0
16-bit counter External event count input (TIP00 pin input) TP0CCR0 register INTTP0CC0 signal
D0 - 1
D0
0000
0001
D0
Remark
This figure shows the basic timing when the rising edge is specified as the valid edge of the external event count input.
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When the TP0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TP0CCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, and a compare match interrupt request signal (INTTP0CC0) is generated. The INTTP0CC0 signal is generated each time the valid edge of the external event count input has been detected (set value of TP0CCR0 register + 1) times. Figure 6-11. Register Setting for Operation in External Event Count Mode (1/2)
(a) TMP0 control register 0 (TP0CTL0)
TP0CE TP0CTL0 0/1 0 0 0 0 TP0CKS2 TP0CKS1 TP0CKS0 0 0 0 0: Stop counting 1: Enable counting
(b) TMP0 control register 1 (TP0CTL1)
TP0EST TP0EEE TP0CTL1 0 0 0 0 0 TP0MD2 TP0MD1 TP0MD0 0 0 1 0, 0, 1: External event count mode
(c) TMP0 I/O control register 0 (TP0IOC0)
TP0OL1 TP0IOC0 0 0 0 0 0 TP0OE1 TP0OL0 0 0 TP0OE0 0 0: Disable TOP00 pin output 0: Disable TOP01 pin output
(d) TMP0 I/O control register 2 (TP0IOC2)
TP0EES1 TP0EES0 TP0ETS1 TP0ETS0 TP0IOC2 0 0 0 0 0/1 0/1 0 0
Select valid edge of external event count input
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Figure 6-11. Register Setting for Operation in External Event Count Mode (2/2)
(e) TMP0 counter read buffer register (TP0CNT) The count value of the 16-bit counter can be read by reading the TP0CNT register. (f) TMP0 capture/compare register 0 (TP0CCR0) If D0 is set to the TP0CCR0 register, the counter is cleared and a compare match interrupt request signal (INTTP0CC0) is generated when the number of external event counts reaches (D0 + 1). (g) TMP0 capture/compare register 1 (TP0CCR1) Usually, the TP0CCR1 register is not used in the external event count mode. However, the set value of the TP0CCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTP0CC1) is generated. Therefore, mask the interrupt signal by using the interrupt mask flag (TP0CCMK1). Remark TMP0 I/O control register 1 (TP0IOC1) and TMP0 option register 0 (TP0OPT0) are not used in the external event count mode.
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(1) External event count mode operation flow Figure 6-12. Flow of Software Processing in External Event Count Mode
FFFFH 16-bit counter 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal D0 D0 D0 D0
<1>
<2>
<1> Count operation start flow
START
Register initial setting TP0CTL0 register (TP0CKS0 to TP0CKS2 bits) TP0CTL1 register, TP0IOC0 register, TP0IOC2 register, TP0CCR0 register
Initial setting of these registers is performed before setting the TP0CE bit to 1.
TP0CE bit = 1
The TP0CKS0 to TP0CKS2 bits can be set at the same time when counting has been started (TP0CE bit = 1).
<2> Count operation stop flow
The counter is initialized and counting is stopped by clearing the TP0CE bit to 0.
TP0CE bit = 0
STOP
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(2) Operation timing in external event count mode Cautions 1. In the external event count mode, do not set the TP0CCR0 and TP0CCR1 registers to 0000H. 2. In the external event count mode, use of the timer output is disabled. If performing timer output using external event count input, set the interval timer mode, and select the operation enabled by the external event count input for the count clock (TP0CTL1.TP0MD2 to TP0CTL1.TP0MD0 bits = 000, TP0CTL1.TP0EEE bit = 1). (a) Operation if TP0CCR0 register is set to FFFFH If the TP0CCR0 register is set to FFFFH, the 16-bit counter counts to FFFFH each time the valid edge of the external event count signal has been detected. TP0OPT0.TP0OVF bit is not set. The 16-bit counter is cleared to 0000H in synchronization with the next count-up timing, and the INTTP0CC0 signal is generated. At this time, the
FFFFH 16-bit counter 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal External event count signal interval External event count signal interval External event count signal interval FFFFH
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(b) Notes on rewriting the TP0CCR0 register To change the value of the TP0CCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TP0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
FFFFH D1 16-bit counter 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal D1 D2 D2 D1 D2 D2
External event count signal interval (1) (D1 + 1)
External event count signal interval (NG) (10000H + D2 + 1)
External event count signal interval (2) (D2 + 1)
If the value of the TP0CCR0 register is changed from D1 to D2 while the count value is greater than D2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TP0CCR0 register has been rewritten. Consequently, the value that is compared with the 16-bit counter is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D2, the INTTP0CC0 signal is generated. Therefore, the INTTP0CC0 signal may not be generated at the valid edge count of "(D1 + 1) times" or "(D2 + 1) times" originally expected, but may be generated at the valid edge count of "(10000H + D2 + 1) times".
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(c) Operation of TP0CCR1 register Figure 6-13. Configuration of TP0CCR1 Register
TP0CCR1 register
CCR1 buffer register Match signal Clear
INTTP0CC1 signal
TIP00 pin
Edge detector
16-bit counter Match signal
INTTP0CC0 signal
TP0CE bit
CCR0 buffer register
TP0CCR0 register
If the set value of the TP0CCR1 register is smaller than the set value of the TP0CCR0 register, the INTTP0CC1 signal is generated once per cycle. Figure 6-14. Timing Chart When D01 D11
FFFFH D01 16-bit counter 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal TP0CCR1 register INTTP0CC1 signal D11 D01 D11 D11 D01 D11 D01 D11 D01
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If the set value of the TP0CCR1 register is greater than the set value of the TP0CCR0 register, the INTTP0CC1 signal is not generated because the count value of the 16-bit counter and the value of the TP0CCR1 register do not match. Figure 6-15. Timing Chart When D01 < D11
FFFFH D01 16-bit counter 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal TP0CCR1 register INTTP0CC1 signal L D11 D01 D01 D01 D01
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6.5.3 External trigger pulse output mode (TP0MD2 to TP0MD0 bits = 010) In the external trigger pulse output mode, 16-bit timer/event counter P waits for a trigger when the TP0CTL0.TP0CE bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event counter P starts counting, and outputs a PWM waveform from the TOP01 pin. Pulses can also be output by generating a software trigger instead of using the external trigger. When using a software trigger, a square wave that has one cycle of the PWM waveform as half its cycle can also be output from the TOP00 pin. Figure 6-16. Configuration in External Trigger Pulse Output Mode
TP0CCR1 register TIP00 pin Edge detector CCR1 buffer register Software trigger generation Match signal Clear Count clock selection Count start control Transfer Output S controller R (RS-FF) TOP01 pin
INTTP0CC1 signal
16-bit counter Match signal
Output controller
TOP00 pin
INTTP0CC0 signal
TP0CE bit
CCR0 buffer register Transfer TP0CCR0 register
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Figure 6-17. Basic Timing in External Trigger Pulse Output Mode
FFFFH D0 16-bit counter 0000H TP0CE bit External trigger input (TIP00 pin input) TP0CCR0 register INTTP0CC0 signal TOP00 pin output (software trigger) TP0CCR1 register INTTP0CC1 signal TOP01 pin output Wait Active level for width (D1) trigger Cycle (D0 + 1) Active level width (D1) Cycle (D0 + 1) Active level width (D1) Cycle (D0 + 1) D1 D0 D1 D1 D0 D1 D0 D1 D0
16-bit timer/event counter P waits for a trigger when the TP0CE bit is set to 1. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOP01 pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and restarted. (The output of the TOP00 pin is inverted. The TOP01 pin outputs a high level regardless of the status (high/low) when a trigger occurs.) The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TP0CCR1 register) x Count clock cycle Cycle = (Set value of TP0CCR0 register + 1) x Count clock cycle Duty factor = (Set value of TP0CCR1 register)/(Set value of TP0CCR0 register + 1) The compare match interrupt request signal INTTP0CC0 is generated when the 16-bit counter counts next time after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal INTTP0CC1 is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. The value set to the TP0CCRa register is transferred to the CCRa buffer register when the count value of the 16-bit counter matches the value of the CCRa buffer register and the 16-bit counter is cleared to 0000H. The valid edge of an external trigger input signal, or setting the software trigger (TP0CTL1.TP0EST bit) to 1 is used as the trigger. Remark a = 0, 1
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Figure 6-18. Setting of Registers in External Trigger Pulse Output Mode (1/2)
(a) TMP0 control register 0 (TP0CTL0)
TP0CE TP0CTL0 0/1 0 0 0 0 TP0CKS2 TP0CKS1 TP0CKS0 0/1 0/1 0/1
Select count clockNote 0: Stop counting 1: Enable counting
Note The setting is invalid when the TP0CTL1.TP0EEE bit = 1. (b) TMP0 control register 1 (TP0CTL1)
TP0EST TP0EEE TP0CTL1 0 0/1 0/1 0 0 TP0MD2 TP0MD1 TP0MD0 0 1 0 0, 1, 0: External trigger pulse output mode 0: Operate on count clock selected by TP0CKS0 to TP0CKS2 bits 1: Count with external event input signal Generate software trigger when 1 is written
(c) TMP0 I/O control register 0 (TP0IOC0)
TP0OL1 TP0IOC0 0 0 0 0 0/1 TP0OE1 TP0OL0 0/1 0/1 TP0OE0 0/1 0: Disable TOP00 pin output 1: Enable TOP00 pin output Settings of output level while operation of TOP00 pin is disabled 0: Low level 1: High level 0: Disable TOP01 pin output 1: Enable TOP01 pin output Specifies active level of TOP01 pin output 0: Active-high 1: Active-low * When TP0OL1 bit = 0 16-bit counter TOP01 pin output * When TP0OL1 bit = 1 16-bit counter TOP01 pin output
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Figure 6-18. Setting of Registers in External Trigger Pulse Output Mode (2/2)
(d) TMP0 I/O control register 2 (TP0IOC2)
TP0EES1 TP0EES0 TP0ETS1 TP0ETS0 TP0IOC2 0 0 0 0 0/1 0/1 0/1 0/1 Select valid edge of external trigger input Select valid edge of external event count input
(e) TMP0 counter read buffer register (TP0CNT) The value of the 16-bit counter can be read by reading the TP0CNT register. (f) TMP0 capture/compare registers 0 and 1 (TP0CCR0 and TP0CCR1) If D0 is set to the TP0CCR0 register and D1 to the TP0CCR1 register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) x Count clock cycle Active level width = D1 x Count clock cycle Remark TMP0 I/O control register 1 (TP0IOC1) and TMP0 option register 0 (TP0OPT0) are not used in the external trigger pulse output mode.
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(1) Operation flow in external trigger pulse output mode Figure 6-19. Software Processing Flow in External Trigger Pulse Output Mode (1/2)
FFFFH D01 16-bit counter 0000H TP0CE bit External trigger input (TIP00 pin input) TP0CCR0 register CCR0 buffer register INTTP0CC0 signal TOP00 pin output (software trigger) TP0CCR1 register CCR1 buffer register INTTP0CC1 signal TOP01 pin output D10 D10 D10 D10 D11 D11 D10 D10 D00 D00 D01 D01 D00 D00 D00 D10 D00 D10 D10 D11 D01 D11 D01 D00 D10
<1>
<2>
<3>
<4>
<5>
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Figure 6-19. Software Processing Flow in External Trigger Pulse Output Mode (2/2)
<1> Count operation start flow
<3> TP0CCR0, TP0CCR1 register setting change flow
Only writing of the TP0CCR1 register must be performed when the set duty factor is changed. When the counter is cleared after setting, the value of the TP0CCRa register is transferred to the CCRa buffer register.
START
Setting of TP0CCR1 register Register initial setting TP0CTL0 register (TP0CKS0 to TP0CKS2 bits) TP0CTL1 register, TP0IOC0 register, TP0IOC2 register, TP0CCR0 register, TP0CCR1 register Initial setting of these registers is performed before setting the TP0CE bit to 1.
<4> TP0CCR0, TP0CCR1 register setting change flow
The TP0CKS0 to TP0CKS2 bits can be set at the same time when counting is enabled (TP0CE bit = 1). Trigger wait status
TP0CE bit = 1
Setting of TP0CCR0 register
When the counter is cleared after setting, the value of the TP0CCRa register is transferred to the CCRa buffer register.
Setting of TP0CCR1 register
<2> TP0CCR0 and TP0CCR1 register setting change flow
<5> Count operation stop flow
Setting of TP0CCR0 register
TP0CCR1 register write processing is necessary only when the set cycle is changed. When the counter is cleared after setting, the value of the TP0CCRa register is transferred to the CCRa buffer register.
TP0CE bit = 0
Counting is stopped.
Setting of TP0CCR1 register
STOP
Remark
a = 0, 1
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(2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TP0CCR1 register last. Rewrite the TP0CCRa register after writing the TP0CCR1 register after the INTTP0CC0 signal is detected.
FFFFH D01 16-bit counter 0000H TP0CE bit External trigger input (TIP00 pin input) TP0CCR0 register CCR0 buffer register INTTP0CC0 signal TOP00 pin output (software trigger) TP0CCR1 register CCR1 buffer register INTTP0CC1 signal TOP01 pin output D10 D10 D11 D11 D00 D00 D01 D01 D00 D10 D00 D10 D00 D10 D11 D11 D01
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In order to transfer data from the TP0CCRa register to the CCRa buffer register, the TP0CCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TP0CCR0 register and then set the active level width to the TP0CCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TP0CCR0 register, and then write the same value to the TP0CCR1 register. To change only the active level width (duty factor) of the PWM waveform, only the TP0CCR1 register has to be set. After data is written to the TP0CCR1 register, the value written to the TP0CCRa register is transferred to the CCRa buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. To write the TP0CCR0 or TP0CCR1 register again after writing the TP0CCR1 register once, do so after the INTTP0CC0 signal is generated. Otherwise, the value of the CCRa buffer register may become undefined because the timing of transferring data from the TP0CCRa register to the CCRa buffer register conflicts with writing the TP0CCRa register. Remark a = 0, 1
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(b) 0%/100% output of PWM waveform To output a 0% waveform, clear the TP0CCR1 register to 0000H. If the set value of the TP0CCR0 register is FFFFH, the INTTP0CC1 signal is generated periodically.
Count clock 16-bit counter TP0CE bit TP0CCR0 register TP0CCR1 register INTTP0CC0 signal INTTP0CC1 signal TOP01 pin output D0 0000H D0 0000H D0 0000H FFFF 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000
To output a 100% waveform, set a value of (set value of TP0CCR0 register + 1) to the TP0CCR1 register. If the set value of the TP0CCR0 register is FFFFH, 100% output cannot be produced.
Count clock 16-bit counter TP0CE bit TP0CCR0 register TP0CCR1 register INTTP0CC0 signal INTTP0CC1 signal TOP01 pin output D0 D0 + 1 D0 D0 + 1 D0 D0 + 1 FFFF 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000
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(c) Conflict between trigger detection and match with TP0CCR1 register If the trigger is detected immediately after the INTTP0CC1 signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOP01 pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened.
16-bit counter External trigger input (TIP00 pin input) TP0CCR1 register INTTP0CC1 signal TOP01 pin output
FFFF
0000
D1 - 1
0000
D1
Shortened
If the trigger is detected immediately before the INTTP0CC1 signal is generated, the INTTP0CC1 signal is not generated, and the 16-bit counter is cleared to 0000H and continues counting. The output signal of the TOP01 pin remains active. Consequently, the active period of the PWM waveform is extended.
16-bit counter External trigger input (TIP00 pin input) TP0CCR1 register INTTP0CC1 signal TOP01 pin output
FFFF
0000
D1 - 2
0000
0001
D1 - 1
D1
D1
Extended
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(d) Conflict between trigger detection and match with TP0CCR0 register If the trigger is detected immediately after the INTTP0CC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOP01 pin is extended by time from generation of the INTTP0CC0 signal to trigger detection.
16-bit counter External trigger input (TIP00 pin input) TP0CCR0 register INTTP0CC0 signal TOP01 pin output
FFFF
0000
D0 - 1
D0
0000
0000
D0
Extended
If the trigger is detected immediately before the INTTP0CC0 signal is generated, the INTTP0CC0 signal is not generated. The 16-bit counter is cleared to 0000H, the TOP01 pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened.
16-bit counter External trigger input (TIP00 pin input) TP0CCR0 register INTTP0CC0 signal TOP01 pin output
FFFF
0000
D0 - 1
D0
0000
0001
D0
Shortened
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(e) Generation timing of compare match interrupt request signal (INTTP0CC1) The timing of generation of the INTTP0CC1 signal in the external trigger pulse output mode differs from the timing of other INTTP0CC1 signals; the INTTP0CC1 signal is generated when the count value of the 16-bit counter matches the value of the TP0CCR1 register.
Count clock 16-bit counter TP0CCR1 register TOP01 pin output INTTP0CC1 signal D1 - 1 D1 - 1 D1 D1 D1 + 1 D1 + 2
Usually, the INTTP0CC1 signal is generated in synchronization with the next count up, after the count value of the 16-bit counter matches the value of the TP0CCR1 register. In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the timing is changed to match the timing of changing the output signal of the TOP01 pin.
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6.5.4 One-shot pulse output mode (TP0MD2 to TP0MD0 bits = 011) In the one-shot pulse output mode, 16-bit timer/event counter P waits for a trigger when the TP0CTL0.TP0CE bit is set to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter P starts counting, and outputs a one-shot pulse from the TOP01 pin. Instead of the external trigger, a software trigger can also be generated to output the pulse. When the software trigger is used, the TOP00 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). Figure 6-20. Configuration in One-Shot Pulse Output Mode
TP0CCR1 register TIP00 pin Edge detector CCR1 buffer register Software trigger generation Match signal Clear Count clock selection Count start control Output S controller R (RS-FF) Transfer Output S controller R (RS-FF) TOP01 pin
INTTP0CC1 signal
16-bit counter Match signal
TOP00 pin
INTTP0CC0 signal
TP0CE bit
CCR0 buffer register Transfer TP0CCR0 register
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Figure 6-21. Basic Timing in One-Shot Pulse Output Mode
FFFFH D0 16-bit counter 0000H TP0CE bit External trigger input (TIP00 pin input) TP0CCR0 register INTTP0CC0 signal TOP00 pin output (software trigger) TP0CCR1 register INTTP0CC1 signal TOP01 pin output Delay (D1) Active level width (D0 - D1 + 1) Delay (D1) Delay Active level width (D1) (D0 - D1 + 1) Active level width (D0 - D1 + 1) D1 D0 D1 D1 D0 D1 D0
When the TP0CE bit is set to 1, 16-bit timer/event counter P waits for a trigger. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOP01 pin. After the one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a trigger is generated again while the one-shot pulse is being output, it is ignored. The output delay period and active level width of the one-shot pulse can be calculated as follows. Output delay period = (Set value of TP0CCR1 register) x Count clock cycle Active level width = (Set value of TP0CCR0 register - Set value of TP0CCR1 register + 1) x Count clock cycle The compare match interrupt request signal INTTP0CC0 is generated when the 16-bit counter counts after its count value matches the value of the CCR0 buffer register. The compare match interrupt request signal INTTP0CC1 is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. The valid edge of an external trigger input or setting the software trigger (TP0CTL1.TP0EST bit) to 1 is used as the trigger.
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Figure 6-22. Setting of Registers in One-Shot Pulse Output Mode (1/2)
(a) TMP0 control register 0 (TP0CTL0)
TP0CE TP0CTL0 0/1 0 0 0 0 TP0CKS2 TP0CKS1 TP0CKS0 0/1 0/1 0/1
Select count clockNote 0: Stop counting 1: Enable counting
Note The setting is invalid when the TP0CTL1.TP0EEE bit = 1. (b) TMP0 control register 1 (TP0CTL1)
TP0EST TP0EEE TP0CTL1 0 0/1 0/1 0 0 TP0MD2 TP0MD1 TP0MD0 0 1 1 0, 1, 1: One-shot pulse output mode 0: Operate on count clock selected by TP0CKS0 to TP0CKS2 bits 1: Count external event input signal Generate software trigger when 1 is written
(c) TMP0 I/O control register 0 (TP0IOC0)
TP0OL1 TP0IOC0 0 0 0 0 0/1 TP0OE1 TP0OL0 0/1 0/1 TP0OE0 0/1 0: Disable TOP00 pin output 1: Enable TOP00 pin output Setting of output level while operation of TOP00 pin is disabled 0: Low level 1: High level 0: Disable TOP01 pin output 1: Enable TOP01 pin output Specifies active level of TOP01 pin output 0: Active-high 1: Active-low
* When TP0OL1 bit = 0 16-bit counter TOP01 pin output
* When TP0OL1 bit = 1 16-bit counter TOP01 pin output
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Figure 6-22. Setting of Registers in One-Shot Pulse Output Mode (2/2)
(d) TMP0 I/O control register 2 (TP0IOC2)
TP0EES1 TP0EES0 TP0ETS1 TP0ETS0 TP0IOC2 0 0 0 0 0/1 0/1 0/1 0/1
Select valid edge of external trigger input Select valid edge of external event count input
(e) TMP0 counter read buffer register (TP0CNT) The value of the 16-bit counter can be read by reading the TP0CNT register. (f) TMP0 capture/compare registers 0 and 1 (TP0CCR0 and TP0CCR1) If D0 is set to the TP0CCR0 register and D1 to the TP0CCR1 register, the active level width and output delay period of the one-shot pulse are as follows. Active level width = (D1 - D0 + 1) x Count clock cycle Output delay period = D1 x Count clock cycle Remark TMP0 I/O control register 1 (TP0IOC1) and TMP0 option register 0 (TP0OPT0) are not used in the one-shot pulse output mode.
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(1) Operation flow in one-shot pulse output mode Figure 6-23. Software Processing Flow in One-Shot Pulse Output Mode
FFFFH D00 16-bit counter 0000H TP0CE bit External trigger input (TIP00 pin input) TP0CCR0 register INTTP0CC0 signal TP0CCR1 register INTTP0CC1 signal TOP01 pin output D10 D11 D00 D01 D01 D10 D11
<1>
<2>
<3>
<1> Count operation start flow
<2> TP0CCR0, TP0CCR1 register setting change flow
As rewriting the TP0CCRm register immediately forwards to the CCRm buffer register, rewriting immediately after the generation of the INTTP0CCR0 signal is recommended.
START Setting of TP0CCR0, TP0CCR1 registers Register initial setting TP0CTL0 register (TP0CKS0 to TP0CKS2 bits) TP0CTL1 register, TP0IOC0 register, TP0IOC2 register, TP0CCR0 register, TP0CCR1 register Initial setting of these registers is performed before setting the TP0CE bit to 1.
<3> Count operation stop flow
Count operation is stopped
TP0CE bit = 1
The TP0CKS0 to TP0CKS2 bits can be set at the same time when counting has been started (TP0CE bit = 1). Trigger wait status
TP0CE bit = 0
STOP
Remark
m = 0, 1
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(2) Operation timing in one-shot pulse output mode (a) Note on rewriting TP0CCRa register To change the set value of the TP0CCRa register to a smaller value, stop counting once, and then change the set value. If the value of the TP0CCRa register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
FFFFH D00 16-bit counter 0000H TP0CE bit External trigger input (TIP00 pin input) TP0CCR0 register INTTP0CC0 signal TOP00 pin output (software trigger) TP0CCR1 register INTTP0CC1 signal TOP01 pin output Delay (D10) Delay (D10) Active level width (D00 - D10 + 1) Delay (10000H + D11) Active level width (D01 - D11 + 1) D10 D11 D00 D01 D10 D10 D00 D10 D00 D01 D11
Active level width (D00 - D10 + 1)
When the TP0CCR0 register is rewritten from D00 to D01 and the TP0CCR1 register from D10 to D11 where D00 > D01 and D10 > D11, if the TP0CCR1 register is rewritten when the count value of the 16-bit counter is greater than D11 and less than D10 and if the TP0CCR0 register is rewritten when the count value is greater than D01 and less than D00, each set value is reflected as soon as the register has been rewritten and compared with the count value. The counter counts up to FFFFH and then counts up again from 0000H. When the count value matches D11, the counter generates the INTTP0CC1 signal and asserts the TOP01 pin. When the count value matches D01, the counter generates the INTTP0CC0 signal, deasserts the TOP01 pin, and stops counting. Therefore, the counter may output a pulse with a delay period or active period different from that of the one-shot pulse that is originally expected. Remark a = 0, 1
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(b) Generation timing of compare match interrupt request signal (INTTP0CC1) The generation timing of the INTTP0CC1 signal in the one-shot pulse output mode is different from other INTTP0CC1 signals; the INTTP0CC1 signal is generated when the count value of the 16-bit counter matches the value of the TP0CCR1 register.
Count clock 16-bit counter TP0CCR1 register TOP01 pin output INTTP0CC1 signal D1 - 2 D1 - 1 D1 D1 D1 + 1 D1 + 2
Usually, the INTTP0CC1 signal is generated when the 16-bit counter counts up next time after its count value matches the value of the TP0CCR1 register. In the one-shot pulse output mode, however, it is generated one clock earlier. This is because the timing is changed to match the change timing of the TOP01 pin.
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6.5.5 PWM output mode (TP0MD2 to TP0MD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOP01 pin when the TP0CTL0.TP0CE bit is set to 1. In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOP00 pin. Figure 6-24. Configuration in PWM Output Mode
TP0CCR1 register Transfer CCR1 buffer register Match signal Clear Count clock selection Count start control Output S controller R (RS-FF) TOP01 pin
INTTP0CC1 signal
16-bit counter Match signal
Output controller
TOP00 pin
INTTP0CC0 signal
TP0CE bit
CCR0 buffer register Transfer TP0CCR0 register
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Figure 6-25. Basic Timing in PWM Output Mode
FFFFH D01 16-bit counter 0000H TP0CE bit TP0CCR0 register CCR0 buffer register INTTP0CC0 signal TOP00 pin output TP0CCR1 register CCR1 buffer register INTTP0CC1 signal TOP01 pin output D10 D10 D11 D11 D00 D00 D01 D01 D00 D10 D00 D10 D00 D10 D11 D11 D01
Active period (D10)
Cycle (D00 + 1)
Inactive period (D00 - D10 + 1)
When the TP0CE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a PWM waveform from the TOP01 pin. The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TP0CCR1 register ) x Count clock cycle Cycle = (Set value of TP0CCR0 register + 1) x Count clock cycle Duty factor = (Set value of TP0CCR1 register)/(Set value of TP0CCR0 register + 1) The PWM waveform can be changed by rewriting the TP0CCRa register while the counter is operating. The newly written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal INTTP0CC0 is generated when the 16-bit counter counts next time after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal INTTP0CC1 is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. The value set to the TP0CCRa register is transferred to the CCRa buffer register when the count value of the 16-bit counter matches the value of the CCRa buffer register and the 16-bit counter is cleared to 0000H. Remark a = 0, 1
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Figure 6-26. Register Setting in PWM Output Mode (1/2)
(a) TMP0 control register 0 (TP0CTL0)
TP0CE TP0CTL0 0/1 0 0 0 0 TP0CKS2 TP0CKS1 TP0CKS0 0/1 0/1 0/1
Select count clockNote 0: Stop counting 1: Enable counting
Note The setting is invalid when the TP0CTL1.TP0EEE bit = 1. (b) TMP0 control register 1 (TP0CTL1)
TP0EST TP0EEE TP0CTL1 0 0 0/1 0 0 TP0MD2 TP0MD1 TP0MD0 1 0 0 1, 0, 0: PWM output mode 0: Operate on count clock selected by TP0CKS0 to TP0CKS2 bits 1: Count with external event count input signal
(c) TMP0 I/O control register 0 (TP0IOC0)
TP0OL1 TP0IOC0 0 0 0 0 0/1 TP0OE1 TP0OL0 0/1 0/1 TP0OE0 0/1 0: Disable TOP00 pin output 1: Enable TOP00 pin output Setting of output level while operation of TOP00 pin is disabled 0: Low level 1: High level 0: Disable TOP01 pin output 1: Enable TOP01 pin output Specifies active level of TOP01 pin output 0: Active-high 1: Active-low
* When TP0OL1 bit = 0 16-bit counter TOP01 pin output
* When TP0OL1 bit = 1 16-bit counter TOP01 pin output
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Figure 6-26. Register Setting in PWM Output Mode (2/2)
(d) TMP0 I/O control register 2 (TP0IOC2)
TP0EES1 TP0EES0 TP0ETS1 TP0ETS0 TP0IOC2 0 0 0 0 0/1 0/1 0 0
Select valid edge of external event count input.
(e) TMP0 counter read buffer register (TP0CNT) The value of the 16-bit counter can be read by reading the TP0CNT register. (f) TMP0 capture/compare registers 0 and 1 (TP0CCR0 and TP0CCR1) If D0 is set to the TP0CCR0 register and D1 to the TP0CCR1 register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) x Count clock cycle Active level width = D1 x Count clock cycle Remark TMP0 I/O control register 1 (TP0IOC1) and TMP0 option register 0 (TP0OPT0) are not used in the PWM output mode.
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(1) Operation flow in PWM output mode Figure 6-27. Software Processing Flow in PWM Output Mode (1/2)
FFFFH D01 16-bit counter D10 0000H TP0CE bit TP0CCR0 register CCR0 buffer register INTTP0CC0 signal TOP00 pin output TP0CCR1 register CCR1 buffer register INTTP0CC1 signal TOP01 pin output D10 D10 D10 D10 D11 D11 D10 D10 D00 D00 D01 D01 D00 D00 D00 D10 D00 D10 D11 D01 D11 D10 D01 D00
<1>
<2>
<3>
<4>
<5>
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Figure 6-27. Software Processing Flow in PWM Output Mode (2/2)
<1> Count operation start flow
<3> TP0CCR0, TP0CCR1 register setting change flow
Only writing of the TP0CCR1 register must be performed when the set duty factor is changed. When the counter is cleared after setting, the value of compare register a is transferred to the CCRa buffer register.
START
Setting of TP0CCR1 register Register initial setting TP0CTL0 register (TP0CKS0 to TP0CKS2 bits) TP0CTL1 register, TP0IOC0 register, TP0IOC2 register, TP0CCR0 register, TP0CCR1 register Initial setting of these registers is performed before setting the TP0CE bit to 1.
<4> TP0CCR0, TP0CCR1 register setting change flow
The TP0CKS0 to TP0CKS2 bits can be set at the same time when counting is enabled (TP0CE bit = 1).
TP0CE bit = 1
Setting of TP0CCR0 register
When the counter is cleared after setting, the value of compare register a is transferred to the CCRa buffer register.
Setting of TP0CCR1 register
<2> TP0CCR0, TP0CCR1 register setting change flow
<5> Count operation stop flow
Setting of TP0CCR0 register
TP0CCR1 write processing is necessary only when the set cycle is changed. When the counter is cleared after setting, the value of the TP0CCRa register is transferred to the CCRa buffer register.
TP0CE bit = 0
Counting is stopped.
Setting of TP0CCR1 register
STOP
Remark
a = 0, 1
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(2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TP0CCR1 register last. Rewrite the TP0CCRa register after writing the TP0CCR1 register after the INTTP0CC1 signal is detected.
FFFFH D01 16-bit counter 0000H TP0CE bit TP0CCR0 register CCR0 buffer register TP0CCR1 register CCR1 buffer register TOP01 pin output INTTP0CC0 signal D00 D00 D10 D10 D11 D11 D01 D01 D00 D10 D00 D10 D00 D10 D11 D11 D01
To transfer data from the TP0CCRa register to the CCRa buffer register, the TP0CCR1 register must be written. To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the TP0CCR0 register and then set the active level to the TP0CCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TP0CCR0 register, and then write the same value to the TP0CCR1 register. To change only the active level width (duty factor) of the PWM waveform, only the TP0CCR1 register has to be set. After data is written to the TP0CCR1 register, the value written to the TP0CCRa register is transferred to the CCRa buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. To write the TP0CCR0 or TP0CCR1 register again after writing the TP0CCR1 register once, do so after the INTTP0CC0 signal is generated. Otherwise, the value of the CCRa buffer register may become undefined because the timing of transferring data from the TP0CCRa register to the CCRa buffer register conflicts with writing the TP0CCRa register. Remark a = 0, 1
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(b) 0%/100% output of PWM waveform To output a 0% waveform, set the TP0CCR1 register to 0000H. If the set value of the TP0CCR0 register is FFFFH, the INTTP0CC1 signal is generated periodically.
Count clock 16-bit counter TP0CE bit TP0CCR0 register TP0CCR1 register INTTP0CC0 signal INTTP0CC1 signal TOP01 pin output D00 0000H D00 0000H D00 0000H FFFF 0000 D00 - 1 D00 0000 0001 D00 - 1 D00 0000
To output a 100% waveform, set a value of (set value of TP0CCR0 register + 1) to the TP0CCR1 register. If the set value of the TP0CCR0 register is FFFFH, 100% output cannot be produced.
Count clock 16-bit counter TP0CE bit TP0CCR0 register TP0CCR1 register INTTP0CC0 signal INTTP0CC1 signal TOP01 pin output D00 D00 + 1 D00 D00 + 1 D00 D00 + 1 FFFF 0000 D00 - 1 D00 0000 0001 D00 - 1 D00 0000
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(c) Generation timing of compare match interrupt request signal (INTTP0CC1) The timing of generation of the INTTP0CC1 signal in the PWM output mode differs from the timing of other INTTP0CC1 signals; the INTTP0CC1 signal is generated when the count value of the 16-bit counter matches the value of the TP0CCR1 register.
Count clock 16-bit counter TP0CCR1 register TOP01 pin output INTTP0CC1 signal D1 - 2 D1 - 1 D1 D1 D1 + 1 D1 + 2
Usually, the INTTP0CC1 signal is generated in synchronization with the next counting up after the count value of the 16-bit counter matches the value of the TP0CCR1 register. In the PWM output mode, however, it is generated one clock earlier. This is because the timing is changed to match the change timing of the output signal of the TOP01 pin.
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6.5.6 Free-running timer mode (TP0MD2 to TP0MD0 bits = 101) In the free-running timer mode, 16-bit timer/event counter P starts counting when the TP0CTL0.TP0CE bit is set to 1. At this time, the TP0CCRa register can be used as a compare register or a capture register, depending on the setting of the TP0OPT0.TP0CCS0 and TP0OPT0.TP0CCS1 bits. Figure 6-28. Configuration in Free-Running Timer Mode
TP0CCR1 register (compare)
Output controller
TOP01 pin output
TP0CCR0 register (compare)
Output controller
TOP00 pin output
TP0CCS0, TP0CCS1 bits (capture/compare selection) Internal count clock TIP00 pin (external event count input/ capture trigger input) Edge detector Count clock selection TP0CE bit Digital noise eliminator Digital noise eliminator Edge detector TP0CCR0 register (capture) Edge detector TP0CCR1 register (capture)
16-bit counter
INTTP0OV signal
0 1 0
INTTP0CC1 signal
INTTP0CC0 signal 1
TIP01 pin (capture trigger input)
Remark
a = 0, 1
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When the TP0CE bit is set to 1, 16-bit timer/event counter P starts counting, and the output signals of the TOP00 and TOP01 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TP0CCRa register, a compare match interrupt request signal (INTTP0CCa) is generated, and the output signal of the TOP0a pin is inverted. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTP0OV) at the next clock, is cleared to 0000H, and continues counting. At this time, the overflow flag (TP0OPT0.TP0OVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction by software. The TP0CCRa register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected at that time, and compared with the count value. Figure 6-29. Basic Timing in Free-Running Timer Mode (Compare Function)
FFFFH D00 16-bit counter D10 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal TOP00 pin output TP0CCR1 register INTTP0CC1 signal TOP01 pin output INTTP0OV signal TP0OVF bit Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction D10 D11 D00 D01 D10 D11 D00 D01 D11 D01 D11
Remark
a = 0, 1
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When the TP0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIP0a pin is detected, the count value of the 16-bit counter is stored in the TP0CCRa register, and a capture interrupt request signal (INTTP0CCa) is generated. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTP0OV) at the next clock, is cleared to 0000H, and continues counting. At this time, the overflow flag (TP0OPT0.TP0OVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction by software. Figure 6-30. Basic Timing in Free-Running Timer Mode (Capture Function)
FFFFH D10 D00 16-bit counter 0000H TP0CE bit TIP00 pin input TP0CCR0 register INTTP0CC0 signal TIP01 pin input TP0CCR1 register INTTP0CC1 signal INTTP0OV signal TP0OVF bit Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction D10 D11 D12 D13 D00 D01 D02 D03 D01 D02 D03 D11 D12 D13
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Figure 6-31. Register Setting in Free-Running Timer Mode (1/2)
(a) TMP0 control register 0 (TP0CTL0)
TP0CE TP0CTL0 0/1 0 0 0 0 TP0CKS2 TP0CKS1 TP0CKS0 0/1 0/1 0/1
Select count clockNote 0: Stop counting 1: Enable counting
Note The setting is invalid when the TP0CTL1.TP0EEE bit = 1 (b) TMP0 control register 1 (TP0CTL1)
TP0EST TP0EEE TP0CTL1 0 0 0/1 0 0 TP0MD2 TP0MD1 TP0MD0 1 0 1 1, 0, 1: Free-running mode 0: Operate with count clock selected by TP0CKS0 to TP0CKS2 bits 1: Count on external event count input signal
(c) TMP0 I/O control register 0 (TP0IOC0)
TP0OL1 TP0IOC0 0 0 0 0 0/1 TP0OE1 TP0OL0 0/1 0/1 TP0OE0 0/1 0: Disable TOP00 pin output 1: Enable TOP00 pin output Setting of output level with operation of TOP00 pin disabled 0: Low level 1: High level 0: Disable TOP01 pin output 1: Enable TOP01 pin output Setting of output level with operation of TOP01 pin disabled 0: Low level 1: High level
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Figure 6-31. Register Setting in Free-Running Timer Mode (2/2)
(d) TMP0 I/O control register 1 (TP0IOC1)
TP0IS3 TP0IOC1 0 0 0 0 0/1 TP0IS2 0/1 TP0IS1 0/1 TP0IS0 0/1
Select valid edge of TIP00 pin input Select valid edge of TIP01 pin input
(e) TMP0 I/O control register 2 (TP0IOC2)
TP0EES1 TP0EES0 TP0ETS1 TP0ETS0 TP0IOC2 0 0 0 0 0/1 0/1 0 0
Select valid edge of external event count input
(f) TMP0 option register 0 (TP0OPT0)
TP0CCS1 TP0CCS0 TP0OPT0 0 0 0/1 0/1 0 0 0 TP0OVF 0/1 Overflow flag Specifies if TP0CCR0 register functions as capture or compare register Specifies if TP0CCR1 register functions as capture or compare register
(g) TMP0 counter read buffer register (TP0CNT) The value of the 16-bit counter can be read by reading the TP0CNT register. (h) TMP0 capture/compare registers 0 and 1 (TP0CCR0 and TP0CCR1) These registers function as capture registers or compare registers depending on the setting of the TP0OPT0.TP0CCSa bit. When the registers function as capture registers, they store the count value of the 16-bit counter when the valid edge input to the TIP0a pin is detected. When the registers function as compare registers and when Da is set to the TP0CCRa register, the INTTP0CCa signal is generated when the counter reaches (Da + 1), and the output signal of the TOP0a pin is inverted. Remark a = 0, 1
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(1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 6-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2)
FFFFH D00 16-bit counter D10 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal TOP00 pin output TP0CCR1 register INTTP0CC1 signal TOP01 pin output INTTP0OV signal TP0OVF bit <1> Cleared to 0 by CLR instruction <2> Cleared to 0 by CLR instruction <2> Cleared to 0 by CLR instruction <2> <3> D10 D11 D00 D01 D10 D11 D00 D01 D11 D01 D11
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Figure 6-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2)
<1> Count operation start flow
START
Register initial setting TP0CTL0 register (TP0CKS0 to TP0CKS2 bits) TP0CTL1 register, TP0IOC0 register, TP0IOC2 register, TP0OPT0 register, TP0CCR0 register, TP0CCR1 register
Initial setting of these registers is performed before setting the TP0CE bit to 1.
TP0CE bit = 1
The TP0CKS0 to TP0CKS2 bits can be set at the same time when counting has been started (TP0CE bit = 1).
<2> Overflow flag clear flow
Read TP0OPT0 register (check overflow flag).
TP0OVF bit = 1
NO
YES Execute instruction to clear TP0OVF bit (CLR TP0OVF).
<3> Count operation stop flow
Counter is initialized and counting is stopped by clearing TP0CE bit to 0.
TP0CE bit = 0
STOP
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(b) When using capture/compare register as capture register Figure 6-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2)
FFFFH D10 D00 16-bit counter 0000H TP0CE bit TIP00 pin input TP0CCR0 register INTTP0CC0 signal TIP01 pin input TP0CCR1 register INTTP0CC1 signal INTTP0OV signal TP0OVF bit Cleared to 0 by CLR instruction <2> Cleared to 0 by CLR instruction <2> 0000 D10 D11 D12 0000 0000 D00 D01 D02 D03 0000 D01 D02 D03 D11 D12
<1>
<3>
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Figure 6-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2)
<1> Count operation start flow
START
Register initial setting TP0CTL0 register (TP0CKS0 to TP0CKS2 bits) TP0CTL1 register, TP0IOC1 register, TP0OPT0 register
Initial setting of these registers is performed before setting the TP0CE bit to 1.
TP0CE bit = 1
The TP0CKS0 to TP0CKS2 bits can be set at the same time when counting has been started (TP0CE bit = 1).
<2> Overflow flag clear flow
Read TP0OPT0 register (check overflow flag).
TP0OVF bit = 1
NO
YES Execute instruction to clear TP0OVF bit (CLR TP0OVF).
<3> Count operation stop flow
Counter is initialized and counting is stopped by clearing TP0CE bit to 0.
TP0CE bit = 0
STOP
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(2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter P is used as an interval timer with the TP0CCRa register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTP0CCa signal has been detected.
FFFFH D10 D00 16-bit counter D01 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal TOP00 pin output D00 D01 D11
D02 D03 D12 D13 D04
D02
D03
D04
D05
Interval period Interval period Interval period Interval period Interval period (D00 + 1) (10000H + (D02 - D01) (10000H + (10000H + D01 - D00) D03 - D02) D04 - D03)
TP0CCR1 register INTTP0CC1 signal TOP01 pin output
D10
D11
D12
D13
D14
Interval period Interval period Interval period Interval period (D10 + 1) (10000H + (10000H + (10000H + D11 - D10) D12 - D11) D13 - D12)
When performing an interval operation in the free-running timer mode, two intervals can be set with one channel. To perform the interval operation, the value of the corresponding TP0CCRa register must be re-set in the interrupt servicing that is executed when the INTTP0CCa signal is detected. The set value for re-setting the TP0CCRa register can be calculated by the following expression, where "Da" is the interval period. Compare register default value: Da - 1 Value set to compare register second and subsequent time: Previous set value + Da (If the calculation result is greater than FFFFH, subtract 10000H from the result and set this value to the register.) Remark a = 0, 1
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(b) Pulse width measurement with capture register When pulse width measurement is performed with the TP0CCRa register used as a capture register, software processing is necessary for reading the capture register each time the INTTP0CCa signal has been detected and for calculating an interval.
FFFFH D10 D00 16-bit counter D01 0000H TP0CE bit TIP00 pin input TP0CCR0 register INTTP0CC0 signal 0000H D00 D11
D02 D03 D12 D13 D04
D01
D02
D03
D04
Pulse interval Pulse interval Pulse interval Pulse interval Pulse interval (D00) (10000H + (D02 - D01) (10000H + (10000H + D01 - D00) D03 - D02) D04 - D03)
TIP01 pin input TP0CCR1 register INTTP0CC1 signal
Pulse interval Pulse interval Pulse interval Pulse interval (D10) (10000H + (10000H + (10000H + D11 - D10) D12 - D11) D13 - D12)
0000H
D10
D11
D12
D13
INTTP0OV signal TP0OVF bit
Cleared to 0 by CLR instruction
Cleared to 0 by CLR instruction
Cleared to 0 by CLR instruction
When executing pulse width measurement in the free-running timer mode, two pulse widths can be measured with one channel. To measure a pulse width, the pulse width can be calculated by reading the value of the TP0CCRa register in synchronization with the INTTP0CCa signal, and calculating the difference between the read value and the previously read value. Remark a = 0, 1
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(c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below.
Example of incorrect processing when two capture registers are used
FFFFH D11 16-bit counter D00 0000H TP0CE bit TIP00 pin input TP0CCR0 register TIP01 pin input TP0CCR1 register INTTP0OV signal TP0OVF bit D10 D11 D00 D01 D10 D01
<1>
<2>
<3>
<4>
The following problem may occur when two pulse widths are measured in the free-running timer mode. <1> Read the TP0CCR0 register (setting of the default value of the TIP00 pin input). <2> Read the TP0CCR1 register (setting of the default value of the TIP01 pin input). <3> Read the TP0CCR0 register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <4> Read the TP0CCR1 register. Read the overflow flag. Because the flag is cleared in <3>, 0 is read. Because the overflow flag is 0, the pulse width can be calculated by (D11 - D10) (incorrect).
When two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. Use software when using two capture registers. An example of how to use software is shown below.
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(1/2) Example when two capture registers are used (using overflow interrupt)
FFFFH D11 16-bit counter D00 0000H TP0CE bit INTTP0OV signal TP0OVF bit TP0OVF0 flagNote TIP00 pin input TP0CCR0 register TP0OVF1 flagNote TIP01 pin input TP0CCR1 register D10 D11 D00 D01 D10 D01
<1>
<2>
<3>
<4>
<5> <6>
Note The TP0OVF0 and TP0OVF1 flags are set on the internal RAM by software. <1> Read the TP0CCR0 register (setting of the default value of the TIP00 pin input). <2> Read the TP0CCR1 register (setting of the default value of the TIP01 pin input). <3> An overflow occurs. Set the TP0OVF0 and TP0OVF1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> Read the TP0CCR0 register. Read the TP0OVF0 flag. If the TP0OVF0 flag is 1, clear it to 0. Because the TP0OVF0 flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <5> Read the TP0CCR1 register. Read the TP0OVF1 flag. If the TP0OVF1 flag is 1, clear it to 0 (the TP0OVF0 flag is cleared in <4>, and the TP0OVF1 flag remains 1). Because the TP0OVF1 flag is 1, the pulse width can be calculated by (10000H + D11 - D10) (correct). <6> Same as <3>
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(2/2) Example when two capture registers are used (without using overflow interrupt)
FFFFH D11 16-bit counter D00 0000H TP0CE bit INTTP0OV signal TP0OVF bit TP0OVF0 flagNote TIP00 pin input TP0CCR0 register TP0OVF1 flagNote TIP01 pin input TP0CCR1 register D10 D11 D00 D01 D10 D01
<1>
<2>
<3>
<4>
<5> <6>
Note The TP0OVF0 and TP0OVF1 flags are set on the internal RAM by software. <1> Read the TP0CCR0 register (setting of the default value of the TIP00 pin input). <2> Read the TP0CCR1 register (setting of the default value of the TIP01 pin input). <3> An overflow occurs. Nothing is done by software. <4> Read the TP0CCR0 register. Read the overflow flag. If the overflow flag is 1, set only the TP0OVF1 flag to 1, and clear the overflow flag to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <5> Read the TP0CCR1 register. Read the overflow flag. Because the overflow flag is cleared in <4>, 0 is read. Read the TP0OVF1 flag. If the TP0OVF1 flag is 1, clear it to 0. Because the TP0OVF1 flag is 1, the pulse width can be calculated by (10000H + D11 - D10) (correct). <6> Same as <3>
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(d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below.
Example of incorrect processing when capture trigger interval is long
FFFFH 16-bit counter Da1 0000H TP0CE bit TIP0a pin input TP0CCRa register INTTP0OV signal TP0OVF bit 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> Da0 Da1 Da0
The following problem may occur when long pulse width is measured in the free-running timer mode. <1> Read the TP0CCRa register (setting of the default value of the TIP0a pin input). <2> An overflow occurs. Nothing is done by software. <3> An overflow occurs a second time. Nothing is done by software. <4> Read the TP0CCRa register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + Da1 - Da0) (incorrect). Actually, the pulse width must be (20000H + Da1 - Da0) because an overflow occurs twice.
If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may not be obtained. If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. An example of how to use software is shown next.
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Example when capture trigger interval is long
FFFFH 16-bit counter Da1 0000H TP0CE bit TIP0a pin input TP0CCRa register INTTP0OV signal TP0OVF bit Overflow counterNote 0H 1H 2H 0H Da0 Da1 Da0
1 cycle of 16-bit counter Pulse width <1> <2> <3> <4>
Note The overflow counter is set arbitrarily by software on the internal RAM. <1> Read the TP0CCRa register (setting of the default value of the TIP0a pin input). <2> An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <3> An overflow occurs a second time. Increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> Read the TP0CCRa register. Read the overflow counter. When the overflow counter is "N", the pulse width can be calculated by (N x 10000H + Da1 - Da0). In this example, the pulse width is (20000H + Da1 - Da0) because an overflow occurs twice. Clear the overflow counter (0H).
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(e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TP0OVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TP0OPT0 register. To accurately detect an overflow, read the TP0OVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
(i) Operation to write 0 (without conflict with setting)
(iii) Operation to clear to 0 (without conflict with setting)
Overflow set signal 0 write signal Overflow flag (TP0OVF bit)
L
Overflow set signal 0 write signal Register access signal Overflow flag (TP0OVF bit)
L
Read
Write
(ii) Operation to write 0 (conflict with setting)
(iv) Operation to clear to 0 (conflict with setting)
Overflow set signal 0 write signal Overflow flag (TP0OVF bit)
Overflow set signal 0 write signal Register access signal Overflow flag (TP0OVF bit) H
Read
Write
To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is cleared to 0 with the CLR instruction, the overflow flag remains set even after execution of the clear instruction.
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6.5.7 Pulse width measurement mode (TP0MD2 to TP0MD0 bits = 110) In the pulse width measurement mode, 16-bit timer/event counter P starts counting when the TP0CTL0.TP0CE bit is set to 1. Each time the valid edge input to the TIP0a pin has been detected, the count value of the 16-bit counter is stored in the TP0CCRa register, and the 16-bit counter is cleared to 0000H. The interval of the valid edge can be measured by reading the TP0CCRa register after a capture interrupt request signal (INTTP0CCa) occurs. Select either the TIP00 or TIP01 pin as the capture trigger input pin. Specify "No edge detected" by using the TP0IOC1 register for the unused pins. When an external clock is used as the count clock, measure the pulse width of the TIP01 pin because the external clock is fixed to the TIP00 pin. At this time, clear the TP0IOC1.TP0IS1 and TP0IOC1.TP0IS0 bits to 00 (capture trigger input (TIP00 pin): No edge detected). Figure 6-34. Configuration in Pulse Width Measurement Mode
Clear Internal count clock TIP00 pin (external event count input/capture trigger input) Edge detector Count clock selection
16-bit counter
INTTP0OV signal INTTP0CC0 signal
TP0CE bit Digital noise eliminator Digital noise eliminator Edge detector TP0CCR0 register (capture) Edge detector TP0CCR1 register (capture) INTTP0CC1 signal
TIP01 pin (capture trigger input)
Remark
a = 0, 1
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Figure 6-35. Basic Timing in Pulse Width Measurement Mode
FFFFH 16-bit counter 0000H TP0CE bit TIP0a pin input TP0CCRa register INTTP0CCa signal INTTP0OV signal TP0OVF bit Cleared to 0 by CLR instruction 0000H D0 D1 D2 D3
Remark
a = 0, 1
When the TP0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIP0a pin is later detected, the count value of the 16-bit counter is stored in the TP0CCRa register, the 16-bit counter is cleared to 0000H, and a capture interrupt request signal (INTTP0CCa) is generated. The pulse width is calculated as follows. Pulse width = Captured value x Count clock cycle If the valid edge is not input to the TIP0a pin even when the 16-bit counter counted up to FFFFH, an overflow interrupt request signal (INTTP0OV) is generated at the next count clock, and the counter is cleared to 0000H and continues counting. At this time, the overflow flag (TP0OPT0.TP0OVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction via software. If the overflow flag is set to 1, the pulse width can be calculated as follows. Pulse width = (10000H x TP0OVF bit set (1) count + Captured value) x Count clock cycle Remark a = 0, 1
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Figure 6-36. Register Setting in Pulse Width Measurement Mode (1/2)
(a) TMP0 control register 0 (TP0CTL0)
TP0CE TP0CTL0 0/1 0 0 0 0 TP0CKS2 TP0CKS1 TP0CKS0 0/1 0/1 0/1
Select count clockNote 0: Stop counting 1: Enable counting
Note Setting is invalid when the TP0EEE bit = 1. (b) TMP0 control register 1 (TP0CTL1)
TP0EST TP0EEE TP0CTL1 0 0 0/1 0 0 TP0MD2 TP0MD1 TP0MD0 1 1 0 1, 1, 0: Pulse width measurement mode 0: Operate with count clock selected by TP0CKS0 to TP0CKS2 bits 1: Count external event count input signal
(c) TMP0 I/O control register 1 (TP0IOC1)
TP0IS3 TP0IOC1 0 0 0 0 0/1 TP0IS2 0/1 TP0IS1 0/1 TP0IS0 0/1
Select valid edge of TIP00 pin input Select valid edge of TIP01 pin input
(d) TMP0 I/O control register 2 (TP0IOC2)
TP0EES1 TP0EES0 TP0ETS1 TP0ETS0 TP0IOC2 0 0 0 0 0/1 0/1 0 0
Select valid edge of external event count input
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Figure 6-36. Register Setting in Pulse Width Measurement Mode (2/2)
(e) TMP0 option register 0 (TP0OPT0)
TP0CCS1 TP0CCS0 TP0OPT0 0 0 0 0 0 0 0 TP0OVF 0/1
Overflow flag
(f) TMP0 counter read buffer register (TP0CNT) The value of the 16-bit counter can be read by reading the TP0CNT register. (g) TMP0 capture/compare registers 0 and 1 (TP0CCR0 and TP0CCR1) These registers store the count value of the 16-bit counter when the valid edge input to the TIP0a pin is detected. Remarks 1. TMP0 I/O control register 0 (TP0IOC0) is not used in the pulse width measurement mode. 2. a = 0, 1
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(1) Operation flow in pulse width measurement mode Figure 6-37. Software Processing Flow in Pulse Width Measurement Mode
FFFFH 16-bit counter 0000H TP0CE bit TIP00 pin input TP0CCR0 register INTTP0CC0 signal <1> <2> 0000H D0 D1 D2 0000H
<1> Count operation start flow
START
Register initial setting TP0CTL0 register (TP0CKS0 to TP0CKS2 bits), TP0CTL1 register, TP0IOC1 register, TP0IOC2 register, TP0OPT0 register
Initial setting of these registers is performed before setting the TP0CE bit to 1.
Set TP0CTL0 register (TP0CE bit = 1)
The TP0CKS0 to TP0CKS2 bits can be set at the same time when counting has been started (TP0CE bit = 1).
<2> Count operation stop flow
The counter is initialized and counting is stopped by clearing the TP0CE bit to 0.
TP0CE bit = 0
STOP
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(2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TP0OVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TP0OPT0 register. To accurately detect an overflow, read the TP0OVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
(i) Operation to write 0 (without conflict with setting)
(iii) Operation to clear to 0 (without conflict with setting)
Overflow set signal 0 write signal Overflow flag (TP0OVF bit)
L
Overflow set signal 0 write signal Register access signal Overflow flag (TP0OVF bit)
L
Read
Write
(ii) Operation to write 0 (conflict with setting)
(iv) Operation to clear to 0 (conflict with setting)
Overflow set signal 0 write signal Overflow flag (TP0OVF bit)
Overflow set signal 0 write signal Register access signal Overflow flag (TP0OVF bit) H
Read
Write
To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is cleared to 0 with the CLR instruction, the overflow flag remains set even after execution of the clear instruction.
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6.5.8 Timer output operations The following table shows the operations and output levels of the TOP00 and TOP01 pins. Table 6-4. Timer Output Control in Each Mode
Operation Mode Interval timer mode External event count mode External trigger pulse output mode One-shot pulse output mode PWM output mode Free-running timer mode Pulse width measurement mode TOP01 Pin Square wave output Square wave output External trigger pulse output One-shot pulse output PWM output Square wave output (only when compare function is used) - - Square wave output TOP00 Pin
Table 6-5. Truth Table of TOP00 and TOP01 Pins Under Control of Timer Output Control Bits
TP0IOC0.TP0OLa Bit 0 TP0IOC0.TP0OEa Bit 0 1 TP0CTL0.TP0CE Bit x 0 1 x 0 1 Level of TOP0a Pin Low-level output Low-level output Low level immediately before counting, high level after counting is started 1 0 1 High-level output High-level output High level immediately before counting, low level after counting is started
Remark
a = 0, 1
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6.6 Eliminating Noise on Capture Trigger Input Pin (TIP0a)
The TIP0a pin has a digital noise eliminator. However, this circuit is valid only when the pin is used as a capture trigger input pin; it is invalid when the pin is used as an external event count input pin or external trigger input pin. Digital noise can be eliminated by specifying the alternate function of the TIP0a pin using the PMC3, PFC3, and PFCE3 registers. The number of times of sampling can be selected from three or two by using the PaNFC.PaNFSTS bit. The sampling clock can be selected from fXX, fXX/2, fXX/4, fXX/16, fXX/32, or fXX/64, by using the PaNFC.PaNFC2 to PaNFC.PaNFC0 bits. (1) TIP0a noise elimination control register (PaNFC) This register is used to select the sampling clock and the number of times of sampling for eliminating digital noise. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.
After reset: 00H
R/W
Address: P0NFC FFFFFB00H, P1NFC FFFFFB04H
PaNFC (a = 0, 1)
0
PaNFSTS
0
0
0
PaNFC2 PaNFC1 PaNFC0
PaNFSTS 0 1
Setting of number of times of sampling for eliminating digital noise Number of times of sampling = 3 Number of times of sampling = 2
PaNFC2 PaNFC1 PaNFC0 0 0 0 0 1 1 0 0 1 1 0 0 Other than above 0 1 0 1 0 1 fXX fXX/2 fXX/4 fXX/16 fXX/32 fXX/64
Sampling clock selection
Setting prohibited
Cautions 1. Enable starting the 16-bit counter of TMP0 (TP0CTL.TP0CE bit = 1) after the lapse of the sampling clock period x number of times of sampling. 2. Be sure to clear bits 7, 5 to 3 to "0".
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<1> Select the number of times of sampling and the sampling clock by using the PaNFC register. <2> Select the alternate function (of the TIP0a pin) by using the PMC3, PFC3, and PFCE3 registers. <3> Set the operating mode of TMP0 (such as the capture mode or the valid edge of the capture trigger). <4> Enable the TMP0 count operation. The digital noise elimination width (tWTIPa) is as follows, where T is the sampling clock period and M is the number of times of sampling. * tWTIPa < (M - 1)T: * (M - 1)T tWTIPa < MT: * tWTIPa MT: Accurately eliminated as noise Eliminated as noise or detected as valid edge Accurately detected as valid edge
Therefore, a pulse width of MT or longer must be input so that the valid edge of the capture trigger input can be accurately detected.
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6.7 Cautions
(1) Capture operation When the capture operation is used and fXX/8, fXX/16, fXX/32, fXX/64, fXX/128, or the external event counter (TP0CLT1.TP0EEE bit = 1) is selected as the count clock, FFFFH, not 0000H, may be captured in the TP0CCRn register if the capture trigger is input immediately after the TP0CE bit is set to 1.
(a) Free-running timer mode
FFFFH
16-bit counter
0000H
Count clock
Sampling clock (fXX)
TP0CCR0 register
0000H
FFFFH
0001H
TP0CE bit
TIP00 pin input Capture trigger input Capture trigger input
(b) Pulse width measurement mode
FFFFH
16-bit counter
0000H
Count clock
Sampling clock (fXX)
TP0CCR0 register
0000H
FFFFH
0002H
TP0CE bit
TIP00 pin input Capture trigger input Capture trigger input
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In the V850ES/KE2, one channel of 16-bit timer/event counter 0 is provided.
7.1 Functions
16-bit timer/event counter 01 has the following functions. (1) Interval timer 16-bit timer/event counter 01 generates an interrupt request at the preset time interval. (2) Square-wave output 16-bit timer/event counter 01 can output a square wave with any selected frequency. (3) External event counter 16-bit timer/event counter 01 can measure the number of pulses of an externally input signal. (4) One-shot pulse output 16-bit timer/event counter 01 can output a one-shot pulse whose output pulse width can be set freely. (5) PPG output 16-bit timer/event counter 01 can output a rectangular wave whose frequency and output pulse width can be set freely. (6) Pulse width measurement 16-bit timer/event counter 01 can measure the pulse width of an externally input signal.
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7.2 Configuration
16-bit timer/event counter 01 includes the following hardware. Table 7-1. Configuration of 16-Bit Timer/Event Counter 01
Item Time/counter Register Timer input Timer output Control registers
Note
Configuration 16-bit timer counter 01 (TM01) 16-bit timer capture/compare registers: 16-bit x 2 (CR010, CR011) 2 (TI010, TI011 pins) 1 (TO01 pin), output controller 16-bit timer mode control register 01 (TMC01) Capture/compare control register 01 (CRC01) 16-bit timer output control register 01 (TOC01) Prescaler mode register 01 (PRM01) Selector operation control register 1 (SELCNT1)
Note To use the TI010, TI011, and TO01 pin functions, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. The block diagram is shown below. Figure 7-1. Block Diagram of 16-Bit Timer/Event Counter 01
Internal bus
Capture/compare control CRC012CRC011 CRC010 register 01 (CRC01)
Selector
INTTM010
Noise eliminator
Selector
Tl011
16-bit timer capture/compare register 010 (CR010) Match
Count clock
Selector
16-bit timer counter 01 (TM01) Match
Clear
Output controller
TO01
fXX/4
Noise eliminator
3
Noise eliminator
Tl010
16-bit timer capture/compare register 011 (CR011)
Selector
INTTM011
ISEL11 PRM011 PRM010
Selector operation control register 1 (SELCNT1) Prescaler mode register 01 (PRM01)
TMC013 TMC012 TMC011 OVF01
OSPT01 OSPE01 TOC014 LVS01 LVR01 TOC011 TOE01 Timer output control register 01 (TOC01)
16-bit timer mode control register 01 (TMC01) Internal bus
Remark
fXX: Main clock frequency
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(1) 16-bit timer counter 01 (TM01) The TM01 register is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock.
After reset: 0000H
15 14
R 13 12
Address: FFFFF610H 11 10 9 8 7 6 5 4 3 2
1 0
TM01
The count value of the TM01 register can be read by reading the TM01 register when the values of the TMC01.TMC013 and TMC01.TMC012 bits are other than 00. The value of the TM01 register is 0000H if it is read when the TMC013 and TMC012 bits are 00. The count value is reset to 0000H in the following cases. * At reset signal generation * If the TMC013 and TMC012 bits are cleared to 00 * If the valid edge of the TI010 pin is input in the mode in which the clear & start occurs when inputting the valid edge to the TI010 pin * If the TM01 register and the CR010 register match in the mode in which the clear & start occurs when the TM01 register and the CR010 register match * The TOC01.OSPT01 bit is set to 1 in one-shot pulse output mode or the valid edge is input to the TI010 pin (2) 16-bit timer capture/compare register 010 (CR010), 16-bit timer capture/compare register 011 (CR011) The CR010 and CR011 registers are 16-bit registers that are used with a capture function or comparison function selected by using the CRC01 register. Change of the value of the CR010 register while the timer is operating (TMC01.TMC013 and TMC01.TMC012 bits = other than 00) is prohibited. The value of the CR011 register can be changed during operation if the value has been set in a specific way. For details, see 7.5.1 Rewriting CR010 register during TM01 operation. These registers can be read or written in 16-bit units. Reset sets these registers to 0000H. (a) 16-bit timer capture/compare register 010 (CR010)
After reset: 0000H
15 14
R/W 13 12
Address: FFFFF612H 11 10 9 8 7 6 5 4 3 2
1 0
CR010
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(i) When the CR010 register is used as a compare register The value set in the CR010 register is constantly compared with the TM01 register count value, and an interrupt request signal (INTTM010) is generated if they match. The value is held until the CR010 register is rewritten. (ii) When the CR010 register is used as a capture register The count value of the TM01 register is captured to the CR010 register when a capture trigger is input. As the capture trigger, an edge of a phase reverse to that of the TI010 pin or the valid edge of the TI011 pin can be selected by using the CRC01 or PRM01 register. (b) 16-bit timer capture/compare register 011 (CR011)
After reset: 0000H
15 14
R/W 13 12
Address: FFFFF614H 11 10 9 8 7 6 5 4 3 2
1 0
CR011
(i)
When using the CR011 register as a compare register The value set to the CR011 register and the count value of the TM01 register are always compared and when these values match, an interrupt request signal (INTTM011) is generated.
(ii) When using the CR011 register as a capture register The TM01 register count value is captured to the CR011 register by inputting a capture trigger. The valid edge of the TI010 pin can be selected as the capture trigger. The valid edge of the TI010 pin is set with the PRM01 register. Cautions 1. When the P35 pin is used as the valid edge of TI010 and the timer output function is used, set the P32 pin as the timer output pin (TO01). 2. If clearing of the TMC013 and TMC012 bits to 00 and input of the capture trigger conflict, then the captured data is undefined. 3. To change the mode from the capture mode to the comparison mode, first clear the TMC013 and TMC012 bits to 00, and then change the setting. A value that has been once captured remains stored in the CR010 and CR011 registers unless the device is reset. If the mode has been changed to the comparison mode, be sure to set a comparison value.
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(c) Setting range when used as compare register When the CR010 or CR011 register is used as a compare register, set it as shown below.
Operation * Operation as interval timer * Operation as square-wave output * Operation as external event counter * Operation in the clear & start mode entered by TI010 pin valid edge input * Operation as free-running timer * Operation as PPG output * Operation as one-shot pulse output M < N FFFFH 0000H
Note Note
CR010 Register 0000H < N FFFFH 0000H
Note
CR011 Register M FFFFH Normally, this setting is not used. Mask the match interrupt signal (INTTM011).
0000H
Note
N FFFFH
0000H
Note
M FFFFH
0000H
MN M FFFFH (M N)
N FFFFH (N M)
0000H
Note
Note When 0000H is set, a match interrupt immediately after the timer operation does not occur and timer output is not changed, and the first match timing is as follows. A match interrupt occurs at the timing when the timer counter (TM01 register) is changed from 0000H to 0001H. * When the timer counter is cleared due to overflow * When the timer counter is cleared due to TI010 pin valid edge (when clear & start mode is entered by TI010 pin valid edge input) * When the timer counter is cleared due to compare match (when clear & start mode is entered by match between TM01 and CR010 (CR010 = other than 0000H, CR011 = 0000H))
Timer counter clear TM01 register
Compare register set value (0000H) Operation Timer operation enable bit disabled (00) Operation enabled (other than 00)
Interrupt request signal Interrupt signal is not generated Interrupt signal is generated
Remarks 1. N: CR010 register set value M: CR011 register set value 2. For details of operation enable bits (TMC01.TMC013, TMC01.TMC012 bits), refer to 7.3 (1) 16-bit timer mode control register 01 (TMC01).
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Table 7-2. Capture Operation of CR010 and CR011 Registers
External Input Signal Capture Operation Capture operation of CR010 register CRC011 bit = 1 TI010 pin input (reverse phase) Set values of ES101 and ES100 Position of edge to be captured 01: Rising CRC011 bit = 0 TI011 pin input Set values of ES111 and ES110 Position of edge to be captured 01: Rising TI010 Pin Input TI011 Pin Input
00: Falling
00: Falling
11: Both edges (cannot be captured) Interrupt signal INTTM010 signal is not generated even if value is captured. Capture operation of CR011 register TI010 pin input
Note
11: Both edges
Interrupt signal
INTTM010 signal is generated each time value is captured.
Set values of ES101 and ES100 Position of edge to be captured 01: Rising
00: Falling
11: Both edges
Interrupt signal
INTTM011 signal is generated each time value is captured.
Note The capture operation of the CR011 register is not affected by the setting of the CRC011 bit. Caution To capture the count value of the TM01 register to the CR010 register by using the phase reverse to that input to the TI010 pin, the interrupt request signal (INTTM010) is not generated after the value has been captured. If the valid edge is detected on the TI011 pin during this operation, the capture operation is not performed but the INTTM010 signal is generated as an external interrupt signal. To not use the external interrupt, mask the INTTM010 signal. Remark CRC011: See 7.3 (2) Capture/compare control register 01 (CRC01). ES111, ES110, ES101, ES100: See 7.3 (4) Prescaler mode register 01 (PRM01).
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7.3 Registers
Registers used to control 16-bit timer/event counter 01 are shown below. * 16-bit timer mode control register 01 (TMC01) * Capture/compare control register 01 (CRC01) * 16-bit timer output control register 01 (TOC01) * Prescaler mode register 01 (PRM01) * Selector operation control register 1 (SELCNT1) Remark To use the TI010, TI011, and TO01 pin functions, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. (1) 16-bit timer mode control register 01 (TMC01) TMC01 is an 8-bit register that sets the 16-bit timer/event counter 01 operation mode, the TM01 register clear mode, and output timing, and detects an overflow. Rewriting TMC01 is prohibited during operation (when the TMC013 and TMC012 bits = other than 00). However, it can be changed when the TMC013 and TMC012 bits are cleared to 00 (stopping operation) and when the OVF01 bit is cleared to 0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Cautions 1. 16-bit timer/event counter 01 starts operation at the moment TMC012 and TMC013 are set to values other than 00 (operation stop mode), respectively. Set TMC012 and TMC013 to 00 to stop the operation. 2. Do not access the TMC01 register when the main clock is stopped and the subclock is operating. For details, refer to 3.4.8 (1) (b).
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After reset: 00H
R/W 7
Address: FFFFF616H 6 0 5 0 4 0 3 TMC013 2 TMC012 1 TMC011 <0> OVF01
TMC01
0
TMC013 0
TMC012 0
Enable operation of 16-bit timer/event counter 01 Disables TM01 operation. Stops supplying operating clock. Clears 16-bit timer counter (TM01).
0 1 1
1 0 1
Free-running timer mode Clear & start mode entered by TI010 pin valid edge input
Note 1
Clear & start mode entered upon a match between TM01 and CR010
TMC011 0 1
Note 2
Condition to reverse timer output (TO01) * Match between TM01 and CR010 or match between TM01 and CR011 * Match between TM01 and CR010 or match between TM01 and CR011 * Trigger input of TI010 pin valid edge
OVF01 Clear (0) Set (1)
TM01 register overflow flag Clears OVF01 to 0 or TMC01.TMC013 and TMC01.TMC012 = 00 Overflow occurs.
OVF01 is set to 1 when the value of TM01 changes from FFFFH to 0000H in all the operation modes (free-running timer mode, clear & start mode entered by TI010 pin valid edge input, and clear & start mode entered upon a match between TM01 and CR010). It can also be set to 1 by writing 1 to the OVF01 bit.
Notes 1. 2.
The TI010 pin valid edge is set by the PRM01 register. Be sure to clear the TMC011 bit to 0 when the TO01 pin and TI010 pin are used alternately.
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(2) Capture/compare control register 01 (CRC01) The CRC01 register is the register that controls the operation of the CR010 and CR011 registers. Changing the value of the CRC01 register is prohibited during operation (when the TMC01.TMC013 and TMC01.TMC012 bits = other than 00). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
After reset: 00H R/W 7 CRC01 0 Address: CRC01 FFFFF618H 6 0 5 0 4 0 3 0 2 CRC012 1 CRC011 0 CRC010
CRC012 0 1
CR011 register operating mode selection Operates as compare register Operates as capture register
CRC011 0 1
CR010 register capture trigger selection Captures on valid edge of TI011 pin Captures on valid edge of TI010 pin by reverse phase
Note
The valid edge of the TI011 and TI010 pin is set by the PRM01 register. If PRM01.ES101 and PRM01.ES100 are set to 11 (both edges) when CRC011 is 1, the valid edge of the TI010 pin cannot be detected.
CRC010 0 1
CR010 register operating mode selection Operates as compare register Operates as capture register
If TMC013 and TMC012 are set to 11 (clear & start mode entered upon a match between TM01 and CR010), be sure to set the CRC010 bit to 0.
Note When the valid edge is detected from the TI011 pin, the capture operation is not performed but the INTTM010 signal is generated as an external interrupt signal. Caution To ensure that the capture operation is performed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by the PRM01 or SELCNT1 register.
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(3) 16-bit timer output control register 01 (TOC01) The TOC01 register is an 8-bit register that controls the TO01 pin output. The TOC01 register can be rewritten while only the OSPT01 bit is operating (when the TMC01.TMC013 and TMC01.TMC012 bits = other than 00). Rewriting the other bits is prohibited during operation. However, TOC014 can be rewritten during timer operation as a means to rewrite the CR011 register (see 7.5.1 Rewriting CR011 register during TM01 operation). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Caution Be sure to set the TOC01 register using the following procedure. <1> Set the TOC014 and TOC011 bits to 1. <2> Set only the TOE01 bit to 1. <3> Set either the LVS01 bit or the LVR01 bit to 1. (1/2)
After reset: 00H R/W 7 TOC01 0 Address: FFFFF619H <6> OSPT01 <5> OSPE01 4 TOC014 <3> LVS01 <2> LVR01 1 TOC011 <0> TOE01
OSPT01 0 1 One-shot pulse output
One-shot pulse output trigger via software -
The value of this bit is always "0" when it is read. If it is set to 1, TM01 is cleared and started.
OSPE01 0 1 Successive pulse output One-shot pulse output
One-shot pulse output operation control
One-shot pulse output operates correctly in the free-running timer mode or clear & start mode entered by TI010 pin valid edge input. The one-shot pulse cannot be output in the clear & start mode entered upon a match between the TM01 and CR010 registers.
TOC014 0 1
TO01 pin output control on match between CR011 and TM01 registers Disables inversion operation Enables inversion operation
The interrupt signal (INTTM011) is generated even when the TOC014 bit = 0.
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(2/2)
LVS01 0 0 1 1 LVR01 0 1 0 1 No change Initial value of TO01 pin output is low level (TO01 pin output is cleared to 0). Initial value of TO01 pin output is high level (TO01 pin output is set to 1). Setting prohibited Setting of TO01 pin output status
* The LVS01 and LVR01 bits can be used to set the initial value of the output level of the TO01 pin. If the initial value does not have to be set, leave the LVS01 and LVR01 bits as 001. * Be sure to set the LVS01 and LVR01 bits when TOE01 = 1. The LVS01, LVR01, and TOE01 bits being simultaneously set to 1 is prohibited. * The LVS01 and LVR01 bits are trigger bits. By setting these bits to 1, the initial value of the output level of the TO01 pin can be set. Even if these bits are cleared to 0, output of the TO01 pin is not affected. * The values of the LVS01 and LVR01 bits are always 0 when they are read. * For how to set the LVS01 and LVR01 bits, see 7.5.2 Setting LVS01 and LVR01 bits. TOC011 0 1 TO01 pin output control on match between CR010 and TM01 registers Disables inversion operation Enables inversion operation
The interrupt signal (INTTM010) is generated even when the TOC011 bit = 0.
TOE01 0 1
TO01 pin output control Disables output (TO01 pin output fixed to low level) Enables output
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(4) Prescaler mode register 01 (PRM01) The PRM01 register is the register that sets the TM01 register count clock and TI010 and TI011 pin input valid edges. The PRM011 and PRM010 bits are set in combination with the SELCNT1.ISEL11 bit. Refer to 7.3 (6) Count clock setting for 16-bit timer/event counter 01 for details. Rewriting the PRM01 register is prohibited during operation (when the TMC01.TMC013 and TMC01.TMC012 bits = other than 00). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Cautions 1. Do not apply the following setting when setting the PRM011 and PRM010 bits to 11 (to specify the valid edge of the TI010 pin as a count clock). * Clear & start mode entered by the TI010 pin valid edge * Setting the TI010 pin as a capture trigger 2. If the operation of the 16-bit timer/event counter 01 is enabled when the TI010 or TI011 pin is at high level and when the valid edge of the TI010 or TI011 pin is specified to be the rising edge or both edges, the high level of the TI010 or TI011 pin is detected as a rising edge. Note this when the TI010 or TI011 pin is pulled up. However, the rising edge is not detected when the timer operation has been once stopped and is then enabled again. 3. When the P35 pin is used as the valid edge of TI010 and the timer output function is used, set the P32 pin as the timer output pin (TO01).
After reset: 00H
7 PRM01
R/W
Address: FFFFF617H
6 ES110 5 ES101 4 ES100 3 0 2 0 1 PRM011 0 PRM010
ES111
ES111 0 0 1 1
ES110 0 1 0 1 Falling edge Rising edge Setting prohibited
TI011 pin valid edge selection
Both falling and rising edges
ES101 0 0 1 1
ES100 0 1 0 1 Falling edge Rising edge Setting prohibited
TI010 pin valid edge selection
Both falling and rising edges
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(5) Selector operation control register 1 (SELCNT1) The SELCNT1 register sets the count clock of 16-bit timer/event counter 01. The SELCNT1 register is set in combination with the PRM01.PRM101 and PRM01.PRM100 bits. Refer to 7.3 (6) Count clock setting for 16-bit timer/event counter 01 for details. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
After reset: 00H 7 SELCNT1 0
R/W 6 0
Address: FFFFF30AH 5 0 4 0 3 0 2 0 1 ISEL11 0 0
(6) Count clock setting for 16-bit timer/event counter 01 The count clock for 16-bit timer/event counter 01 is set by using the PRM01.PRM011, PRM01.PRM010, and SELCNT1.ISEL11 bits in combination.
SELCNT1 Register ISEL11 Bit 0 0 0 0 1 1 1 1 PRM01 Register PRM011 Bit 0 0 1 1 0 0 1 1 PRM010 Bit 0 1 0 1 0 1 0 1 fXX fXX/4 INTWT Valid edge of TI0101 fXX/2 fXX/8 fXX/16
ote 2
Selection of Count Clock Count Clock fXX = 20 MHz
Note 1
fXX = 16 MHz
fXX = 10 MHz 100 ns 400 ns - - 200 ns 800 ns 1.6 s
Setting prohibited Setting prohibited 200 ns - - 100 ns 400 ns 800 ns Setting prohibited 250 ns - - 125 ns 500 ns 1.0 s
Notes 1.
When the internal clock is selected, set so as to satisfy the following conditions: VDD = 4.0 to 5.5 V: Count clock 10 MHz VDD = 2.7 to 4.0 V: Count clock 5 MHz
2.
The external clock requires a pulse longer than two cycles of the internal clock (fXX/4).
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7.4 Operation
7.4.1 Interval timer operation If the TMC01.TMC013 and TMC01.TMC012 bits are set to 11 (clear & start mode entered upon a match between the TM01 register and the CR010 register), the count operation is started in synchronization with the count clock. When the value of the TM01 register later matches the value of the CR010 register, the TM01 register is cleared to 0000H and a match interrupt signal (INTTM010) is generated. This INTTM010 signal enables the TM01 register to operate as an interval timer. Remarks 1. For the alternate-function pin settings, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. 2. For enabling the INTTM010 interrupt, refer to CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION. Figure 7-2. Block Diagram of Interval Timer Operation
Clear Count clock 16-bit counter (TM01) Match signal Operable bits TMC013, TMC012 CR010 register INTTM010 signal
Figure 7-3. Basic Timing Example of Interval Timer Operation
N TM01 register 0000H Operable bits (TMC013, TMC012) Compare register (CR010) Compare match interrupt (INTTM010) Interval (N + 1) Interval (N + 1) Interval (N + 1) Interval (N + 1) 00 11 N N N N
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Figure 7-4. Example of Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 01 (TMC01)
TMC013 TMC012 TMC011 0 0 0 0 1 1 0 OVF01 0
Clears and starts on match between TM01 and CR010.
(b) Capture/compare control register 01 (CRC01)
CRC012 CRC011 CRC010 0 0 0 0 0 0 0 0 CR010 used as compare register
(c) 16-bit timer output control register 01 (TOC01)
OSPT01 OSPE01 TOC014 0 0 0 0 LVS01 0 LVR01 0 TOC011 0 TOE01 0
(d) Prescaler mode register 01 (PRM01), selector operation control register 1 (SELCNT1)
ES111 PRM01 0 ES110 0 ES101 0 ES100 0 0 0 PRM011 PRM010 0/1 0/1 SELCNT1 ISEL11 0/1
Selects count clock.
(e) 16-bit timer counter 01 (TM01) By reading the TM01 register, the count value can be read. (f) 16-bit capture/compare register 010 (CR010) If M is set to the CR010 register, the interval time is as follows. * Interval time = (M + 1) x Count clock cycle Setting the CR010 register to 0000H is prohibited. (g) 16-bit capture/compare register 011 (CR011) Usually, the CR011 register is not used for the interval timer function. However, a compare match interrupt (INTTM011) is generated when the set value of the CR011 register matches the value of the TM01 register. Therefore, mask the interrupt request by using the interrupt mask flag (TM0MK11).
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Figure 7-5. Example of Software Processing for Interval Timer Function
N TM01 register 0000H
Operable bits (TMC013, TMC012)
N
N
00
11 N
00
Compare register (CR010) Compare match interrupt (INTTM010) <1>
<2>
<1> Count operation start flow
START
Register initial setting PRM01 register, SELCNT1 register, CRC01 register, CR010 register, port setting
Initial setting of these registers is performed before setting the TMC013 and TMC012 bits to 11.
TMC013, TMC012 bits = 11
Starts count operation
<2> Count operation stop flow
The counter is initialized and counting is stopped by clearing the TMC013 and TMC012 bits to 00.
TMC013, TMC012 bits = 00
STOP
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7.4.2 Square wave output operation When 16-bit timer/event counter 01 operates as an interval timer (see 7.4.1), a square wave can be output from the TO01 pin by setting the TOC01 register to 03H. When the TMC01.TMC013 and TMC01.TMC012 bits are set to 11 (count clear & start mode entered upon a match between the TM01 register and the CR010 register), the counting operation is started in synchronization with the count clock. When the value of the TM01 register later matches the value of the CR010 register, the TM01 register is cleared to 0000H, an interrupt signal (INTTM010) is generated, and output of the TO01 pin is inverted. This TO01 pin output that is inverted at fixed intervals enables TO01 to output a square wave. Remarks 1. For the alternate-function pin settings, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. 2. For enabling the INTTM010 interrupt, refer to CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION. Figure 7-6. Block Diagram of Square Wave Output Operation
Clear Count clock 16-bit counter (TM01) Match signal Operable bits TMC013, TMC012 CR010 register Output controller TO01 pin
INTTM010 signal
Figure 7-7. Basic Timing Example of Square Wave Output Operation
N TM01 register 0000H Operable bits (TMC013, TMC012) Compare register (CR010) TO01 pin output Compare match interrupt (INTTM010) Interval (N + 1) Interval (N + 1) Interval (N + 1) Interval (N + 1) 00 11 N N N N
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Figure 7-8. Example of Register Settings for Square Wave Output Operation (a) 16-bit timer mode control register 01 (TMC01)
TMC013 TMC012 TMC011 0 0 0 0 1 1 0 OVF01 0
Clears and starts on match between TM01 and CR010.
(b) Capture/compare control register 01 (CRC01)
CRC012 CRC011 CRC010 0 0 0 0 0 0 0 0 CR010 used as compare register
(c) 16-bit timer output control register 01 (TOC01)
OSPT01 OSPE01 TOC014 0 0 0 0 LVS01 0/1 LVR01 0/1 TOC011 1 TOE01 1 Enables TO01 pin output. Inverts TO01 pin output on match between TM01 and CR010. Specifies the initial value of TO01 output F/F.
(d) Prescaler mode register 01 (PRM01), selector operation control register 1 (SELCNT1)
ES111 PRM01 0 ES110 0 ES101 0 ES100 0 0 0 PRM011 PRM010 0/1 0/1 SELCNT1 ISEL11 0/1
Selects count clock.
(e) 16-bit timer counter 01 (TM01) By reading the TM01 register, the count value can be read. (f) 16-bit capture/compare register 010 (CR010) If M is set to the CR010 register, the square wave frequency is as follows. 1 / [2 x (M + 1) x Count clock cycle] Setting the CR010 register to 0000H is prohibited. (g) 16-bit capture/compare register 011 (CR011) Usually, the CR011 register is not used for the square wave output function. However, a compare match interrupt (INTTM011) is generated when the set value of the CR011 register matches the value of the TM01 register. Therefore, mask the interrupt request by using the interrupt mask flag (TM0MK11).
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Figure 7-9. Example of Software Processing for Square Wave Output Function
N TM01 register 0000H
Operable bits (TMC013, TMC012)
N
N
00
11 N
00
Compare register (CR010) TO01 pin output Compare match interrupt (INTTM010) TO01 output control bit (TOC011, TOE01) <1>
<2>
<1> Count operation start flow
START
Register initial setting PRM01 register, SELCNT1 register, CRC01 register, TOC01 registerNote, CR010 register, port setting
Initial setting of these registers is performed before setting the TMC013 and TMC012 bits to 11.
TMC013, TMC012 bits = 11
Starts count operation.
<2> Count operation stop flow
The counter is initialized and counting is stopped by clearing the TMC013 and TMC012 bits to 00.
TMC013, TMC012 bits = 00
STOP
Note Care must be exercised when setting the TOC01 register. For details, see 7.3 (3) 16-bit timer output control register 01 (TOC01).
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7.4.3 External event counter operation When the PRM01.PRM011 and PRM01.PRM010 bits are set to 11 (for counting up with the valid edge of the TI010 pin) and the TMC01.TMC013 and TMC01.TMC012 bits are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating matching between the TM01 register and the CR010 register (INTTM010) is generated. To input the external event, the TI010 pin is used. Therefore, the timer/event counter cannot be used as an external event counter in the clear & start mode entered by the TI010 pin valid edge input (when the TMC013 and TMC012 bits = 10). The INTTM010 signal is generated with the following timing. * Timing of generation of INTTM010 signal (second time or later) = Number of times of detection of valid edge of external event x (Set value of the CR010 register + 1) However, the first match interrupt immediately after the timer/event counter has started operating is generated with the following timing. * Number of times of detection of valid edge of external event input x (Set value of the CR010 register + 2) To detect the valid edge, the signal input to the TI010 pin is sampled during the clock cycle of fPRS. The valid edge is not detected until it is detected two times in a row. Therefore, a noise with a short pulse width can be eliminated. Remarks 1. For the alternate-function pin (TI010) settings, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. 2. For enabling the INTTM010 interrupt, refer to CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION. Figure 7-10. Block Diagram of External Event Counter Operation
fXX/4 Clear TI010 pin Edge detection Output controller TO01 pin
16-bit counter (TM01) Match signal
Operable bits TMC013, TMC012 CR010 register
INTTM010 signal
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Figure 7-11. Example of Register Settings in External Event Counter Mode (a) 16-bit timer mode control register 01 (TMC01)
TMC013 TMC012 TMC011 0 0 0 0 1 1 0 OVF01 0
Clears and starts on match between TM01 and CR010.
(b) Capture/compare control register 01 (CRC01)
CRC012 CRC011 CRC010 0 0 0 0 0 0 0 0 CR010 used as compare register
(c) 16-bit timer output control register 01 (TOC01)
OSPT01 OSPE01 TOC014 0 0 0 0/1 LVS01 0/1 LVR01 0/1 TOC011 0/1 TOE01 0/1 0: Disables TO01 output. 1: Enables TO01 output. Specifies initial value of TO01 output F/F. 00: Does not invert TO01 output on match between TM01 and CR010/CR011. 01: Inverts TO01 output on match between TM01 and CR010. 10: Inverts TO01 output on match between TM01 and CR011. 11: Inverts TO01 output on match between TM01 and CR010/CR011.
(d) Prescaler mode register 01 (PRM01), selector operation control register 1 (SELCNT1)
ES111 PRM01 0 ES110 0 ES101 0/1 ES100 0/1 0 0 PRM011 PRM010 1 1 SELCNT1 ISEL11 0
Selects count clock (specifies valid edge of TI010). 00: Falling edge detection 01: Rising edge detection 10: Setting prohibited 11: Both edges detection
(e) 16-bit timer counter 01 (TM01) By reading the TM01 register, the count value can be read. (f) 16-bit capture/compare register 010 (CR010) If M is set to the CR010 register, the interrupt signal (INTTM010) is generated when the number of external events reaches (M + 1). Setting the CR010 register to 0000H is prohibited. (g) 16-bit capture/compare register 011 (CR011) When this register's value matches the count value of the TM01 register, an interrupt signal (INTTM011) is generated. The count value of the TM01 register is not cleared.
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Figure 7-12. Example of Software Processing in External Event Counter Mode
N TM01 register 0000H
Operable bits (TMC013, TMC012) 00
N
N
11 N
00
Compare register (CR010) TO01 pin output Compare match interrupt (INTTM010) TO01 output control bit (TOC014, TOC011, TOE01) <1>
<2>
<1> Count operation start flow
START
Register initial setting PRM01 register, SELCNT1 register, CRC01 register, TOC01 registerNote, CR010 register, port setting
Initial setting of these registers is performed before setting the TMC013 and TMC012 bits to 11.
TMC013, TMC012 bits = 11
Starts count operation.
<2> Count operation stop flow
TMC013, TMC012 bits = 00
The counter is initialized and counting is stopped by clearing the TMC013 and TMC012 bits to 00.
STOP
Note Care must be exercised when setting the TOC01 register. For details, see 7.3 (3) 16-bit timer output control register 01 (TOC01).
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7.4.4 Operation in clear & start mode entered by TI010 pin valid edge input When the TMC01.TMC013 and TMC01.TMC012 bits are set to 10 (clear & start mode entered by the TI010 pin valid edge input) and the count clock (set by the PRM01, SELCNT1 registers) is supplied to the timer/event counter, the TM01 register starts counting up. When the valid edge of the TI010 pin is detected during the counting operation, the TM01 register is cleared to 0000H and starts counting up again. If the valid edge of the TI010 pin is not detected, the TM01 register overflows and continues counting. The valid edge of the TI010 pin is a cause to clear the TM01 register. Starting the counter is not controlled immediately after the start of the operation. The CR010 and CR011 registers are used as compare registers and capture registers. (a) When the CR010 and CR011 registers are used as compare registers Signals INTTM010 and INTTM011 are generated when the value of the TM01 register matches the value of the CR010 and CR011 registers. (b) When the CR010 and CR011 registers are used as capture registers The count value of the TM01 register is captured to the CR010 register and the INTTM010 signal is generated when the valid edge is input to the TI011 pin (or when the phase reverse to that of the valid edge is input to the TI010 pin). When the valid edge is input to the TI010 pin, the count value of the TM01 register is captured to the CR011 register and the INTTM011 signal is generated. As soon as the count value has been captured, the counter is cleared to 0000H. Caution Do not set the count clock as the valid edge of the TI010 pin (RPM01.PRM011 and RPM01.PRM010 bits = 11). When the PRM011 and PRM010 bits = 11, the TM01 register is cleared. Remarks 1. For the alternate-function pin settings, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. 2. For enabling the INTTM010 interrupt, refer to CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION.
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(1) Operation in clear & start mode entered by TI010 pin valid edge input (CR010 register: compare register, CR011 register: compare register) Figure 7-13. Block Diagram of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 register: Compare Register, CR011 register: Compare Register)
TI010 pin
Edge detection Clear
Count clock
16-bit counter (TM01) Match signal Interrupt signal (INTTM010) Output controller TO01 pin Interrupt signal (INTTM011)
Operable bits TMC013, TMC012 Compare register (CR010) Match signal
Compare register (CR011)
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Figure 7-14. Timing Example of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 Register: Compare Register, CR011 Register: Compare Register) (a) TOC01 = 13H, PRM01 = 10H, CRC01 = 00H, TMC01 = 08H
TM01 register 0000H Operable bits (TMC013, TMC012) Count clear input (TI010 pin input) Compare register (CR010) Compare match interrupt (INTTM010) Compare register (CR011) Compare match interrupt (INTTM011) TO01 pin output M 00 10 M N N M N M N M
N
(b) TOC01 = 13H, PRM01 = 10H, CRC01, = 00H, TMC01 = 0AH
TM01 register 0000H Operable bits (TMC013, TMC012) Count clear input (TI010 pin input) Compare register (CR010) Compare match interrupt (INTTM010) Compare register (CR011) Compare match interrupt (INTTM011) TO01 pin output M 00 10 M N N M N M N M
N
(a) and (b) differ as follows depending on the setting of the TMC01 register (TMC011 bit). (a) The output level of the TO01 pin is inverted when the TM01 register matches a compare register. (b) The output level of the TO01 pin is inverted when the TM01 register matches a compare register or when the valid edge of the TI010 pin is detected.
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(2) Operation in clear & start mode entered by TI010 pin valid edge input (CR010 register: compare register, CR011 register: capture register) Figure 7-15. Block Diagram of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 Register: Compare Register, CR011 Register: Capture Register)
TI010 pin
Edge detector Clear
Count clock
16-bit counter (TM01) Match signal Interrupt signal (INTTM010) Output controller TO01 pin
Operable bits TMC013, TMC012 Compare register (CR010)
Capture signal
Capture register (CR011)
Interrupt signal (INTTM011)
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Figure 7-16. Timing Example of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 Register: Compare Register, CR011 Register: Capture Register) (1/2) (a) TOC01 = 13H, PRM01 = 10H, CRC01, = 04H, TMC01 = 08H, CR010 = 0000H
M TM01 register 0000H Operable bits (TMC013, TMC012) Capture & count clear input (TI010 pin input) Compare register (CR010) Compare match interrupt (INTTM010) Capture register (CR011) Capture interrupt (INTTM011) TO01 pin output N S P Q
00
10
0000H
0000H
M
N
S
P
Q
This is an application example where the output level of the TO01 pin is inverted when the count value has been captured & cleared. The count value is captured to the CR011 register and the TM01 register is cleared (to 0000H) when the valid edge of the TI010 pin is detected. When the count value of the TM01 register is 0000H, a compare match interrupt signal (INTTM010) is generated, and the output level of the TO01 pin is inverted.
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Figure 7-16. Timing Example of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 Register: Compare Register, CR011 Register: Capture Register) (2/2) (b) TOC01 = 13H, PRM01 = 10H, CRC01 = 04H, TMC01 = 0AH, CR010 = 0003H
M TM01 register 0003H 0000H Operable bits (TMC013, TMC012) Capture & count clear input (TI010 pin input) Compare register (CR010) Compare match interrupt (INTTM010) Capture register (CR011) Capture interrupt (INTTM011) TO01 pin output 0000H M N S P Q 0003H 00 10 N S P Q
4
4
4
4
This is an application example where the width set to the CR010 register (4 clocks in this example) is to be output from the TO01 pin when the count value has been captured & cleared. The count value is captured to the CR011 register, a capture interrupt signal (INTTM011) is generated, the TM01 register is cleared (to 0000H), and the output level of the TO01 pin is inverted when the valid edge of the TI010 pin is detected. When the count value of the TM01 register is 0003H (four clocks have been counted), a compare match interrupt signal (INTTM010) is generated and the output level of the TO01 pin is inverted.
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(3) Operation in clear & start mode entered by TI010 pin valid edge input (CR010 register: capture register, CR011 register: compare register) Figure 7-17. Block Diagram of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 Register: Capture Register, CR011 Register: Compare Register)
TI010 pin
Edge detection Clear
Count clock
16-bit counter (TM01) Match signal Interrupt signal (INTTM011) Output controller TO01 pin
Operable bits TMC013, TMC012 Compare register (CR011)
Capture signal
Capture register (CR010)
Interrupt signal (INTTM010)
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Figure 7-18. Timing Example of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 Register: Capture Register, CR011 Register: Compare Register) (1/2) (a) TOC01 = 13H, PRM01 = 10H, CRC01 = 03H, TMC01 = 08H, CR011 = 0000H
TM01 register M 0000H Operable bits (TMC013, TMC012) Capture & count clear input (TI010 pin input) Capture register (CR010) Capture interrupt (INTTM010) Compare register (CR011) Compare match interrupt (INTTM011) TO01 pin output N S P
00
10
0000H L 0000H
M
N
S
P
This is an application example where the output level of the TO01 pin is to be inverted when the count value has been captured & cleared. The TM01 register is cleared at the rising edge detection of the TI010 pin and it is captured to the CR010 register at the falling edge detection of the TI010 pin. When the CRC01.CRC011 bit is set to 1, the count value of the TM01 register is captured to CR010 in the phase reverse to that of the signal input to the TI010 pin, but the capture interrupt signal (INTTM010) is not generated. However, the INTTM010 signal is generated when the valid edge of the TI011 pin is detected. Mask the INTTM010 signal when it is not used.
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Figure 7-18. Timing Example of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 Register: Capture Register, CR011 Register: Compare Register) (2/2) (b) TOC01 = 13H, PRM01 = 10H, CRC01 = 03H, TMC01 = 0AH, CR011 = 0003H
TM01 register 0003H 0000H Operable bits (TMC013, TMC012) Capture & count clear input (TI010 pin input) Compare register (CR010) Compare match interrupt (INTTM010) Capture register (CR011) Capture interrupt (INTTM011) TO01 pin output
M N
S
P
00
10
0000H L 0003H
M
N
S
P
4
4
4
4
This is an application example where the width set to the CR011 register (4 clocks in this example) is to be output from the TO01 pin when the count value has been captured & cleared. The TM01 register is cleared (to 0000H) at the rising edge detection of the TI010 pin and captured to the CR010 register at the falling edge detection of the TI010 pin. The output level of the TO01 pin is inverted when the TM01 register is cleared (to 0000H) because the rising edge of the TI010 pin has been detected or when the value of the TM01 register matches that of a compare register (CR011). When the CRC01.CRC011 bit is 1, the count value of the TM01 register is captured to the CR010 register in the phase reverse to that of the input signal of the TI010 pin, but the capture interrupt signal (INTTM010) is not generated. However, the INTTM010 interrupt is generated when the valid edge of the TI011 pin is detected. Mask the INTTM010 signal when it is not used.
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(4) Operation in clear & start mode entered by TI010 pin valid edge input (CR010 register: capture register, CR011 register: capture register) Figure 7-19. Block Diagram of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 Register: Capture Register, CR011 Register: Capture Register)
Operable bits TMC013, TMC012
Clear 16-bit counter (TM01)
Count clock
Capture signal
Capture register (CR011) Output controller
Interrupt signal (INTTM011) TO01 pin Interrupt signal (INTTM010)
Selector
TI010 pin TI011 pin
Edge detection Edge detection
Capture signal
Capture register (CR010)
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Figure 7-20. Timing Example of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 Register: Capture Register, CR011 Register: Capture Register) (1/3)
(a) TOC01 = 13H, PRM01 = 30H, CRC01 = 05H, TMC01 = 0AH
L TM01 register M 0000H Operable bits (TMC013, TMC012) Capture & count clear input (TI010 pin input) Capture register (CR010) Capture interrupt (INTTM010) Capture register (CR011) Capture interrupt (INTTM011) TO01 pin output N O P Q R S T
00
10
0000H L 0000H L M N O P Q R S T
This is an application example where the count value is captured to the CR011 register, the TM01 register is cleared, and the TO01 pin output is inverted when the rising or falling edge of the TI010 pin is detected. When the edge of the TI011 pin is detected, an interrupt signal (INTTM010) is generated. Mask the INTTM010 signal when it is not used.
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Figure 7-20. Timing Example of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 Register: Capture Register, CR011 Register: Capture Register) (2/3) (b) TOC01 = 13H, PRM01 = C0H, CRC01 = 05H, TMC01 = 0AH
FFFFH TM01 register M 0000H Operable bits (TMC013, TMC012) Capture trigger input (TI011 pin input) Capture register (CR010) Capture interrupt (INTTM010) Capture & count clear input (TI010) Capture register (CR011) Capture interrupt (INTTM011) O N P Q S R
L
T
00
10
0000H
L
M
N
O
P
Q
R
S
T
L 0000H L L
TO01 pin output
This is a timing example where an edge is not input to the TI010 pin, in an application where the count value is captured to the CR010 register when the rising or falling edge of the TI011 pin is detected. Because the TO010 pin does not detect any edges, the TO01 pin output is not inverted and remains low level.
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Figure 7-20. Timing Example of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 Register: Capture Register, CR011 Register: Capture Register) (3/3) (c) TOC01 = 13H, PRM01 = 00H, CRC01 = 07H, TMC01 = 0AH
M TM01 register L 0000H Operable bits (TMC013, TMC012) Capture & count clear input (TI010 pin input) Capture register (CR010) Capture register (CR011) Capture interrupt (INTTM011) TO01 pin output Capture input (TI011) Capture interrupt (INTTM010) N P O Q R S T W
00
10
0000H 0000H
L M
N O
P Q
R S
T W
L L
This is an application example where the pulse width of the signal input to the TI010 pin is measured. By setting the CRC01 register, the count value can be captured to the CR010 register in the phase reverse to the falling edge of the TI010 pin (i.e., rising edge) and to the CR011 register at the falling edge of the TI010 pin. The high- and low-level widths of the input pulse can be calculated by the following expressions. * High-level width = [CR011 register value] - [CR010 register value] x [Count clock cycle] * Low-level width = [CR010 register value] x [Count clock cycle] If the reverse phase of the TI010 pin is selected as a trigger to capture the count value to the CR010 register, the INTTM010 signal is not generated. Read the values of the CR010 and CR011 registers to measure the pulse width immediately after the INTTM011 signal is generated. However, if the valid edge specified by the PRM01.ES111 and PRM01.ES110 bits is input to the TI011 pin, the count value is not captured but the INTTM010 signal is generated. To measure the pulse width of the TI010 pin, mask the INTTM010 signal when it is not used.
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Figure 7-21. Example of Register Settings in Clear & Start Mode Entered by TI010 Pin Valid Edge Input (1/2) (a) 16-bit timer mode control register 01 (TMC01)
TMC013 TMC012 TMC011 0 0 0 0 1 0 0/1 OVF01 0 0: Inverts TO01 output on match between CR010 and CR011. 1: Inverts TO01 output on match between CR010 and CR011 and valid edge of TI010 pin. Clears and starts at valid edge input of TI010 pin.
(b) Capture/compare control register 01 (CRC01)
CRC012 CRC011 CRC010 0 0 0 0 0 0/1 0/1 0/1
0: CR010 used as compare register 1: CR010 used as capture register 0: TI011 pin is used as capture trigger of CR010. 1: Reverse phase of TI010 pin is used as capture trigger of CR010. 0: CR011 used as compare register 1: CR011 used as capture register
(c) 16-bit timer output control register 01 (TOC01)
OSPT01 OSPE01 TOC014 0 0 0 0/1 LVS01 0/1 LVR01 0/1 TOC011 0/1 TOE01 0/1 0: Disables TO01 output 1: Enables TO01 output Specifies initial value of TO01 output F/F 00: Does not invert TO01 output on match between TM01 and CR010/CR011. 01: Inverts TO01 output on match between TM01 and CR010. 10: Inverts TO01 output on match between TM01 and CR011. 11: Inverts TO01 output on match between TM01 and CR010/CR011.
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Figure 7-21. Example of Register Settings in Clear & Start Mode Entered by TI010 Pin Valid Edge Input (2/2) (d) Prescaler mode register 01 (PRM01), selector operation control register 1 (SELCNT1)
ES111 PRM01 0/1 ES110 0/1 ES101 0/1 ES100 0/1 0 0 PRM011 PRM010 0/1 0/1 SELCNT1 ISEL11 0/1
Count clock selection (setting TI010 valid edge is prohibited) 00: 01: 10: 11: 00: 01: 10: 11: Falling edge detection Rising edge detection Setting prohibited Both edges detection (setting prohibited when CRC011 = 1) Falling edge detection Rising edge detection Setting prohibited Both edges detection
(e) 16-bit timer counter 01 (TM01) By reading the TM01 register, the count value can be read. (f) 16-bit capture/compare register 010 (CR010) When this register is used as a compare register and when its value matches the count value of the TM01 register, an interrupt signal (INTTM010) is generated. The count value of the TM01 register is not cleared. To use this register as a capture register, select either the TI010 or TI011 pin input as a capture trigger. When the valid edge of the capture trigger is detected, the count value of the TM01 register is stored in the CR010 register. (g) 16-bit capture/compare register 011 (CR011) When this register is used as a compare register and when its value matches the count value of the TM01 register, an interrupt signal (INTTM011) is generated. The count value of the TM01 register is not cleared. When this register is used as a capture register, the TI010 pin input is used as a capture trigger. When the valid edge of the capture trigger is detected, the count value of the TM01 register is stored in the CR011 register.
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Figure 7-22. Example of Software Processing in Clear & Start Mode Entered by TI010 Pin Valid Edge Input
TM01 register 0000H Operable bits (TMC013, TMC012) Count clear input (TI010 pin input) Compare register (CR010) Compare match interrupt (INTTM010) Compare register (CR011) Compare match interrupt (INTTM011) TO01 pin output M N N M N M N M
00
10
00
M
N
<1>
<2>
<2>
<2>
<2>
<3>
<1> Count operation start flow
<3> Count operation stop flow
The counter is initialized and counting is stopped by clearing the TMC013 and TMC012 bits to 00.
START
TMC013, TMC012 bits = 00
Register initial setting PRM01 register, SELCNT1 register, CRC01 register, TOC01 registerNote, CR010, CR011 registers, TMC01.TMC011 bit, port setting
Initial setting of these registers is performed before setting the TMC013 and TMC012 bits to 10.
STOP
TMC013, TMC012 bits = 10
Starts count operation
<2> TM01 register clear & start flow
Edge input to TI010 pin
When the valid edge is input to the TI010 pin, the value of the TM01 register is cleared.
Note Care must be exercised when setting the TOC01 register. For details, see 7.3 (3) 16-bit timer output control register 01 (TOC01).
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7.4.5 Free-running timer operation When the TMC01.TMC013 and TMC01.TMC012 bits are set to 01 (free-running timer mode), 16-bit timer/event counter 01 continues counting up in synchronization with the count clock. When it has counted up to FFFFH, the overflow flag (TMC01.OVF01 bit) is set to 1 at the next clock, and the TM01 register is cleared (to 0000H) and continues counting. Clear the OVF01 bit to 0 by executing the CLR instruction via software. The following three types of free-running timer operations are available. * Both the CR010 and CR011 registers are used as compare registers. * Either the CR010 register or CR011 register is used as a compare register and the other is used as a capture register. * Both the CR010 and CR011 registers are used as capture registers. Remarks 1. For the alternate-function pin (TO01) settings, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. 2. For enabling the INTTM010 and INTTM011 interrupts, refer to CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION. (1) Free-running timer mode operation (CR010 register: compare register, CR011 register: compare register) Figure 7-23. Block Diagram of Free-Running Timer Mode (CR010 Register: Compare Register, CR011 Register: Compare Register)
Count clock
16-bit counter (TM01) Match signal Interrupt signal (INTTM010) Output controller TO01 pin Interrupt signal (INTTM011)
Operable bits TMC013, TMC012 Compare register (CR010) Match signal
Compare register (CR011)
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Figure 7-24. Timing Example of Free-Running Timer Mode (CR010 Register: Compare Register, CR011 Register: Compare Register) * TOC01 = 13H, PRM01 = 00H, CRC01 = 00H, TMC01 = 04H
FFFFH
TM01 register 0000H Operable bits (TMC013, TMC012) Compare register (CR010) Compare match interrupt (INTTM010) Compare register (CR011) Compare match interrupt (INTTM011) TO01 pin output Overflow flag (OVF01) 0 write clear 0 write clear 0 write clear 0 write clear N M N M N M N M
00
01 M
00
N
This is an application example where two compare registers are used in the free-running timer mode. The output level of the TO01 pin is reversed each time the count value of the TM01 register matches the set values of the CR010 and CR011 registers. When the count value matches the register value, the INTTM010 or INTTM011 signal is generated.
(2) Free-running timer mode operation (CR010 register: compare register, CR011 register: capture register) Figure 7-25. Block Diagram of Free-Running Timer Mode (CR010 Register: Compare Register, CR011 Register: Capture Register)
Count clock 16-bit counter (TM01) Match signal Operable bits TMC013, TMC012 Compare register (CR010) Output controller Interrupt signal (INTTM010) TO01 pin
TI010 pin
Edge detection
Capture signal
Capture register (CR011)
Interrupt signal (INTTM011)
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Figure 7-26. Timing Example of Free-Running Timer Mode (CR010 Register: Compare Register, CR011 Register: Capture Register) * TOC01 = 13H, PRM01 = 10H, CRC01 = 04H, TMC01 = 04H
FFFFH
TM01 register 0000H Operable bits (TMC013, TMC012) Capture trigger input (TI010) Compare register (CR010) Compare match interrupt (INTTM010) Compare register (CR011) Capture interrupt (INTTM011) TO01 pin output Overflow flag (OVF01)
M
N
S
P Q
00
01
0000H
0000H
M
N
S
P
Q
0 write clear
0 write clear
0 write clear
0 write clear
This is an application example where a compare register and a capture register are used at the same time in the free-running timer mode. In this example, the INTTM010 signal is generated and the output level of the TO01 pin is reversed each time the count value of the TM01 register matches the set value of the CR010 register (compare register). In addition, the INTTM011 signal is generated and the count value of the TM01 register is captured to the CR011 register each time the valid edge of the TI010 pin is detected.
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(3) Free-running timer mode operation (CR010 register: capture register, CR011 register: capture register) Figure 7-27. Block Diagram of Free-Running Timer Mode (CR010 Register: Capture Register, CR011 Register: Capture Register)
Operable bits TMC013, TMC012 16-bit counter (TM01)
Count clock
Capture signal
Capture register (CR011)
Interrupt signal (INTTM011)
Selector
TI010 pin TI011 pin
Edge detection Edge detection
Capture signal
Capture register (CR010)
Interrupt signal (INTTM010)
Remark
If both the CR010 and CR011 registers are used as capture registers in the free-running timer mode, the output level of the TO01 pin is not inverted. However, it can be inverted each time the valid edge of the TI010 pin is detected if the TMC01.TMC011 bit is set to 1.
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Figure 7-28. Timing Example of Free-Running Timer Mode (CR010 Register: Capture Register, CR011 Register: Capture Register) (1/2) (a) TOC01 = 13H, PRM01 = 0 to 50H, CRC01 = 05H, TMC01 = 04H
FFFFH
M TM01 register A 0000H Operable bits (TMC013, TMC012) Capture trigger input (TI010) Capture register (CR011) Capture interrupt (INTTM011) Capture trigger input (TI011) Capture register (CR010) Capture interrupt (INTTM010) Overflow flag (OVF01) 0 write clear 0 write clear 0 write clear 0 write clear B N C S D P E Q
00
01
0000H
M
N
S
P
Q
0000H
A
B
C
D
E
This is an application example where the count values that have been captured at the valid edges of separate capture trigger signals are stored in separate capture registers in the free-running timer mode. The count value is captured to the CR011 register when the valid edge of the TI010 pin input is detected and to the CR010 register when the valid edge of the TI011 pin input is detected.
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Figure 7-28. Timing Example of Free-Running Timer Mode (CR010 Register: Capture Register, CR011 Register: Capture Register) (2/2) (b) TOC01 = 13H, PRM01 = C0H, CRC01 = 05H, TMC01 = 04H
FFFFH TM01 register 0000H Operable bits (TMC013, TMC012) Capture trigger input (TI011) Capture register (CR010) Capture interrupt (INTTM010) Capture trigger input (TI010) Capture register (CR011) Capture interrupt (INTTM011) M O N P Q S R
L
T
00
01
0000H
L
M
N
O
P
Q
R
S
T
L 0000H L
This is an application example where both the edges of the TI011 pin are detected and the count value is captured to the CR010 register in the free-running timer mode. When both the CR010 and CR011 registers are used as capture registers and when the valid edge of only the TI011 pin is to be detected, the count value cannot be captured to the CR011 register.
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Figure 7-29. Example of Register Settings in Free-Running Timer Mode (1/2) (a) 16-bit timer mode control register 01 (TMC01)
TMC013 TMC012 TMC011 0 0 0 0 0 1 0/1 OVF01 0
0: Inverts TO01 pin output on match between CR010 and CR011. 1: Inverts TO01 pin output on match between CR010 and CR011 and valid edge of TI010 pin. Free-running timer mode
(b) Capture/compare control register 01 (CRC01)
CRC012 CRC011 CRC010 0 0 0 0 0 0/1 0/1 0/1
0: CR010 used as compare register 1: CR010 used as capture register 0: TI011 pin is used as capture trigger of CR010. 1: Reverse phase of TI010 pin is used as capture trigger of CR010. 0: CR011 used as compare register 1: CR011 used as capture register
(c) 16-bit timer output control register 01 (TOC01)
OSPT01 OSPE01 TOC014 0 0 0 0/1 LVS01 0/1 LVR01 0/1 TOC011 0/1 TOE01 0/1 0: Disables TO01 output 1: Enables TO01 output Specifies initial value of TO01 output F/F 00: Does not invert TO01 output on match between TM01 and CR010/CR011. 01: Inverts TO01 output on match between TM01 and CR010. 10: Inverts TO01 output on match between TM01 and CR011. 11: Inverts TO01 output on match between TM01 and CR010/CR011.
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Figure 7-29. Example of Register Settings in Free-Running Timer Mode (2/2) (d) Prescaler mode register 01 (PRM01), selector operation control register 1 (SELCNT1)
ES111 PRM01 0/1 ES110 0/1 ES101 0/1 ES100 0/1 0 0 PRM011 PRM010 0/1 0/1 SELCNT1 ISEL11 0/1
Count clock selection (setting TI010 valid edge is prohibited) 00: 01: 10: 11: Falling edge detection Rising edge detection Setting prohibited Both edges detection (setting prohibited when CRC011 = 1) Falling edge detection Rising edge detection Setting prohibited Both edges detection
00: 01: 10: 11:
(e) 16-bit timer counter 01 (TM01) By reading the TM01 register, the count value can be read. (f) 16-bit capture/compare register 010 (CR010) When this register is used as a compare register and when its value matches the count value of the TM01 register, an interrupt signal (INTTM010) is generated. The count value of the TM01 register is not cleared. To use this register as a capture register, select either the TI010 or TI011 pin input as a capture trigger. When the valid edge of the capture trigger is detected, the count value of the TM01 register is stored in the CR010 register. (g) 16-bit capture/compare register 011 (CR011) When this register is used as a compare register and when its value matches the count value of the TM01 register, an interrupt signal (INTTM011) is generated. The count value of the TM01 register is not cleared. When this register is used as a capture register, the TI010 pin input is used as a capture trigger. When the valid edge of the capture trigger is detected, the count value of the TM01 register is stored in the CR011 register.
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Figure 7-30. Example of Software Processing in Free-Running Timer Mode
FFFFH M TM01 register 0000H Operable bits (TMC013, TMC012) Compare register (CR010) Compare match interrupt (INTTM010) Compare register (CR011) Compare match interrupt (INTTM011) Timer output control bits (TOE01, TOC014, TOC011) TO01 pin output N N M N M N
00
01 M
00
N
<1> <1> Count operation start flow
START
<2>
Register initial setting PRM01 register, SELCNT1 register, CRC01 register, TOC01 registerNote, CR010/CR011 register, TMC01.TMC011 bit, port setting
Initial setting of these registers is performed before setting the TMC013 and TMC012 bits to 01.
TMC013, TMC012 bits = 0, 1
Starts count operation
<2> Count operation stop flow
TMC013, TMC012 bits = 0, 0 The counter is initialized and counting is stopped by clearing the TMC013 and TMC012 bits to 00.
STOP
Note Care must be exercised when setting the TOC01 register. For details, see 7.3 (3) 16-bit timer output control register 01 (TOC01).
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7.4.6 PPG output operation A rectangular wave having a pulse width set in advance by the CR011 register is output from the TO01 pin as a PPG (Programmable Pulse Generator) signal during a cycle set by the CR010 register when the TMC01.TMC013 and TMC01.TMC012 bits are set to 11 (clear & start upon a match between the TM01 register and the CR010 register). The pulse cycle and duty factor of the pulse generated as the PPG output are as follows. * Pulse cycle = (Set value of the CR010 register + 1) x Count clock cycle * Duty = (Set value of the CR011 register + 1) / (Set value of the CR010 register + 1) Caution To change the duty factor (value of the CR011 register) during operation, see 7.5.1 Rewriting CR011 register during TM01 operation. Remarks 1. For the alternate-function pin settings, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. 2. For enabling the INTTM010 and INTTM011 interrupts, refer to CHAPTER 17 EXCEPTION PROCESSING FUNCTION. Figure 7-31. Block Diagram of PPG Output Operation INTERRUPT/
Clear Count clock 16-bit counter (TM01) Match signal Operable bits TMC013, TMC012 Compare register (CR010) Match signal Output controller Interrupt signal (INTTM010) TO01 pin Interrupt signal (INTTM011)
Compare register (CR011)
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Figure 7-32. Example of Register Settings for PPG Output Operation (a) 16-bit timer mode control register 01 (TMC01)
TMC013 TMC012 TMC011 0 0 0 0 1 1 0 OVF01 0
Clears and starts on match between TM01 and CR010.
(b) Capture/compare control register 01 (CRC01)
CRC012 CRC011 CRC010 0 0 0 0 0 0 0 0
CR010 used as compare register CR011 used as compare register
(c) 16-bit timer output control register 01 (TOC01)
OSPT01 OSPE01 TOC014 0 0 0 1 LVS01 0/1 LVR01 0/1 TOC011 1 TOE01 1 Enables TO01 output Specifies initial value of TO01 output F/F 11: Inverts TO01 output on match between TM01 and CR010/CR011. 00: Disables one-shot pulse output
(d) Prescaler mode register 01 (PRM01), selector operation control register 1 (SELCNT1)
ES111 PRM01 0 ES110 0 ES101 0 ES100 0 0 0 PRM011 PRM010 0/1 0/1 SELCNT1 ISEL11 0/1
Selects count clock
(e) 16-bit timer counter 01 (TM01) By reading the TM01 register, the count value can be read. (f) 16-bit capture/compare register 010 (CR010) An interrupt signal (INTTM010) is generated when the value of this register matches the count value of the TM01 register. (g) 16-bit capture/compare register 011 (CR011) An interrupt signal (INTTM011) is generated when the value of this register matches the count value of the TM01 register. Caution Set values to the CR010 and CR011 registers such that the condition 0000H CR011 < CR010 FFFFH is satisfied.
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Figure 7-33. Example of Software Processing for PPG Output Operation
M TM01 register 0000H Operable bits (TMC013, TMC012) Compare register (CR010) Compare match interrupt (INTTM010) Compare register (CR011) Compare match interrupt (INTTM011) Timer output control bits (TOE01, TOC014, TOC011) TO01 pin output N+1 M+1 N+1 M+1 N+1 M+1 N N M N M
00
11 M
00
N
<1> <1> Count operation start flow <2> Count operation stop flow
<2>
START
TMC013, TMC012 bits = 00
The counter is initialized and counting is stopped by clearing the TMC013 and TMC012 bits to 00.
Register initial setting PRM01 register, SELCNT1 register, CRC01 register, TOC01 registerNote, CR010, CR011 registers, port setting
Initial setting of these registers is performed before setting the TMC013 and TMC012 bits.
STOP
TMC013, TMC012 bits = 11
Starts count operation
Note Care must be exercised when setting the TOC01 register. For details, see 7.3 (3) 16-bit timer output control register 01 (TOC01). Remark PPG pulse cycle = (M + 1) x Count clock cycle PPG duty = (N + 1)/(M + 1)
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7.4.7 One-shot pulse output operation A one-shot pulse can be output by setting the TMC01.TMC013 and TMC01.TMC012 bits to 01 (free-running timer mode) or to 10 (clear & start mode entered by the TI010 pin valid edge) and setting the TOC01.OSPE01 bit to 1. When the TOC01.OSPT01 is set to 1 or when the valid edge is input to the TI010 pin during timer operation, clearing & starting of the TM01 register is triggered, and a pulse of the difference between the values of the CR010 and CR011 registers is output only once from the TO01 pin. Caution Do not input the trigger again (setting OSPT01 to 1 or detecting the valid edge of the TI010 pin) while the one-shot pulse is output. To output the one-shot pulse again, generate the trigger after the current one-shot pulse output has completed. Remarks 1. For the alternate-function pin settings, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. 2. For enabling the INTTM010 and INTTM011 interrupts, refer to CHAPTER 17 EXCEPTION PROCESSING FUNCTION. Figure 7-34. Block Diagram of One-Shot Pulse Output Operation INTERRUPT/
TI010 edge detection OSPT01 bit OSPE01 bit Count clock
Clear
16-bit counter (TM01) Match signal Interrupt signal (INTTM010) Output controller TO01 pin Interrupt signal (INTTM011)
Operable bits TMC013, TMC012 Compare register (CR010) Match signal
Compare register (CR011)
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Figure 7-35. Example of Register Settings for One-Shot Pulse Output Operation (1/2) (a) 16-bit timer mode control register 01 (TMC01)
TMC013 TMC012 TMC011 0 0 0 0 0/1 0/1 0 OVF01 0
01: Free running timer mode 10: Clear and start mode by valid edge of TI010 pin.
(b) Capture/compare control register 01 (CRC01)
CRC012 CRC011 CRC010 0 0 0 0 0 0 0 0
CR010 used as compare register CR011 used as compare register
(c) 16-bit timer output control register 01 (TOC01)
OSPT01 OSPE01 TOC014 0 0/1 1 1 LVS01 0/1 LVR01 0/1 TOC011 1 TOE01 1 Enables TO01 pin output Specifies initial value of TO01 pin output Inverts TO01 output on match between TM01 and CR010/CR011. Enables one-shot pulse output Software trigger is generated by writing 1 to this bit (operation is not affected even if 0 is written to it).
(d) Prescaler mode register 01 (PRM01), selector operation control register 1 (SELCNT1)
ES111 PRM01 0 ES110 0 ES101 0 ES100 0 0 0 PRM011 PRM010 0/1 0/1 SELCNT1 ISEL11 0/1
Selects count clock
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Figure 7-35. Example of Register Settings for One-Shot Pulse Output Operation (2/2) (e) 16-bit timer counter 01 (TM01) By reading the TM01 register, the count value can be read. (f) 16-bit capture/compare register 010 (CR010) This register is used as a compare register when a one-shot pulse is output. When the value of the TM01 register matches that of the CR010 register, an interrupt signal (INTTM010) is generated and the output level of the TO01 pin is inverted. (g) 16-bit capture/compare register 011 (CR011) This register is used as a compare register when a one-shot pulse is output. When the value of the TM01 register matches that of the CR011 register, an interrupt signal (INTTM011) is generated and the output level of the TO01 pin is inverted.
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Figure 7-36. Example of Software Processing for One-Shot Pulse Output Operation (1/2)
FFFFH N TM01 register 0000H
Operable bits (TMC013, TMC012)
N M M
N
M
00
01 or 10
00
One-shot pulse enable bit (OSPE1) One-shot pulse trigger bit (OSPT1) One-shot pulse trigger input (TI010 pin) Overflow plug (OVF01) Compare register (CR010) Compare match interrupt (INTTM010) Compare register (CR011) Compare match interrupt (INTTM011) TO01 pin output M+1 TO01 output control bits (TOE01, TOC014, TOC011) <1> <2> N-M M+1 N-M M N
TO01 output level is not inverted because no oneshot trigger is input.
<2>
<3>
* Time from when the one-shot pulse trigger is input until the one-shot pulse is output = (M + 1) x Count clock cycle * One-shot pulse output active level width = (N - M) x Count clock cycle
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Figure 7-36. Example of Software Processing for One-Shot Pulse Output Operation (2/2)
<1> Count operation start flow
START
Register initial setting PRM01 register, SELCNT1 register, CRC01 register, TOC01 registerNote, CR010, CR011 registers, port setting
Initial setting of these registers is performed before setting the TMC013 and TMC012 bits.
TMC013, TMC012 bits = 01 or 10
Starts count operation
<2> One-shot trigger input flow
TOC01.OSPT01 bit = 1 or edge input to TI010 pin
Write the same value to the bits other than the OSPT01 bit.
<3> Count operation stop flow
TMC013, TMC012 bits = 00
The counter is initialized and counting is stopped by clearing the TMC013 and TMC012 bits to 00.
STOP
Note Care must be exercised when setting the TOC01 register. For details, see 7.3 (3) 16-bit timer output control register 01 (TOC01).
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7.4.8 Pulse width measurement operation The TM01 register can be used to measure the pulse width of the signal input to the TI010 and TI011 pins. Measurement can be accomplished by operating the 16-bit timer/event counter 01 in the free-running timer mode or by restarting the timer in synchronization with the signal input to the TI010 pin. When an interrupt is generated, read the value of the valid capture register and measure the pulse width. Check the TMC01.OVF01 flag. If it is set (to 1), clear it to 0 by software. Figure 7-37. Block Diagram of Pulse Width Measurement (Free-Running Timer Mode)
Operable bits TMC013, TMC012 16-bit counter (TM01)
Count clock
Capture signal
Capture register (CR011)
Interrupt signal (INTTM011)
Selector
TI010 pin TI011 pin
Edge detection Edge detection
Capture signal
Capture register (CR010)
Interrupt signal (INTTM010)
Figure 7-38. Block Diagram of Pulse Width Measurement (Clear & Start Mode Entered by TI010 Pin Valid Edge Input)
Operable bits TMC013, TMC012
Clear 16-bit counter (TM01)
Count clock
Capture signal
Capture register (CR011)
Interrupt signal (INTTM011)
Selector
TI010 pin TI011 pin
Edge detection Edge detection
Capture signal
Capture register (CR010)
Interrupt signal (INTTM010)
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A pulse width can be measured in the following three ways. * Measuring the pulse width by using two input signals of the TI010 and TI011 pins (free-running timer mode) * Measuring the pulse width by using one input signal of the TI010 pin (free-running timer mode) * Measuring the pulse width by using one input signal of the TI010 pin (clear & start mode entered by the TI010 pin valid edge input) (1) Measuring the pulse width by using two input signals of the TI010 and TI011 pins (free-running timer mode) Set the free-running timer mode (the TMC01.TMC013 and TMC01.TMC012 bits = 01). When the valid edge of the TI010 pin is detected, the count value of the TM01 register is captured to the CR011 register. When the valid edge of the TI011 pin is detected, the count value of the TM01 register is captured to the CR010 register. Specify detection of both the edges of the TI010 and TI011 pins. By this measurement method, the previous count value is subtracted from the count value captured by the edge of each input signal. Therefore, save the previously captured value to a separate register in advance. If an overflow occurs, the value becomes negative if the previously captured value is simply subtracted from the current captured value and, therefore, a borrow occurs (the PSW.CY bit is set to 1). If this happens, ignore CY and take the calculated value as the pulse width. In addition, clear the TMC01.OVF01 bit to 0. Figure 7-39. Timing Example of Pulse Width Measurement (1) * TMC01 = 04H, PRM01 = F0H, CRC01 = 05H
FFFFH TM01 register A 0000H Operable bits (TMC013, TMC012) Capture trigger input (TI010) Capture register (CR011) Capture interrupt (INTTM011) Capture trigger input (TI011) Capture register (CR010) Capture interrupt (INTTM010) Overflow flag (OVF01) 0 write clear 0 write clear 0 write clear 0 write clear M B N C S D P E Q
00
01
0000H
M
N
S
P
Q
0000H
A
B
C
D
E
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(2) Measuring the pulse width by using one input signal of the TI010 pin (free-running timer mode) Set the free-running timer mode (the TMC01.TMC013 and TMC01.TMC012 bits = 01). The count value of the TM01 register is captured to the CR010 register in the phase reverse to the valid edge detected on the TI010 pin. When the valid edge of the TI010 pin is detected, the count value of the TM01 register is captured to the CR011 register. By this measurement method, values are stored in separate capture registers when a width from one edge to another is measured. Therefore, the capture values do not have to be saved. By subtracting the value of one capture register from that of another, a high-level width, low-level width, and cycle are calculated. If an overflow occurs, the value becomes negative if one captured value is simply subtracted from another and, therefore, a borrow occurs (the PSW.CY bit is set to 1). If this happens, ignore CY and take the calculated value as the pulse width. In addition, clear the TMC01.OVF01 bit to 0. Figure 7-40. Timing Example of Pulse Width Measurement (2) * TMC01 = 04H, PRM01 = 10H, CRC01 = 07H
FFFFH TM01 register 0000H Operable bits (TMC013, TMC012) Capture trigger input (TI010) Capture register (CR010) Capture register (CR011) Capture interrupt (INTTM011) Overflow flag (OVF01) 0 write clear Capture trigger input (TI011) Capture interrupt (INTTM010) 0 write clear 0 write clear 0 write clear M A B N C S D P E Q
00
01
0000H 0000H
A M
B N
C S
D P
E Q
L L
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(3) Measuring the pulse width by using one input signal of the TI010 pin (clear & start mode entered by the TI010 pin valid edge input) Set the clear & start mode entered by the TI010 pin valid edge (the TMC01.TMC013 and TMC01.TMC012 bits = 10). The count value of the TM01 register is captured to the CR010 register in the phase reverse to the valid edge of the TI010 pin, and the count value of the TM01 register is captured to the CR011 register and the TM01 register is cleared (0000H) when the valid edge of the TI010 pin is detected. Therefore, a cycle is stored in the CR011 register if the TM01 register does not overflow. If an overflow occurs, take the value that results from adding 10000H to the value stored in the CR011 register as a cycle. Clear the TMC01.OVF01 bit to 0. Figure 7-41. Timing Example of Pulse Width Measurement (3) * TMC01 = 08H, PRM01 = 10H, CRC01 = 07H
FFFFH TM01 register 0000H Operable bits 00 (TMC013, TMC012) Capture & count clear input (TI010) <2> Capture register (CR010) Capture register (CR011) Capture interrupt (INTTM011) Overflow flag (OVF01) 0 write clear Capture trigger input (TI011) L Capture interrupt (INTTM010) L <3> <2> <3> <2> <3> <2> <3> M A N P C S D Q
B
10
<1> <1> <1> <1>
00
0000H 0000H M
A N
B S
C P
D Q
<1> <2> <3>
Pulse cycle =
(10000H x Number of times OVF01 bit is set to 1 + Captured value of the CR011 register) x Count clock cycle
High-level pulse width = (10000H x Number of times OVF01 bit is set to 1 + Captured value of the CR010 register) x Count clock cycle Low-level pulse width = (Pulse cycle - High-level pulse width)
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Figure 7-42. Example of Register Settings for Pulse Width Measurement (1/2) (a) 16-bit timer mode control register 01 (TMC01)
TMC013 TMC012 TMC011 0 0 0 0 0/1 0/1 0 OVF01 0
01: Free running timer mode 10: Clear and start mode entered by valid edge of TI010 pin.
(b) Capture/compare control register 01 (CRC01)
CRC012 CRC011 CRC010 0 0 0 0 0 1 0/1 1
1: CR010 used as capture register 0: TI011 pin is used as capture trigger of CR010. 1: Reverse phase of TI010 pin is used as capture trigger of CR010. 1: CR011 used as capture register
(c) 16-bit timer output control register 01 (TOC01)
OSPT01 OSPE01 TOC014 0 0 0 0 LVS01 0 LVR01 0 TOC011 0 TOE01 0
(d) Prescaler mode register 01 (PRM01), selector operation control register 1 (SELCNT1)
ES111 PRM01 0/1 ES110 0/1 ES101 0/1 ES100 0/1 0 0 PRM011 PRM010 0/1 0/1 SELCNT1 ISEL11 0/1
Selects count clock (setting valid edge of TI010 is prohibited) 00: 01: 10: 11: 00: 01: 10: 11: Falling edge detection Rising edge detection Setting prohibited Both edges detection (setting when CRC011 = 1 is prohibited) Falling edge detection Rising edge detection Setting prohibited Both edges detection
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Figure 7-42. Example of Register Settings for Pulse Width Measurement (2/2) (e) 16-bit timer counter 01 (TM01) By reading the TM01 register, the count value can be read. (f) 16-bit capture/compare register 010 (CR010) This register is used as a capture register. Either the TI010 or TI011 pin is selected as a capture trigger. When a specified edge of the capture trigger is detected, the count value of the TM01 register is stored in the CR010 register. (g) 16-bit capture/compare register 011 (CR011) This register is used as a capture register. The signal input to the TI010 pin is used as a capture trigger. When the capture trigger is detected, the count value of the TM01 register is stored in the CR011 register.
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Figure 7-43. Example of Software Processing for Pulse Width Measurement (1/2) (a) Example of free-running timer mode
FFFFH D10 TM01 register 0000H Operable bits (TMC013, TMC012) Capture trigger input (TI010) Capture register (CR011) Capture interrupt (INTTM011) Capture trigger input (TI011) Capture register (CR010) Capture interrupt (INTTM010) D00 D01 D11 D02 D12 D03 D13 D04
00
01
00
0000H
D10
D11
D12
D13
0000H
D00
D01
D02
D03
D04
<1> <2> <2>
<2>
<2>
<2> <2>
<2>
<2>
<2><3>
(b) Example of clear & start mode entered by TI010 pin valid edge
FFFFH TM01 register 0000H Operable bits (TMC013, TMC012) Capture & count clear input (TI010) Capture register 0000H (CR010) Capture interrupt (INTTM010) L D0 D2 D4 D6 D8 D1 D3 D5 D7 D0 D1 D4 D2 D3 D6 D8 D7
D5
00
10
00
Capture register (CR011) 0000H Capture interrupt (INTTM011)
<1>
<2> <2>
<2>
<2>
<2>
<2> <2>
<2> <2> <3>
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Figure 7-43. Example of Software Processing for Pulse Width Measurement (2/2)
<1> Count operation start flow
START
Register initial setting PRM01 register, SELCNT1 register, CRC01 register, port setting
Initial setting of these registers is performed before setting the TMC013 and TMC012 bits.
TMC013, TMC012 bits = 01 or 10
Starts count operation
<2> Capture trigger input flow
Edge detection of TI010, TI011 pins
Stores count value to CR010, CR011 registers. Generates capture interruptNote. Calculated pulse width from capture value
<3> Count operation stop flow
TMC013, TMC012 bits = 00
The counter is initialized and counting is stopped by clearing the TMC013 and TMC012 bits to 00.
STOP
Note The capture interrupt signal (INTTM010) is not generated when the reverse-phase edge of the TI010 pin input is selected to the valid edge of the CR010 register.
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7.5 Special Use of TM01
7.5.1 Rewriting CR011 register during TM01 operation In principle, rewriting the CR010 and CR011 registers of the V850ES/KE2 when they are used as compare registers is prohibited while the TM01 register is operating (TMC01.TMC013 and TMC01.TMC012 bits = other than 00). However, the value of the CR011 register can be changed, even while the TM01 register is operating, using the following procedure if the CR011 register is used for PPG output and the duty factor is changed (change the value of the CR011 register immediately after its value matches the value of the TM01 register. If the value of the CR011 register is changed immediately before its value matches the TM01 register, an unexpected operation may be performed). Procedure for changing value of the CR011 register <1> Disable interrupt INTTM011 (TM0IC10.TM0MK11 bit = 1). <2> Disable reversal of the timer output when the value of the TM01 register matches that of the CR011 register (TOC01.TOC014 bit = 0). <3> Change the value of the CR011 register. <4> Wait for one cycle of the count clock of the TM01 register. <5> Enable reversal of the timer output when the value of the TM01 register matches that of the CR011 register (TOC01.TOC014 bit = 1). <6> Clear the interrupt flag of INTTM011 to 0 (TM0IC10.TM0IF11 bit = 0). <7> Enable interrupt INTTM011 (TM0IC10.TM0MK11 bit = 0). Remark For the TM0IC10 register, see CHAPTER 17 FUNCTION. 7.5.2 Setting LVS01 and LVR01 bits (1) Usage of the LVS01 and LVR01 bits The TOC01.LVS01 and TOC01.LVR01 bits are used to set the default value of the TO01 pin output and to invert the timer output without enabling the timer operation (TMC01.TMC013 and TMC01.TMC012 bits = 00). Clear the LVS01 and LVR01 bits to 00 (default value: low-level output) when software control is unnecessary.
LVS01 Bit 0 0 1 1 LVR01 Bit 0 1 0 1 Timer Output Status Not changed (low-level output) Cleared (low-level output) Set (high-level output) Setting prohibited
INTERRUPT/EXCEPTION PROCESSING
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(2) Setting the LVS01 and LVR01 bits Set the LVS01 and LVR01 bits using the following procedure. Figure 7-44. Example of Flow for Setting LVS01 and LVR01 Bits
Setting TOC01.OSPE01, TOC014, TOC011 bits <1> Setting of timer output operation Setting TOC01.TOE01 bit Setting TOC01.LVS01, LVR01 bits Setting TMC01.TMC013, TMC012 bits <2> Setting of timer output F/F <3> Enabling timer operation
Caution Be sure to set the LVS01 and LVR01 bits following steps <1>, <2>, and <3> above. Step <2> can be performed after <1> and before <3>.
Figure 7-45. Timing Example of LVR01 and LVS01 Bits
TOC01.LVS01 bit TOC01.LVR01 bit Operable bits (TMC013, TMC012) TO01 pin output INTTM010 signal <1> <2> <1> <3> <4> <4> <4> 00 01, 10, or 11
<1> The TO01 pin output goes high when the LVS01 and LVR01 bits = 10. <2> The TO01 pin output goes low when the LVS01 and LVR01 bits = 01 (the pin output remains unchanged from the high level even if the LVS01 and LVR01 bits are cleared to 00). <3> The timer starts operating when the TMC013 and TMC012 bits are set to 01, 10, or 11. Because the LVS01 and LVR01 bits were set to 10 before the operation was started, the TO01 pin output starts from the high level. After the timer starts operating, setting the LVS01 and LVR01 bits is prohibited until the TMC013 and TMC012 bits = 00 (disabling the timer operation). <4> The output level of the TO01 pin is inverted each time an interrupt signal (INTTM010) is generated.
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7.6 Cautions
(1) Alternate functions of TI010/TO01 pins
Channel TM01 Pin TI010 TI011 TO01 Alternate function P35/TO01 P50/KR0/RTP00 P32/ASCK0/ADTRG P35/TI010 Remarks Shares the pin with TO01. - Assigned to two pins, P32 and P35.
* To perform the one-shot pulse output with detecting the valid edge of the TI010 pin as a trigger, use the output of the TO01 pin that functions alternately as P32. When using the output of the TO01 pin that functions alternately as P35, the TI010 pin that functions alternately as P35 cannot be used. When using only a software trigger (setting (1) TOC01.OSPT01 bit ) as the start trigger for the one-shot pulse output, either of the P32 and P35 pins can be used as the TO01 pin output. * To perform the TO01 pin output inversion operation by detecting the valid edge of the TI010 pin input, use the output of the TO01 pin that functions alternately as P32. When using the output of the TO01 pin that functions alternately as P35, the TI010 pin that functions alternately as P35 cannot be used. Therefore, the TO01 pin output inversion operation by detecting the valid edge of the TI010 pin input cannot be performed. When using the TO01 pin that functions alternately as P35, clear the TMC01.TMC011 bit to 0. (2) Error on starting timer An error of up to 1 clock occurs before the match signal is generated after the timer has been started. This is because the count of the TM01 register is started asynchronously to the count pulse. Figure 7-46. Count Start Timing of TM01 Register
Count pulse TM01 count value 0000H Timer start 0001H 0002H 0003H 0004H
(3) Setting CR010 and CR011 registers (in the mode in which clear & start occurs upon match between TM01 register and CR010 register) Set the CR010 and CR011 registers to a value other than 0000H (when using these registers as external event counters, one-pulse count operation is not possible).
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(4) Data hold timing of capture register (a) If the valid edge of the TI011/TI010 pin is input while the CR010/CR011 register is read, the CR010/CR011 register performs capture operation, but the read value at this time is not guaranteed. However, the interrupt request signal (INTTM010/INTTM011) is generated as a result of detection of the valid edge. Figure 7-47. Data Hold Timing of Capture Register
Count pulse TM01 count value Edge input INTTM011 Capture read signal Value captured to CR011 X Capture operation N+1 Capture operation is performed but read value is not guaranteed. N N+1 N+2 M M+1 M+2
(b) The values of the CR010 and CR011 registers are not guaranteed after 16-bit timer/event counter 01 has stopped. (5) Setting valid edge Set the valid edge of the TI010 pin while the timer operation is stopped (TMC01.TMC013 and TMC01.TMC012 bits = 00). Set the valid edge by using the PRM01.ES100 and PRM01.ES101 bits. (6) Re-triggering one-shot pulse Make sure that the trigger is not generated while an active level is being output in the one-shot pulse output mode. Be sure to input the next trigger after the current active level is output.
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(7) Operation of OVF01 flag (a) Setting of OVF01 flag The TMC01.OVF01 flag is set to 1 in the following case in addition to when the TM01 register overflows. Select the mode in which clear & start occurs upon match between the TM01 register and the CR010 register. Set the CR010 register to FFFFH When the TM01 register is cleared from FFFFH to 0000H upon match with the CR010 register Figure 7-48. Operation Timing of OVF01 Flag
Count pulse CR010 TM01 OVF01 INTTM010 FFFFH FFFEH FFFFH 0000H 0001H
(b) Clearing of OVF01 flag After the TM01 register overflows, clearing OVF01 flag is invalid and set (1) again even if the OVF01 flag is cleared (0) before the next count clock is counted (before TM01 register becomes 0001H). (8) One-shot pulse output One-shot pulse output operates normally in either the free-running timer mode or the mode in which clear & start occurs on the valid edge of the TI010 pin. In the mode in which clear & start occurs upon match between the TM01 register and the CR010 register, one-shot pulse output is not possible.
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(9) Capture operation (a) If valid edge of TI010 pin is specified for count clock If the valid edge of the TI010 pin is specified for the count clock, the capture register that specified the TI010 pin as the trigger does not operate normally. (b) To ensure that signals input from TI011 and TI010 pins are correctly captured To accurately capture the count value, the pulse input to the TI010 and TI011 pins as a capture trigger must be wider than two count clocks selected by the PRM01 and SELCNT1 registers. (c) Interrupt signal generation Although a capture operation is performed at the falling edge of the count clock, an interrupt request signal (INTTM010, INTTM011) is generated at the rising edge of the next count clock. (d) Note when CRC01.CRC011 bit is set to 1 When the count value of the TM01 register is captured to the CR010 register in the phase reverse to the signal input to the TI010 pin, the interrupt signal (INTTM010) is not generated after the count value is captured. If the valid edge is detected on the TI011 pin during this operation, the capture operation is not performed but the INTTM010 signal is generated as an external interrupt signal. Mask the INTTM010 signal when the external interrupt is not used. (10) Edge detection (a) Specifying valid edge after reset If the operation of the 16-bit timer/event counter 01 is enabled after reset and while the TI010 or TI011 pin is at high level and when the rising edge or both the edges are specified as the valid edge of the TI010 or TI011 pin, then the high level of the TI010 or TI011 pin is detected as the rising edge. Note this when the TI010 or TI011 pin is pulled up. However, the rising edge is not detected when the operation is once stopped and then enabled again. (b) Sampling clock for noise elimination The sampling clock for noise elimination differs depending on whether the valid edge of TI010 is used for the count clock or as a capture trigger. In the former case, sampling is performed using fXX/4, and in the latter case, sampling is performed using the count clock selected by the PRM01 and SELCNT1 registers. When the signal input to the TI010 pin is sampled and the valid level is detected two times in a row, the valid edge is detected. Therefore, noise having a short pulse width can be eliminated. Remark fXX: Main clock frequency
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In the V850ES/KE2, two channels of 8-bit timer/event counter 5 are provided.
8.1 Functions
8-bit timer/event counter 5n has the following two modes (n = 0, 1). * Mode using 8-bit timer/event counter alone (individual mode) * Mode using cascade connection (16-bit resolution: cascade connection mode) These two modes are described below. (1) Mode using 8-bit timer/event counter alone (individual mode) 8-bit timer/event counter 5n operates as an 8-bit timer/event counter. The following functions can be used. * Interval timer * External event counter * Square-wave output * PWM output (2) Mode using cascade connection (16-bit resolution: cascade connection mode) 8-bit timer/event counter 5n operates as a 16-bit timer/event counter by connecting the TM5n register in cascade. The following functions can be used. * Interval timer with 16-bit resolution * External event counter with 16-bit resolution * Square-wave output with 16-bit resolution The block diagram of 8-bit timer/event counter 5n is shown next.
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Figure 8-1. Block Diagram of 8-Bit Timer/Event Counter 5n
Internal bus
Mask circuit
8-bit timer compare register 5n (CR5n) Match
Selector
Selector
INTTM5n
TI5n
Count clockNote
8-bit timer counter 5n (TM5n)
OVF
S INV Q R
Selector
TO5n
Clear
3
Selector
S R
Q
Invert level
TCL5n2 TCL5n1 TCL5n0
Timer clock selection register 5n (TCL5n)
TCE5n TMC5n6 TMC5n4 LVS5n LVR5n TMC5n1 TOE5n
8-bit timer mode control register 5n (TMC5n) Internal bus
Note The count clock is set by the TCL5n register. Remark n = 0, 1
8.2 Configuration
8-bit timer/event counter 5n includes the following hardware. Table 8-1. Configuration of 8-Bit Timer/Event Counter 5n
Item Timer registers 8-bit timer counter 5n (TM5n) 16-bit timer counter 5 (TM5): Only when using cascade connection Registers 8-bit timer compare register 5n (CR5n) 16-bit timer compare register 5 (CR5): Only when using cascade connection Timer output Control registers
Note
Configuration
1 (TO5n pin) Timer clock selection register 5n (TCL5n) 8-bit timer mode control register 5n (TMC5n) 16-bit timer mode control register 5 (TMC5): Only when using cascade connection
Note When using the functions of the TI5n and TO5n pins, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. Remark n = 0, 1
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(1) 8-bit timer counter 5n (TM5n) The TM5n register is an 8-bit read-only register that counts the count pulses. The counter is incremented in synchronization with the rising edge of the count clock. Through cascade connection, the TM5n registers can be used as a 16-bit timer. When using the TM50 register and the TM51 register in cascade as a 16-bit timer, these registers can be read only in 16-bit units. Therefore, read these registers twice and compare the values, taking into consideration that the reading occurs during a count change.
After reset: 00H 7 TM5n (n = 0, 1)
R 6
Address: TM50 FFFFF5C0H, TM51 FFFFF5C1H 5 4 3 2
1 0
The count value is reset to 00H in the following cases. <1> Reset <2> When the TMC5n.TCE5n bit is cleared (0) <3> The TM5n register and CR5n register match in the mode in which clear & start occurs on a match between the TM5n register and the CR5n register Caution When connected in cascade, these registers become 0000H even when the TCE50 bit in the lowest timer (TM50) is cleared. Remark n = 0, 1
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(2) 8-bit timer compare register 5n (CR5n) The CR5n register can be read and written in 8-bit units. In a mode other than the PWM mode, the value set to the CR5n register is always compared to the count value of the TM5n register, and if the two values match, an interrupt request signal (INTTM5n) is generated. In the PWM mode, TM5n register overflow causes the TO5n pin output to change to the active level, and when the values of the TM5n register and the CR5n register match, the TO5n pin output changes to the inactive level. The value of the CR5n register can be set in the range of 00H to FFH. When using the TM50 register and TM51 register in cascade as a 16-bit timer, the CR50 register and CR51 register operate as 16-bit timer compare register 5 (CR5). The counter value and register value are compared in 16-bit lengths, and if they match, an interrupt request signal (INTTM50) is generated.
After reset: 00H 7 CR5n (n = 0, 1)
R/W 6
Address: CR50 FFFFF5C2H, CR51 FFFFF5C3H 5 4 3 2
1 0
Cautions 1. In the mode in which clear & start occurs upon a match of the TM5n register and CR5n register (TMC5n.TMC5n6 bit = 0), do not write a different value to the CR5n register during the count operation. 2. In the PWM mode, set the CR5n register rewrite interval to three or more count clocks (clock selected with the TCL5n register). 3. Before changing the value of the CR5n register when using a cascade connection, be sure to stop the timer operation. Remark n = 0, 1
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8.3 Registers
The following two registers are used to control 8-bit timer/event counter 5n. * Timer clock selection register 5n (TCL5n) * 8-bit timer mode control register 5n (TMC5n) Remark To use the functions of the TI5n and TO5n pins, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. (1) Timer clock selection register 5n (TCL5n) The TCL5n register sets the count clock of 8-bit timer/event counter 5n and the valid edge of the TI5n pin input. The TCL5n register can be read or written in 8-bit units. Reset sets this register to 00H.
After reset: 00H 7 TCL5n (n = 0, 1) 0
R/W 6 0
Address: TCL50 FFFFF5C4H, TCL51 FFFFF5C5H 5 0 4 0 3 0 2 TCL5n2 1 TCL5n1 0 TCL5n0
TCL5n2 TCL5n1 TCL5n0
Clock
Count clock selectionNote
fXX 20 MHz 10 MHz - -
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Falling edge of TI5n Rising edge of TI5n fXX fXX/2 fXX/4 fXX/64 fXX/256 INTTM010
- -
Setting prohibited 100 ns
100 ns 200 ns 3.2 s 12.8 s -
200 ns 0.4 s 6.4 s 25.6 s -
Note When the internal clock is selected, set so as to satisfy the following conditions. VDD = 4.0 to 5.5 V: Count clock 10 MHz VDD = 2.7 to 4.0 V: Count clock 5 MHz Caution Before overwriting the TCL5n register with different data, stop the timer operation. Remark When the TM5n register is connected in cascade, the TCL51 register settings are invalid.
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(2) 8-bit timer mode control register 5n (TMC5n) The TMC5n register performs the following six settings. * Controls counting by the TM5n register * Selects the operation mode of the TM5n register * Selects the individual mode or cascade connection mode * Sets the status of the timer output flip-flop * Controls the timer output flip-flop or selects the active level in the PWM (free-running timer) mode * Controls timer output The TMC5n register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
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After reset: 00H <7> TMC5n (n = 0, 1) TCE5n 0 1 TCE5n
R/W 6 TMC5n6
Address: TMC50 FFFFF5C6H, TMC51 FFFFF5C7H 5 0 4 TMC514
Note
<3> LVS5n
<2> LVR5n
1 TMC5n1
<0> TOE5n
Control of count operation of 8-bit timer/event counter 5n Counting is disabled after the counter is cleared to 0 (counter disabled) Start count operation
TMC5n6 0 1
Selection of operation mode of 8-bit timer/event counter 5n Mode in which clear & start occurs on match between TM5n register and CR5n register PWM (free-running timer) mode
TMC514 Selection of individual mode or cascade connection mode for 8-bit timer/event counter 51 0 1 Individual mode Cascade connection mode (connected with 8-bit timer/event counter 50)
LVS5n 0 0 1 1
LVR5n 0 1 0 1 Unchanged
Setting of status of timer output F/F
Reset timer output F/F to 0 Set timer output F/F to 1 Setting prohibited
TMC5n1 Other than PWM (free-running timer) mode (TMC5n6 bit = 0) Controls timer F/F 0 1 Disable inversion operation Enable inversion operation
PWM (free-running timer) mode (TMC5n6 bit = 1) Selects active level High active Low active
TOE5n 0 1
Timer output control Disable output (TO5n pin is low level) Enable output
Note Bit 4 of the TMC50 register is fixed to 0. Cautions 1. Because the TO51 and TI51 pins are alternate functions of the same pin, only one can be used at one time. 2. The LVS5n and LVR5n bit settings are valid in modes other than the PWM mode. 3. Do not set <1> to <4> below at the same time. Set as follows. <1> Set the TMC5n1, TMC5n6, and TMC514Note bits: <2> Set the TOE5n bit for timer output enable: <3> Set the LVS5n and LVR5n bits (Caution 2): <4> Set the TCE5n bit Remarks 1. In the PWM mode, the PWM output is set to the inactive level by the TCE5n bit = 0. 2. When the LVS5n and LVR5n bits are read, 0 is read. 3. The values of the TMC5n6, LVS5n, LVR5n, TMC5n1, and TOE5n bits are reflected to the TO5n output regardless of the TCE5n bit value.
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8.4 Operation
8.4.1 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that repeatedly generates interrupts at the interval of the count value preset in the CR5n register. If the count value in the TM5n register matches the value set in the CR5n register, the value of the TM5n register is cleared to 00H and counting is continued, and at the same time, an interrupt request signal (INTTM5n) is generated. Setting method <1> Set each register. * TCL5n register: * CR5n register: Selects the count clock (t). Compare value (N) between the TM5n register and CR5n register (TMC5n register = 0000xx00B, x: don't care). <2> When the TMC5n.TCE5n bit is set to 1, the count operation starts. <3> When the values of the TM5n register and CR5n register match, the INTTM5n signal is generated (TM5n register is cleared to 00H). <4> Then, the INTTM5n signal is repeatedly generated at the same interval. To stop counting, set the TCE5n bit = 0. Interval time = (N + 1) x t: N = 00H to FFH Caution During interval timer operation, do not rewrite the value of the CR5n register. Remark n = 0, 1 Figure 8-2. Timing of Interval Timer Operation (1/2)
* TMC5n register: Stops count operation and selects the mode in which clear & start occurs on a match
Basic operation
t Count clock TM5n count value 00H 01H N 00H Clear N 01H N 00H Clear N N 01H N
Count start CR5n TCE5n INTTM5n N
Interrupt acknowledgment Interrupt acknowledgment Interval time Interval time
Remark
n = 0, 1
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Figure 8-2. Timing of Interval Timer Operation (2/2)
When CR5n register = 00H
t Count clock TM5n count value 00H CR5n TCE5n INTTM5n Interval time 00H 00H 00H 00H
Remark
n = 0, 1
When CR5n register = FFH
t Count clock TM5n count value 00H CR5n TCE5n INTTM5n Interrupt acknowledgment Interval time Interrupt acknowledgment FFH 01H FEH FFH FFH 00H FEH FFH FFH 00H
Remark
n = 0, 1
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8.4.2 Operation as external event counter The external event counter counts the number of clock pulses input to the TI5n pin from an external source by using the TM5n register. Each time the valid edge specified by the TCL5n register is input to the TI5n pin, the TM5n register is incremented. Either the rising edge or the falling edge can be specified as the valid edge. When the count value of the TM5n register matches the value of the CR5n register, the TM5n register is cleared to 00H and an interrupt request signal (INTTM5n) is generated. Setting method <1> Set each register. * TCL5n register: Selects the TI5n pin input edge. Falling edge of TI5n pin TLC5n register = 00H Rising edge of TI5n pin TCL5n register = 01H * CR5n register: Compare value (N) between the TM5n register and CR5n register, disables timer output F/F inversion operation, and disables timer output. (TMC5n register = 0000xx00B, x: don't care) * For the alternate-function pin settings, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. <2> When the TMC5n.TCE5n bit is set to 1, the counter counts the number of pulses input from the TI5n pin. <3> When the values of the TM5n register and CR5n register match, the INTTM5n signal is generated (TM5n register is cleared to 00H). <4> Then, the INTTM5n signal is generated each time the values of the TM5n register and CR5n register match. INTTM5n signal is generated when the valid edge of TI5n pin is input N + 1 times: N = 00H to FFH * TMC5n register: Stops count operation, selects the mode in which clear & start occurs on a match
Caution During external event counter operation, do not rewrite the value of the CR5n register. Remark n = 0, 1
Figure 8-3. Timing of External Event Counter Operation (with Rising Edge Specified)
TI5n TM5n count value 00H 01H 02H 03H 04H 05H N-1 N 00H 01H 02H 03H
Count start CR5n N
TCE5n INTTM5n
Remark
n = 0, 1
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8.4.3 Square-wave output operation A square wave with any frequency can be output at an interval determined by the value preset in the CR5n register. By setting the TMC5n.TOE5n bit to 1, the output status of the TO5n pin is inverted at an interval determined by the count value preset in the CR5n register. In this way, a square wave of any frequency can be output (duty = 50%) (n = 0, 1). Setting method <1> Set each register. * TCL5n register: * CR5n register: Selects the count clock (t). Compare value (N) between the TM5n register and CR5n register, sets initial value of timer output, enables timer output F/F inversion operation, and enables timer output. (TMC5n register = 00001011B or 00000111B) * For the alternate-function pin settings, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. <2> When the TMC5n.TCE5n bit is set to 1, counting starts. <3> When the values of the TM5n register and CR5n register match, the timer output F/F is inverted. Moreover, the INTTM5n signal is generated and the TM5n register is cleared to 00H. <4> Then, the timer output F/F is inverted during the same interval and a square wave is output from the TO5n pin.
* TMC5n register: Stops count operation, selects the mode in which clear & start occurs on a match
Frequency = 1/2t(N + 1): N = 00H to FFH
Caution Do not rewrite the value of the CR5n register during square-wave output.
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Figure 8-4. Timing of Square-Wave Output Operation
t Count clock TM5n count value 00H 01H N 00H Clear N 01H N 00H Clear N N 01H N
Count start CR5n TCE5n INTTM5n N
Interrupt acknowledgment TO5nNote Interval time
Interrupt acknowledgment
Interval time
Note The initial value of the TO5n pin output can be set using the TMC5n.LVS5n and TMC5n.LVR5n bits. Remark n = 0, 1
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8.4.4 8-bit PWM output operation By setting the TMC5n.TMC5n6 bit to 1, 8-bit timer/event counter 5n performs PWM output. Pulses with a duty factor determined by the value set in the CR5n register are output from the TO5n pin. Set the width of the active level of the PWM pulse in the CR5n register. The active level can be selected using the TMC5n.TMC5n1 bit. The count clock can be selected using the TCL5n register. PWM output can be enabled/disabled by the TMC5n.TOE5n bit. Caution The CR5n register rewrite interval must be three or more operation clocks (set by the TCL5n register). Use method <1> Set each register. * TCL5n register: * CR5n register: Selects the count clock (t). Compare value (N) unchanged, sets active level, and enables timer output. (TMC5n register = 01000001B or 01000011B) * For the alternate-function pin settings, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. <2> When the TMC5n.TCE5n bit is set to 1, counting starts. PWM output operation <1> When counting starts, PWM output (output from the TO5n pin) outputs the inactive level until an overflow occurs. <2> When an overflow occurs, the active level set by setting method <1> is output. The active level is output until the value of the CR5n register and the count value of the TM5n register match. An interrupt request signal (INTTM5n) is generated. <3> When the value of the CR5n register and the count value of the TM5n register match, the inactive level is output and continues to be output until an overflow occurs again. <4> Then, steps <2> and <3> are repeated until counting is stopped. <5> When counting is stopped by clearing TCE5n bit to 0, PWM output becomes inactive. Cycle = 256t, active level width = Nt, duty = N/256: N = 00H to FFH
* TMC5n register: Stops count operation, selects PWM mode, and leave timer output F/F
Remarks 1. n = 0, 1 2. For the detailed timing, refer to Figure 8-5 Timing of PWM Output Operation and Figure 8-6 Timing of Operation Based on CR5n Register Transitions.
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(a) Basic operation of PWM output Figure 8-5. Timing of PWM Output Operation
Basic operation (active level = H)
t Count clock TM5n count value CR5n TCE5n INTTM5n TO5n Active level Inactive level Active level
00H 01H N FFH 00H 01H 02H N N+1 FFH 00H 01H 02H M 00H
When CR5n register = 00H
t Count clock TM5n count value CR5n TCE5n INTTM5n TO5n Inactive level Inactive level
00H 01H 00H FFH 00H 01H 02H N N + 1N + 2 FFH 00H 01H 02H M 00H
When CR5n register = FFH
t Count clock TM5n count value CR5n TCE5n INTTM5n TO5n Inactive level Active level Inactive level Active level Inactive level
00H 01H FFH FFH 00H 01H 02H N N + 1N + 2 FFH 00H 01H 02H M 00H
Remark
n = 0, 1
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(b) Operation based on CR5n register transitions Figure 8-6. Timing of Operation Based on CR5n Register Transitions
When the value of the CR5n register changes from N to M before the rising edge of the FFH clock The value of the CR5n register is transferred at the overflow that occurs immediately after.
t Count clock TM5n count value CR5n TCE5n INTTM5n TO5n <2> <1> CR5n transition (N M) H N N+1 N+2 N FFH 00H 01H 02H M M M+1 M+2 FFH 00H 01H 02H M M+1 M+2
When the value of the CR5n register changes from N to M after the rising edge of the FFH clock The value of the CR5n register is transferred at the second overflow.
t Count clock TM5n count value CR5n TCE5n INTTM5n TO5n <1> CR5n transition (N M) <2> H N N+1 N+2 N FFH 00H 01H 02H 03H N N N+1 N+2 FFH 00H 01H 02H M M M+1 M+2
Caution In the case of reload from the CR5n register between <1> and <2>, the value that is actually used differs (Read value: M; Actual value of CR5n register: N). Remark n = 0, 1
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8.4.5 Operation as interval timer (16 bits) The 16-bit resolution timer/event counter mode is selected by setting the TMC51.TMC514 bit to 1. 8-bit timer/event counter 5n operates as an interval timer by repeatedly generating interrupts using the count value preset in 16-bit timer compare register 5 (CR5) as the interval. Setting method <1> Set each register. * TCL50 register: * CR50 register: * CR51 register: * TMC50, TMC51 register: Selects the count clock (t) (The TCL51 register does not need to be set in cascade connection) Compare value (N) ... Lower 8 bits (settable from 00H to FFH) Compare value (N) ... Higher 8 bits (settable from 00H to FFH) Selects the mode in which clear & start occurs on a match between TM5 register and CR5 register (x: don't care) TMC50 register = 0000xx00B TMC51 register = 0001xx00B <2> Set the TMC51.TCE51 bit to 1. Then set the TMC50.TCE50 bit to 1 to start the count operation. <3> When the values of the TM5 register and CR5 register connected in cascade match, the INTTM50 signal is generated (the TM5 register is cleared to 0000H). <4> The INTTM50 signal is then generated repeatedly at the same interval. Interval time = (N + 1) x t: N = 0000H to FFFFH
Cautions 1. To write using 8-bit access during cascade connection, set the TCE51 bit to 1 at operation start and then set the TCE50 bit to 1. When operation is stopped, clear the TCE50 bit to 0 and then clear the TCE51 bit to 0. 2. During cascade connection, TI50 input, TO50 output, and the INTTM50 signal are used. Do not use TI51 input, TO51 output, and the INTTM51 signal; mask them instead (for details, refer to CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION). Clear the LVS51, LVR51, TMC511, and TOE51 bits to 0. 3. Do not change the value of the CR5 register during timer operation.
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Figure 8-7 shows a timing example of the cascade connection mode with 16-bit resolution. Figure 8-7. Cascade Connection Mode with 16-Bit Resolution
t Count clock TM50 count value 00H TM51 count value 00H CR50 CR51 TCE50 TCE51 INTTM50 Interval time Operation enabled, count start Interrupt occurrence, counter cleared Operation stopped N M 01H N N+1 FFH 00H 01H FFH 00H 02H FFH 00H 01H M-1 M N 00H 01H 00H A 00H B 00H
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8.4.6 Operation as external event counter (16 bits) The 16-bit resolution timer/event counter mode is selected by setting the TMC51.TMC514 bit to 1. The external event counter counts the number of clock pulses input to the TI50 pin from an external source using 16-bit timer counter 5 (TM5). Setting method <1> Set each register. * TCL50 register: Selects the TI50 pin input edge. (The TCL51 register does not have to be set during cascade connection.) Falling edge of TI50 pin TCL50 register = 00H Rising edge of TI50 pin TCL50 register = 01H * CR50 register: * CR51 register: Compare value (N) ... Lower 8 bits (settable from 00H to FFH) Compare value (N) ... Higher 8 bits (settable from 00H to FFH) between the TM5 register and CR5 register, disables timer output F/F inversion, and disables timer output. (x: don't care) TMC50 register = 0000xx00B TMC51 register = 0001xx00B * For the alternate-function pin settings, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. <2> Set the TMC51.TCE51 bit to 1. Then set the TMC50.TCE50 bit to 1 and count the number of pulses input from the TI50 pin. <3> When the values of the TM5 register and CR5 register connected in cascade match, the INTTM50 signal is generated (the TM5 register is cleared to 0000H). <4> The INTTM50 signal is then generated each time the values of the TM5 register and CR5 register match. INTTM50 signal is generated when the valid edge of TI50 pin is input N + 1 times: N = 0000H to FFFFH
* TMC50, TMC51 registers: Stops count operation, selects the clear & stop mode entered on a match
Cautions 1. During external event counter operation, do not rewrite the value of the CR5n register. 2. To write using 8-bit access during cascade connection, set the TCE51 bit to 1 and then set the TCE50 bit to 1. When operation is stopped, clear the TCE50 bit to 0 and then clear the TCE51 bit to 0 (n = 0, 1). 3. During cascade connection, TI50 input and the INTTM50 signal are used. Do not use TI51 input, TO51 output, and the INTTM51 signal; mask them instead (for details, refer to CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION). Clear the LVS51, LVR51, TMC511, and TOE51 bits to 0. 4. Do not change the value of the CR5 register during external event counter operation.
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8.4.7 Square-wave output operation (16-bit resolution) The 16-bit resolution timer/event counter mode is selected by setting the TMC51.TMC514 bit to 1. 8-bit timer/event counter 5n outputs a square wave of any frequency using the interval preset in 16-bit timer compare register 5 (CR5). Setting method <1> Set each register. * TCL50 register: * CR50 register: * CR51 register: Selects the count clock (t) (The TCL51 register does not have to be set in cascade connection) Compare value (N) ... Lower 8 bits (settable from 00H to FFH) Compare value (N) ... Higher 8 bits (settable from 00H to FFH) match between the TM5 register and CR5 register.
LVS50 1 0 LVR50 0 1 Timer Output F/F Status Settings High-level output Low-level output
* TMC50, TCM51 registers: Stops count operation, selects the mode in which clear & start occurs on a
Enables timer output F/F inversion, and enables timer output. TMC50 register = 00001011B or 00000111B TMC51 register = 00010000B * For the alternate-function pin settings, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. <2> Set the TMC51.TCE51 bit to 1. Then set the TMC50.TCE50 bit to 1 to start the count operation. <3> When the values of the TM5 register and the CR5 register connected in cascade match, the TO50 timer output F/F is inverted. Moreover, the INTTM50 signal is generated and the TM5 register is cleared to 0000H. <4> Then, the timer output F/F is inverted during the same interval and a square wave is output from the TO50 pin. Frequency = 1/2t(N + 1): N = 0000H to FFFFH
Caution Do not write a different value to the CR5 register during operation.
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8.4.8 Cautions (1) Error on starting timer An error of up to 1 clock occurs before the match signal is generated after the timer has been started. This is because the TM5n register is started asynchronously to the count pulse. Figure 8-8. Count Start Timing of TM5n Register
Count pulse TM5n count value 00H Timer start 01H 02H 03H 04H
Remark
n = 0, 1
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In the V850ES/KE2, two channels of 8-bit timer H are provided.
9.1 Functions
8-bit timer Hn has the following functions (n = 0, 1). * Interval timer * Square ware output * PWM output * Carrier generator
9.2 Configuration
8-bit timer Hn includes the following hardware. Table 9-1. Configuration of 8-Bit Timer Hn
Item Timer registers Register Configuration 8-bit timer counter Hn: 1 each 8-bit timer H compare register n0 (CMPn0): 1 each 8-bit timer H compare register n1 (CMPn1): 1 each Timer outputs Control registers
Note
TOHn, output controller 8-bit timer H mode register n (TMHMDn) 8-bit timer H carrier control register n (TMCYCn)
Note To use the TOHn pin function, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. Remark n = 0, 1
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The block diagram is shown below. Figure 9-1. Block Diagram of 8-Bit Timer Hn
Internal bus
8-bit timer H mode register n (TMHMDn)
TMHEn CKSHn2 CKSHn1 CKSHn0 TMMDn1TMMDn0 TOLEVn TOENn
8-bit timer H compare register n1 (CMPn1)
8-bit timer H compare register n0 (CMPn0)
8-bit timer H carrier control register n (TMCYCn) RMCn NRZBn NRZn Reload/ interrupt control
INTTM5n
3
2
Decoder
Selector
TOHn
Match
fXX fXX/2 fXX/22 fXX/24 fXX/26 Note
Interrupt generator
F/F R
Output controller
Level inversion
Selector
Carrier generator mode signal PWM mode signal
8-bit timer counter Hn Clear
Timer H enable signal
1 0
INTTMHn
10 Note fXX/2 when n = 0, fXT when n = 1
Remark
n = 0, 1
(1) 8-bit timer H compare register n0 (CMPn0) This register can be read or written in 8-bit units. This register is used in all of the timer operation modes. This register constantly compares the value set to the CMPn0 register with the count value of 8-bit timer counter Hn and, when the two values match, generates an interrupt request signal (INTTMHn) and inverts the output level of the TOHn pin. Rewrite the value of the CMPn0 register while the timer is stopped (TMHMDn.TMHEn bit = 0). Reset sets this register to 00H.
After reset: 00H 7 CMPn0 (n = 0, 1)
R/W 6
Address: CMP00 FFFFF582H, CMP10 FFFFF592H 5 4 3 2 1 0
Caution Rewriting the CMPn0 register during timer count operation is prohibited.
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(2) 8-bit timer H compare register n1 (CMPn1) This register can be read or written in 8-bit units. This register is used in the PWM output mode and carrier generator mode. In the PWM output mode, this register constantly compares the value set to the CMPn1 register with the count value of 8-bit timer counter Hn and, when the two values match, inverts the output level of the TOHn pin. No interrupt request signal is generated. In the carrier generator mode, the CMPn1 register always compares the value set to the CMPn1 register with the count value of 8-bit timer counter Hn and, when the two values match, generates an interrupt request signal (INTTMHn). At the same time, the count value is cleared. The CMPn1 register can be rewritten during timer count operation. If the value of the CMPn1 register is rewritten while the timer is operating, the new value is latched and transferred to the CMPn1 register when the count value of the timer matches the old value of the CMPn1 register, and then the value of the CMPn1 register is changed to the new value. If matching of the count value and the CMPn1 register value and writing a value to the CMPn1 register conflict, the value of the CMPn1 register is not changed. Reset sets this register to 00H.
After reset: 00H 7 CMPn1 (n = 0, 1)
R/W 6
Address: CMP01 FFFFF583H, CMP11 FFFFF593H 5 4 3 2 1 0
The CMPn1 register can be rewritten during timer count operation. In the carrier generator mode, after the CMPn1 register is set, if the count value of 8-bit timer counter Hn and the set value of the CMPn1 register match, an interrupt request signal (INTTMHn) is generated. At the same time, the value of 8-bit timer counter Hn is cleared to 00H. If the set value of the CMPn1 register is rewritten during timer operation, the reload timing is when the count value of 8-bit timer counter Hn and the set value of the CMPn1 register match. If the transfer timing and write to the CMPn1 register from the CPU conflict, transfer is not performed. Caution In the PWM output mode and carrier generator mode, be sure to set the CMPn1 register when starting the timer count operation (TMHMDn.TMHEn bit = 1) after the timer count operation was stopped (TMHEn bit = 0) (be sure to set again even if setting the same value to the CMPn1 register).
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9.3 Registers
The registers that control 8-bit timer Hn are as follows. * 8-bit timer H mode register n (TMHMDn) * 8-bit timer H carrier control register n (TMCYCn) Remarks 1. To use the TOHn pin function, refer to Table 4-12 Alternate Functions. 2. n = 0, 1 (1) 8-bit timer H mode register n (TMHMDn) The TMHMDn register controls the mode of 8-bit timer Hn. TMHMDn register can be read or written in 8-bit or 1-bit units. Reset sets TMHMDn to 00H. Remark n = 0, 1 Settings When Port Pins Are Used for
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(a) 8-bit timer H mode register 0 (TMHMD0)
After reset: 00H <7> TMHMD0 TMHE0 R/W 6 Address: FFFFF580H 5 4 3 2 <1> <0> TOEN0
CKSH02 CKSH01 CKSH00 TMMD01 TMMD00 TOLEV0
TMHE0 0 1
8-bit timer H0 operation enable Stop timer count operation (8-bit timer counter H0 = 00H) Enable timer count operation (Counting starts when clock is input)
CKSH02 CKSH01 CKSH00 Count clock 0 0 0 0 1 1 0 0 1 1 0 0 Other than above 0 1 0 1 0 1 fXX fXX/2 fXX/4 fXX/16 fXX/64 fXX/1024
Note
Selection of count clock fXX = 20 MHz fXX = 16.0 MHz fXX = 10.0 MHz
Setting prohibited Setting prohibited 100 ns
100 ns 200 ns 800 ns 1.6 s 51.2 s
125 ns 250 ns 1 s 4 s 64 s
200 ns 400 ns 1.6 s 6.4 s 102.4 s
Setting prohibited
TMMD01 TMMD00 0 0 1 1 0 1 0 1
8-bit timer H0 operation mode Interval timer mode Carrier generator mode PWM output mode Setting prohibited
TOLEV0 0 1 Low level High level
Timer output level control (default)
TOEN0 0 1 Disable output Enable output
Timer output control
Note Set so as to satisfy the following conditions. VDD = 4.0 to 5.5 V: Count clock 10 MHz VDD = 2.7 to 4.0 V: Count clock 5 MHz Cautions 1. When the TMHE0 bit = 1, setting bits other than those of the TMHMD0 register is prohibited. 2. In the PWM output mode and carrier generator mode, be sure to set the CMP01 register when starting the timer count operation (TMHE0 bit = 1) after the timer count operation was stopped (TMHE0 bit = 0) (be sure to set again even if setting the same value to the CMP01 register). 3. When using the carrier generator mode, set 8-bit timer H0 count clock frequency to six times 8-bit timer/event counter 50 count clock frequency or higher.
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(b) 8-bit timer H mode register 1 (TMHMD1)
After reset: 00H <7> TMHMD1 TMHE1 R/W 6 Address: FFFFF590H 5 4 3 2 <1> <0> TOEN1
CKSH12 CKSH11 CKSH10 TMMD11 TMMD10 TOLEV1
TMHE1 0 1
8-bit timer H1 operation enable Stop timer count operation (8-bit timer counter H1 = 00H) Enable timer count operation (Counting starts when clock is input)
CKSH12 CKSH11 CKSH10 Count clock 0 0 0 0 1 1 0 0 1 1 0 0 Other than above 0 1 0 1 0 1 fXX fXX/2 fXX/4 fXX/16 fXX/64
Note
Selection of count clock fXX = 20.0 MHz fXX = 16.0 MHz fXX = 10.0 MHz
Setting prohibited Setting prohibited 100 ns
100 ns 200 ns 800 ns 1.6 s
125 ns 250 ns 1 s 4 s
200 ns 400 ns 1.6 s 6.4 s
fXT (subclock) Setting prohibited
TMMD11 TMMD10 0 0 1 1 0 1 0 1
8-bit timer H1 operation mode Interval timer mode Carrier generator mode PWM output mode Setting prohibited
TOLEV1 0 1 Low level High level
Timer output level control (default)
TOEN1 0 1 Disable output Enable output
Timer output control
Note Set so as to satisfy the following conditions. VDD = 4.0 to 5.5 V: Count clock 10 MHz VDD = 2.7 to 4.0 V: Count clock 5 MHz Cautions 1. When the TMHE1 bit = 1, setting bits other than those of the TMHMD1 register is prohibited. 2. In the PWM output mode and carrier generator mode, be sure to set the CMP11 register when starting the timer count operation (TMHE1 bit = 1) after the timer count operation was stopped (TMHE1 bit = 0) (be sure to set again even if setting the same value to the CMP11 register). 3. When using the carrier generator mode, set 8-bit timer H1 count clock frequency to six times 8-bit timer/event counter 51 count clock frequency or higher.
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(2) 8-bit timer H carrier control register n (TMCYCn) This register controls the 8-bit timer Hn remote control output and carrier pulse output status. TMCYCn register can be read or written in 8-bit or 1-bit units. The NRZn bit is a read-only bit. Reset sets TMCYCn to 00H. Remark n = 0, 1
After reset: 00H 7 TMCYCn (n = 0, 1) RMCn 0 0 1 1 0
R/W 6 0
Address: TMCYC0 FFFFF581H, TMCYC1 FFFFF591H 5 0 4 0 3 0 2 RMCn 1 NRZBn <0> NRZn
NRZBn 0 1 0 1 Low-level output
Remote control output
High-level output Low-level output Carrier pulse output
NRZn 0 1
Carrier pulse output status flag Carrier output disabled status (low-level status) Carrier output enable status
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9.4 Operation
9.4.1 Operation as interval timer/square wave output When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, an interrupt request signal (INTTMHn) is generated and 8-bit timer counter Hn is cleared to 00H. The CMPn1 register cannot be used in the interval timer mode. Even if the CMPn1 register is set, this has no effect on the timer output because matches between 8-bit timer counter Hn and the CMPn1 register are not detected. A square wave of the desired frequency (duty = 50%) is output from the TOHn pin, by setting the TMHMDn.TOENn bit to 1. Remarks 1. For the alternate-function pin (TOHn) settings, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. 2. For INTTMHn interrupt enable, refer to CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION. Setting <1> Set each register. Figure 9-2. Register Settings in Interval Timer Mode
(i)
8-bit timer H mode register n (TMHMDn) settings
TMHEn TMHMDn 0 CKSHn2 CKSHn1 CKSHn0 TMMDn1 TMMDn0 TOLEVn 0/1 0/1 0/1 0 0 0/1 TOENn 0/1
Sets timer output Sets timer output default level Sets interval timer mode Selects count clock (fCNT) Stops count operation
(ii) CMPn0 register settings The interval time is as follows if N is set as a comparison value. * Interval time = (N + 1)/fCNT <2> When the TMHEn bit is set to 1, counting starts. <3> When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, the INTTMHn signal is generated and 8-bit timer counter Hn is cleared to 00H. <4> Then, the INTTMHn signal is generated in the same interval. To stop the count operation, clear the TMHEn bit to 0.
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Figure 9-3. Timing of Interval Timer/Square Wave Output Operation (1/2)
Basic operation (operation when 01H CMPn0 FEH)
Count clock Count start 8-bit timer counter Hn count value 00H 01H N 00H Clear CMPn0 N 01H N 00H Clear 01H 00H
TMHEn
INTTMHn Interval time TOHn <1> <2> Level inversion, match interrupt occurrence, 8-bit timer counter clear <3> <2> Level inversion, match interrupt occurrence, 8-bit timer counter clear
<1> When the TMHEn bit is set to 1, the count operation is enabled. The count clock starts counting no more than one clock after operation has been enabled. <2> When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, the value of 8-bit timer counter Hn is cleared, the TOHn output level is inverted, and the INTTMHn signal is output at the rising edge of the count clock. <3> The INTTMHn signal and TOHn output are set to the default level when the TMHEn bit is cleared to 0 during 8-bit timer Hn operation. If the level is already at the default level before the TMHMDn.TMHEn bit is cleared to 0, that level is maintained. Remarks 1. n = 0, 1 2. 01H N FEH
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Figure 9-3. Timing of Interval Timer/Square Wave Output Operation (2/2)
Operation when CMPn0 = FFH
Count clock Count start 8-bit timer counter Hn count value 00H 01H FEH FFH 00H Clear CMPn0 FFH FEH FFH 00H Clear
TMHEn
INTTMHn
TOHn Interval time
Operation when CMPn0 = 00H
Count clock Count start 8-bit timer counter Hn count value 00H
CMPn0
00H
TMHEn
INTTMHn
TOHn Interval time
Remark
n = 0, 1
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9.4.2 PWM output mode operation In the PWM output mode, a pulse of any duty and cycle can be output. The CMPn0 register controls the timer output (TOHn) cycle. Rewriting the CMPn0 register during timer operation is prohibited. The CMPn1 register controls the timer output (TOHn) duty. The CMPn1 register can be rewritten during timer operation. The operation in the PWM output mode is as follows. After timer counting starts, when the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, the TOHn output level is inverted and 8-bit timer counter Hn is cleared to 00H. When the count value of 8-bit timer counter Hn and the set value of the CMPn1 register match, the TOHn output level is inverted. Remarks 1. For the alternate-function pin (TOHn) settings, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. 2. For INTTMHn interrupt enable, refer to CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION. Setting <1> Set each register. Figure 9-4. Register Settings in PWM Output Mode
(i)
8-bit timer H mode register n (TMHMDn) settings
TMHEn CKSHn2 CKSHn1 CKSHn0 TMMDn1 TMMDn0 TOLEVn 0/1 0/1 0/1 1 0 0/1 TOENn 1
TMHMDn
0
Enables timer output Sets timer output default level Selects PWM output mode Selects count clock (fCNT) Stops count operation
(ii) CMPn0 register setting * Compare value (N): Sets cycle (ii) CMPn1 register setting * Compare value (M): Sets duty Remarks 1. n = 0, 1 2. 00H CMPn1 (M) < CMPn0 (N) FFH
<2> When the TMHEn bit is set to 1, counting starts.
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<3> After the count operation is enabled, the first compare register to be compared is the CMPn0 register. When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, 8-bit timer counter Hn is cleared, an interrupt request signal (INTTMHn) is generated, and the TOHn output level is inverted. At the same time, the register that is compared with 8-bit timer counter Hn changes from the CMPn0 register to the CMPn1 register. <4> When the count value of 8-bit timer counter Hn and the set value of the CMPn1 register match, the TOHn output level is inverted, and at the same time the register that is compared with 8-bit timer counter Hn changes from the CMPn1 register to the CMPn0 register. At this time, 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated. <5> A pulse of any duty can be obtained through the repetition of steps <3> and <4> above. <6> To stop the count operation, clear the TMHEn bit to 0. Designating the set value of the CMPn0 register as (N), the set value of the CMPn1 register as (M), and the count clock frequency as fCNT, the PWM pulse output cycle and duty are as follows. PWM pulse output cycle = (N + 1)/fCNT Duty = inactive width: Active width = (M + 1) : (N + 1)
Cautions 1. The set value of the CMPn1 register can be changed while the timer counter is operating. However, this takes a duration of at least three operating clocks (signal selected by the CKSHn2 to CKSHn0 bits of the TMHMDn register) from when the value of the CMPn1 register is changed until the value is transferred to the register. 2. Be sure to set the CMPn1 register when starting the timer count operation (TMHEn bit = 1) after the timer count operation was stopped (TMHEn bit = 0) (be sure to set again even if setting the same value to the CMPn1 register). 3. Make sure that the CMPn1 register set value (M) and CMPn0 register set value (N) are within the following range. 00H CMPn1 (M) < CMPn0 (N) FFH
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Figure 9-5. Operation Timing in PWM Output Mode (1/4)
Basic operation
Count clock
8-bit timer counter Hn count value
00H 01H
A5H 00H 01H 02H
A5H 00H 01H 02H
A5H 00H
CMPn0
A5H
CMPn1
01H
TMHEn
INTTMHn
TOHn (TOLEVn = 0) <1> TOHn (TOLEVn = 1) <2> <3> <4>
<1> When the TMHEn bit is set to 1, counting starts. At this time TOHn output remains the default level. <2> When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, the TOHn output level is inverted, 8-bit timer counter Hn is cleared, and the INTTMHn signal is output. <3> When the count value of 8-bit timer counter Hn and the set value of the CMPn1 register match, the TOHn output level is inverted. At this time, the value of 8-bit timer counter Hn is not cleared and the INTTMHn signal is not output. <4> When the TMHEn bit is cleared to 0 during 8-bit timer Hn operation, the INTTMHn signal and TOHn output are set to the default level. Remark n = 0, 1
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Figure 9-5. Operation Timing in PWM Output Mode (2/4)
Operation when CMPn0 = FFH, CMPn1 = 00H
Count clock
8-bit timer counter Hn count value
00H 01H
FFH 00H 01H 02H
FFH 00H 01H 02H
FFH 00H
CMPn0
FFH
CMPn1
00H
TMHEn
INTTMHn
TOHn (TOLEVn = 0)
Operation when CMPn0 = FFH, CMPn1 = FEH
Count clock
8-bit timer counter Hn count value
00H 01H
FEH FFH 00H 01H
FEH FFH 00H 01H
FEH FFH 00H
CMPn0
FFH
CMPn1
FEH
TMHEn
INTTMHn
TOHn (TOLEVn = 0)
Remark
n = 0, 1
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Figure 9-5. Operation Timing in PWM Output Mode (3/4)
Operation when CMPn0 = 01H, CMPn1 = 00H
Count clock
8-bit timer counter Hn count value
00H
01H 00H 01H 00H
00H 01H 00H 01H
CMPn0
01H
CMPn1
00H
TMHEn
INTTMHn
TOHn (TOLEVn = 0)
Remark
n = 0, 1
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Figure 9-5. Operation Timing in PWM Output Mode (4/4)
Operation by changing CMPn1 (CMPn1 = 02H 03H, CMPn0 = A5H)
Count clock
8-bit timer counter Hn
00H 01H 02H
80H
A5H 00H 01H 02H 03H
A5H 00H 01H 02H 03H
A5H 00H
CMPn0
A5H
CMPn1
02H <2>
02H (03H) <2>'
03H
TMHEn
INTTMHn
TOHn (TOLEVn = 0) <1> <3> <4> <5> <6>
<1> When the TMHEn bit is set to 1, counting starts. At this time, the TOHn output remains the default level. <2> The set value of the CMPn1 register can be changed during count operation. asynchronous to the count clock. <3> When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, 8-bit timer counter Hn is cleared, the TOHn output level is inverted, and the INTTMHn signal is generated. <4> Even if the value of the CMPn1 register is changed, that value is latched and not transferred to the register. When the count value of 8-bit timer counter Hn and the set value of the CMPn1 register prior to the change match, the changed value is transferred to the CMPn1 register and the value of the CMPn1 register is changed (<2>'). However, three or more count clocks are required from the time the value of the CMPn1 register is changed until it is transferred to the register. Even if a match signal is generated within three count clocks, the changed value cannot be transferred to the register. <5> When the count value of 8-bit timer counter Hn matches the changed set value of the CMPn1 register, the TOHn output level is inverted. 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated. <6> When the TMHEn bit is cleared to 0 during 8-bit timer Hn operation, the INTTMHn signal and TOHn output are set to the default level. This operation is
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9.4.3 Carrier generator mode operation The carrier clock generated by 8-bit timer Hn is output using the cycle set with 8-bit timer/event counter 5n. In the carrier generator mode, 8-bit timer/event counter 5n is used to control the extent to which the carrier pulse of 8-bit timer Hn is output, and the carrier pulse is output from the TOHn output. Remarks 1. For the alternate-function pin (TOHn) settings, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. 2. For INTTMHn interrupt enable, refer to CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION. (1) Carrier generation In the carrier generator mode, the CMPn0 register generates a waveform with the low-level width of the carrier pulse and the CMPn1 register generates a waveform with the high-level width of the carrier pulse. During 8-bit timer Hn operation, the CMPn1 register can be rewritten, but rewriting of the CMPn0 register is prohibited. (2) Carrier output control Carrier output control is performed with the interrupt request signal (INTTM5n) of 8-bit timer/event counter 5n and the TMCYCn.NRZBn and TMCYCn.RMCn bits. The output relationships are as follows.
RMCn Bit 0 0 1 1 NRZBn Bit 0 1 0 1 Output Low level output High level output Low level output Carrier pulse output
Remark
n = 0, 1
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To control carrier pulse output during count operation, the TMCYCn.NRZn and TMCYCn.NRZBn bits have a master and slave bit configuration. The NRZn bit is read-only while the NRZBn bit can be read and written. The INTTM5n signal is synchronized with the 8-bit timer Hn clock and output as the INTTM5Hn signal. The INTTM5Hn signal becomes the data transfer signal of the NRZn bit and the value of the NRZBn bit is transferred to the NRZn bit. The transfer timing from the NRZBn bit to the NRZn bit is as follows. Figure 9-6. Transfer Timing
TMHEn
8-bit timer Hn count clock
INTTM5n
INTTM5Hn <1> NRZn 0 <2> NRZBn 1 <3> RMCn 0 1 1 0
<1> The INTTM5n signal is synchronized with the count clock of 8-bit timer Hn and is output as the INTTM5Hn signal. <2> The value of the NRZBn bit is transferred to the NRZn bit at the second clock from the rising edge of the INTTM5Hn signal. <3> Write the next value to the NRZBn bit in the interrupt servicing programming that has been started by the INTTM5Hn interrupt or after timing has been checked by polling the interrupt request flag. Write data to count the next time to the CR5n register. Cautions 1. Do not rewrite the NRZBn bit again until at least the second clock after it has been rewritten, or else transfer from the NRZBn bit to the NRZn bit is not guaranteed. 2. When using 8-bit timer/event counter 5n in the carrier generator mode, an interrupt occurs at the timing of <1>. An interrupt occurs at a different timing when it is used in other than the carrier generator mode. Remark n = 0, 1
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Setting <1> Set each register. Figure 9-7. Register Settings in Carrier Generator Mode
* 8-bit timer H mode register n (TMHMDn)
TMHEn TMHMDn 0 CKSHn2 CKSHn1 CKSHn0 TMMDn1 TMMDn0 TOLEVn 0/1 0/1 0/1 0 1 0/1 TOENn 1
Enables timer output Sets timer output default level Selects carrier generator mode Selects count clock (fCNT) Stops count operation
* CMPn0 register: * CMPn1 register: * TMCYCn register:
Compare value Compare value RMCn = 1 ... Remote control output enable bit NRZBn = 0/1 ... Carrier output enable bit
* TCL5n, TMC5n registers: Refer to 9.3 Registers. Remark n = 0, 1
<2> When the TMHEn bit is set to 1, 8-bit timer Hn count operation starts. <3> When the TMC5n.TCE5n bit is set to 1, 8-bit timer/event counter 5n count operation starts. <4> After the count operation is enabled, the first compare register to be compared is the CMPn0 register. When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, the INTTMHn signal is generated, 8-bit timer counter Hn is cleared, and at the same time, the register that is compared with 8-bit timer counter Hn changes from the CMPn0 register to the CMPn1 register. <5> When the count value of 8-bit timer counter Hn and the set value of the CMPn1 register match, the INTTMHn signal is generated, 8-bit timer counter Hn is cleared, and at the same time, the register that is compared with 8-bit timer counter Hn changes from the CMPn1 register to the CMPn0 register. <6> The carrier clock is obtained through the repetition of steps <4> and <5> above. <7> The INTTM5n signal is synchronized with 8-bit timer Hn and output as the INTTM5Hn signal. This signal becomes the data transfer signal of the NRZBn bit and the value of the NRZBn bit is transferred to the NRZn bit. <8> Write the next value to the NRZBn bit in the interrupt servicing programming that has been started by the INTTM5Hn interrupt or after timing has been checked by polling the interrupt request flag. Write data to count the next time to the CR5n register. <9> When the NRZn bit becomes high level, the carrier clock is output from the TOHn pin. <10> Any carrier clock can be obtained through the repetition of the above steps. To stop the count operation, clear the TMHEn bit to 0.
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Designating the set value of the CMPn0 register as (N), the set value of the CMPn1 register as (M), and the count clock frequency as fCNT, the carrier clock output cycle and duty are as follows. Carrier clock output cycle = (N + M + 2)/fCNT Duty = High level width: Carrier clock output width = (M + 1) : (N + M + 2)
Cautions 1. Be sure to set the CMPn1 register when starting the timer count operation (TMHEn bit = 1) after the timer count operation was stopped (TMHEn bit = 0) (be sure to set again even if setting the same value to the CMPn1 register). 2. Set the values of the CMPn0 and CMPn1 registers in the range of 01H to FFH. 3. In the carrier generator mode, three operating clocks (signal selected by the TMHMDn.CKSHn0 to TMHMDn.CKSHn2 bits) are required for actual transfer of the new value to the register after the CMPn1 register has been rewritten. 4. Be sure to perform the TMCYCn.RMCn bit setting before the start of the count operation. 5. When using the carrier generator mode, set the 8-bit timer Hn count clock frequency to six times the 8-bit timer/event counter 5n count clock frequency or higher.
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Figure 9-8. Carrier Generator Mode (1/3) Operation when the CMPn0 register = N, the CMPn1 register = N is set
8-bit timer Hn count clock 8-bit timer counter Hn count value CMPn0 CMPn1 TMHEn INTTMHn <1> <2> Carrier clock 8-bit timer 5n count clock TM5n count value CR5n TCE5n <5> INTTM5n INTTM5Hn NRZBn NRZn Carrier clock TOHn <7> 0 0 1 1 0 <6> 0 1 0 1 0
00H 01H K 00H 01H L 00H 01H M 00H 01H N 00H 01H 00H N 00H N 00H N 00H N N 00H N 00H N
N
<3>
<4>
K
L
M
N
<6>
<1> When the TMHEn bit = 0 and the TCE5n bit = 0, the operation of 8-bit timer Hn is stopped. <2> When the TMHEn bit is set to 1, 8-bit timer Hn starts counting. The carrier clock remains the default level. <3> When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, the first INTTMHn signal is generated, the carrier clock signal is inverted, and the register that is compared with 8-bit timer counter Hn changes from the CMPn0 register to the CMPn1 register. 8-bit timer counter Hn is cleared to 00H. <4> When the count value of 8-bit timer counter Hn and the set value of the CMPn1 register match, the INTTMHn signal is generated, the carrier clock signal is inverted, and the register that is compared with 8-bit timer counter Hn changes from the CMPn1 register to the CMPn0 register. 8-bit timer counter Hn is cleared to 00H. A carrier clock with a duty of 50% is generated through the repetition of steps <3> and <4>. <5> The INTTM5n signal is synchronized with 8-bit timer Hn and output as the INTTM5Hn signal. <6> The INTTM5Hn signal becomes the data transfer signal of the NRZBn bit, and the value of the NRZBn bit is transferred to the NRZn bit. <7> The TOHn output is made low level by clearing the NRZn bit = 0. Remark n = 0, 1
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Figure 9-8. Carrier Generator Mode (2/3) Operation when the CMPn0 register = N, the CMPn1 register = M is set
8-bit timer Hn count clock 8-bit timer counter Hn count value CMPn0 CMPn1 TMHEn INTTMHn <1> <2> Carrier clock 8-bit timer 5n count clock TM5n count value NRZBn TCE5n <5> INTTM5n INTTM5Hn NRZBn NRZn Carrier clock <6> TOHn <7> 0 0 1 1 0 0 1 1 0 0
00H 01H K K 00H 01H L L 00H 01H M 00H 01H M N 00H 01H N 00H N 00H 01H M 00H N N 00H 01H M 00H N 00H
M
<3>
<4>
<1> When the TMHEn bit = 0 and the TCE5n bit = 0, the operation of 8-bit timer Hn is stopped. <2> When the TMHEn bit is set to 1, 8-bit timer Hn starts counting. The carrier clock remains the default level at this time. <3> When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, the first INTTMHn signal is generated, the carrier clock signal is inverted, and the register that is compared with 8-bit timer counter Hn changes from the CMPn0 register to the CMPn1 register. 8-bit timer counter Hn is cleared to 00H. <4> When the count value of 8-bit timer counter Hn and the set value of the CMPn1 register match, the INTTMHn signal is generated, the carrier clock signal is inverted, and the register that is compared with 8-bit timer counter Hn changes from the CMPn1 register to the CMPn0 register. 8-bit timer counter Hn is cleared to 00H. A carrier clock with a fixed duty (other than 50%) is generated through the repetition of steps <3> and <4>. <5> The INTTM5n signal is generated. This signal is synchronized with 8-bit timer Hn and output as the INTTM5Hn signal. <6> The carrier is output from the rising edge of the first carrier clock by setting the NRZn bit = 1. <7> By setting the NRZn bit = 0, the TOHn output is also maintained high level while the carrier clock is high level, and does not change to low level (the high level width of the carrier waveform is guaranteed through steps <6> and <7>). Remark n = 0, 1
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Figure 9-8. Carrier Generator Mode (3/3) Operation based on the CMPn1 register transitions
8-bit timer Hn count clock
8-bit timer counter Hn count value
00H 01H
N
00H 01H
M
00H
N
00H 01H
L
00H
CMPn0 <3> CMPn1 M M (L)
N <3>' L
TMHEn
INTTMHn <2> Carrier clock <1> <4> <5>
<1> When the TMHEn bit is set to 1, counting starts. The carrier clock remains the default level at this time. <2> When the count value of the 8-bit timer counter Hn matches the value of the CMPn0 register, the INTTMHn signal is output, the carrier signal is inverted, and the 8-bit timer counter is cleared to 00H. At the same time, the compare register whose value is to be compared with that of the 8-bit timer counter Hn is changed from the CMPn0 register to the CMPn1 register. <3> The CMPn1 register is asynchronous to the count clock, and its value can be changed while the 8-bit timer Hn is operating. The new value (L) to which the value of the register is to be changed is latched. When the count value of the 8-bit timer counter Hn matches the value (M) of the CMPn1 register before the change, the CMPn1 register is changed (<3>'). However, it takes three count clocks or more since the value of the CMPn1 register has been changed until the value is transferred to the register. Even if a match signal is generated before the duration of three count clocks elapses, the new value is not transferred to the register. <4> When the count value of 8-bit timer counter Hn and the value (M) of the CMPn1 register match, the INTTMHn signal is output, the carrier signal is inverted, and 8-bit timer counter Hn is cleared to 00H. At the same time, the compare register whose value is to be compared with that of the 8-bit timer counter Hn is changed from the CMPn1 register to the CMPn0 register. <5> The timing at which the count value of 8-bit timer counter Hn and the value of the CMPn1 register match again is the changed value (L). Remark n = 0, 1
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CHAPTER 10 INTERVAL TIMER, WATCH TIMER
The V850ES/KE2 includes interval timer BRG and a watch timer. Interval timer BRG can also be used as the source clock of the watch timer. The watch timer can also be used as interval timer WT. Two interval timer channels and one watch timer channel can be used at the same time.
10.1 Interval Timer BRG
10.1.1 Functions Interval timer BRG has the following functions. * Interval timer BRG: An interrupt request signal (INTBRG) is generated at a specified interval. * Generation of count clock for watch timer: When the main clock is used as the count clock for the watch timer, a count clock (fBRG) is generated. 10.1.2 Configuration The following shows the block diagram of interval timer BRG. Figure 10-1. Block Diagram of Interval Timer BRG
fX
Clock control
3-bit prescaler fX/8 fX/4 fX/2 fX
Selector
fBGCS Clear
INTBRG 8-bit counter Match Output control fBRG Count clock for watch timer
1/2
2
PRSCM register
BGCE
TODIS
BGCS1
BGCS0
PRSM register Internal bus
Remark
fX: fBGCS: fBRG:
Main clock oscillation frequency Interval timer BRG count clock frequency Watch timer count clock frequency
INTBRG: Interval timer BRG interrupt request signal
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(1) Clock control The clock control controls supply/stop of the operation clock of interval timer BRG. (2) 3-bit prescaler The 3-bit prescaler divides fX to generate fX/2, fX/4, and fX/8. (3) Selector The selector selects the count clock (fBGCS) for interval timer BRG from fX, fX/2, fX/4, and fX/8. (4) 8-bit counter The 8-bit counter counts the count clock (fBGCS). (5) Output control The output control controls supply of the count clock (fBRG) for the watch timer. (6) PRSCM register The PRSCM register is an 8-bit compare register that sets the interval time. (7) PRSM register The PRSM register controls the operation of interval timer BRG, the selector, and clock supply to the watch timer.
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10.1.3 Registers Interval timer BRG includes the following registers. (1) Interval timer BRG mode register (PRSM) PRSM controls the operation of interval timer BRG, selection of count clock, and clock supply to the watch timer. This register can be read or written in 8-bit or 1-bit units. Reset sets PRSM to 00H.
After reset: 00H
R/W
Address: FFFFF8B0H <>
PRSM
0
0
0
BGCE
0
TODIS
BGCS1
BGCS0
BGCE 0 1
Control of interval timer operation Operation stopped, 8-bit counter cleared to 01H Operate
TODIS 0 1
Control of clock supply for watch timer Clock for watch timer supplied Clock for watch timer not supplied
BGCS1
BGCS0
Selection of input clock (fBGCS)Note 10 MHz 5 MHz 200 ns 400 ns 800 ns 1.6 s 4 MHz 250 ns 500 ns 1 s 2 s
0 0 1 1
0 1 0 1
fX fX/2 fX/4 fX/8
100 ns 200 ns 400 ns 800 ns
Note Set these bits so that the following conditions are satisfied. VDD = 4.0 to 5.5 V: fBGCS 10 MHz VDD = 2.7 to 4.0 V: fBGCS 5 MHz Cautions 1. Do not change the values of the TODIS, BGCS1, and BGCS0 bits while interval timer BRG is operating (BGCE bit = 1). Set the TODIS, BGCS1, and BGCS0 bits before setting (1) the BGCE bit. 2. When the BGCE bit is cleared (to 0), the 8-bit counter is cleared.
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(2) Interval timer BRG compare register (PRSCM) PRSCM is an 8-bit compare register. This register can be read or written in 8-bit units. Reset sets PRSCM to 00H.
After reset: 00H
R/W
Address: FFFFF8B1H
PRSCM
PRSCM7 PRSCM6 PRSCM5 PRSCM4 PRSCM3 PRSCM2 PRSCM1 PRSCM0
Caution Do not rewrite the PRSCM register while interval timer BRG is operating (PRSM.BGCE bit = 1). before setting (1) the BGCE bit. Set the PRSCM register
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10.1.4 Operation (1) Operation of interval timer BRG Set the count clock by using the BGCS1 and BGCS0 bits of PRSM and the 8-bit compare value by using the PRSCM register. When the PRSM.BGCE bit is set (1), interval timer BRG starts operating. Each time the count value of the 8-bit counter and the set value in the PRSCM register match, an interrupt request signal (INTBRG) is generated. At the same time, the 8-bit counter is cleared to 00H and counting is continued. The interval time can be obtained from the following equation. Interval time = 2m x N/fX Remark m: Division value (set values of BGCS1 and BGCS0 bits) = 0 to 3 N: Set value in PRSCM register = 1 to 256 (when the set value in the PRSCM register is 00H, N = 256) fX: Main clock oscillation frequency (2) Count clock supply for watch timer Set the count clock by using the BGCS1 and BGCS0 bits of PRSM and the 8-bit compare value by using the PRSCM register, so that the count clock frequency (fBRG) of the watch timer is 32.768 kHz. Clear (0) the PRSM.TODIS bit at the same time. When the PRSM.BGCE bit is set (1), fBRG is supplied to the watch timer. fBRG is obtained from the following equation. fBRG = fX/(2m+ 1 x N) To set fBRG to 32.768 kHz, perform the following calculation to set the BGCS1 and BGCS0 bits and the PRSCM register. <1> Set N = fX/65,536 (round off the decimal) to set m = 0. <2> If N is even, N = N/2 and m = m + 1 <3> Repeat step <2> until N is even or m = 3 <4> Set N to the PRSCM register and m to the BGCS1 and BGCS0 bits. Example: When fX = 4.00 MHz <1> N = 4,000,000/65,536 = 61 (round off the decimal), m = 0 <2>, <3> Since N is odd, the values remain as N = 61, m = 0 <4> The set value in the PRSCM register: 3DH (61), the set values in the BGCS1 and BGCS0 bits: 00 Remark m: Divided value (set value in the BGCS1 and BGCS0 bits) = 0 to 3 N: Set value in PRSCM register = 1 to 256 (when the set value in the PRSCM register is 00H, N = 256) fX: Main clock oscillation frequency
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10.2 Watch Timer
10.2.1 Functions The watch timer has the following functions. * Watch timer: An interrupt request signal (INTWT) is generated at time intervals of 0.5 or 0.25 seconds by using the main clock or subclock. * Interval timer: An interrupt request signal (INTWTI) is generated at the preset time interval. The watch timer and interval timer functions can be used at the same time. 10.2.2 Configuration The following shows the block diagram of the watch timer. Figure 10-2. Block Diagram of Watch Timer
Clear
Selector
Selector
5-bit counter
Selector
INTWT
fBRG fXT
fW
11-bit prescaler fW/24 fW/25 fW/26 fW/27 fW/28 fW/210 fW/211 fW/29
Clear
Selector
INTWTI
3
WTM7
WTM6
WTM5
WTM4
WTM3
WTM2
WTM1
WTM0
Watch timer operation mode register (WTM) Internal bus
Remark
fBRG: fXT: fW: INTWT:
Frequency of count clock from interval timer BRG Subclock frequency Watch timer clock frequency Watch timer interrupt request signal
INTWTI: Interval timer interrupt request signal
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(1) 11-bit prescaler The 11-bit prescaler generates a clock of fW/24 to fW/211 by dividing fW. (2) 5-bit counter The 5-bit counter generates the watch timer interrupt request signal (INTWT) at intervals of 24/fW, 25/fW, 213/fW, or 214/fW by counting fW or fW/29. (3) Selectors The watch timer has the following four selectors. * Selector that selects the main clock (the clock from interval timer BRG (fBRG)) or the subclock (fXT) as the clock for the watch timer. * Selector that selects fW or fW/29 as the count clock frequency of the 5-bit counter * Selector that selects 24/fW or 213/fW, or 25/fW or 214/fW as the INTWT signal generation time interval. * Selector that selects the generation time interval of the interval timer WT interrupt request signal (INTWTI) from 24/fW to 211/fW. (4) 8-bit counter The 8-bit counter counts the count clock (fBGCS). (5) WTM register The WTM register is an 8-bit register that controls the operation of the watch timer/interval timer WT and sets the interval of interrupt request signal generation. 10.2.3 Registers The watch timer includes the following register. (1) Watch timer operation mode register (WTM) This register enables or disables the count clock and operation of the watch timer, sets the interval time of the 11-bit prescaler, controls the operation of the 5-bit counter, and sets the timer of watch timer interrupt request signal (INTWT) generation. The WTM register can be read or written in 8-bit or 1-bit units. Reset sets WTM to 00H.
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After reset: 00H
R/W
Address: FFFFF680H <> <> WTM0
WTM
WTM7
WTM6
WTM5
WTM4
WTM3
WTM2
WTM1
WTM7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
WTM6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
WTM5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
WTM4 Selection of interval timer interrupt (INTWTI) time 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 24/fW (488 s: fW = fXT) 25/fW (977 s: fW = fXT) 26/fW (1.95 ms: fW = fXT) 27/fW (3.91 ms: fW = fXT) 28/fW (7.81 ms: fW = fXT) 29/fW (15.6 ms: fW = fXT) 210/fW (31.3 ms: fW = fXT) 211/fW (62.5 ms: fW = fXT) 24/fW (488 s: fW = fBRG) 25/fW (977 s: fW = fBRG) 26/fW (1.95 ms: fW = fBRG) 27/fW (3.91 ms: fW = fBRG) 28/fW (7.81 ms: fW = fBRG) 29/fW (15.6 ms: fW = fBRG) 210/fW (31.3 ms: fW = fBRG) 211/fW (62.5 ms: fW = fBRG)
WTM7 0 0 0 0 1 1 1 1
WTM3 0 0 1 1 0 0 1 1
WTM2 0 1 0 1 0 1 0 1
Selection of watch timer interrupt (INTWT) time 214/fW (0.5 s: fW = fXT) 213/fW (0.25 s: fW = fXT) 25/fW (977 s: fW = fXT) 24/fW (488 s: fW = fXT) 214/fW (0.5 s: fW = fBRG) 213/fW (0.25 s: fW = fBRG) 25/fW (977 s: fW = fBRG) 24/fW (488 s: fW = fBRG)
WTM1 0 1
Control of 5-bit counter operation Clear after operation stops Start
WTM0 0 1
Watch timer operation enable Stop operation (clear both prescaler and 5-bit counter) Enable operation
Caution Rewrite the WTM2 to WTM7 bits while both the WTM0 and WTM1 bits are 0. Remarks 1. fW: Watch timer clock frequency 2. Values in parentheses apply when fW = 32.768 kHz
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10.2.4 Operation (1) Operation as watch timer The watch timer generates an interrupt request at fixed time intervals. The watch timer operates using time intervals of 0.25 or 0.5 seconds with the subclock (32.768 kHz). The count operation starts when the WTM.WTM0 and WTM.WTM1 bits are set to 11. When these bits are cleared to 00, the 10-bit prescaler and 5-bit counter are cleared and the count operation stops. The 5-bit counter can be cleared to synchronize the time by clearing the WTM1 bit to 0 when the watch timer and interval timer WT operate simultaneously. At this time, an error of up to 15.6 ms may occur in the watch timer, but interval timer WT is not affected. (2) Operation as interval timer The watch timer can also be used as an interval timer that repeatedly generates an interrupt request signal (INTWTI) at intervals specified by a count value set in advance. The interval time can be selected by the WTM.WTM4 to WTM.WTM7 bits. Table 10-1. Interval Time of Interval Timer
WTM7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WTM6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WTM5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WTM4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 x 1/fW
4
Interval Time 488 s (operating at fW = fXT = 32.768 kHz) 977 s (operating at fW = fXT = 32.768 kHz) 1.95 ms (operating at fW = fXT = 32.768 kHz) 3.91 ms (operating at fW = fXT = 32.768 kHz) 7.81 ms (operating at fW = fXT = 32.768 kHz) 15.6 ms (operating at fW = fXT = 32.768 kHz) 31.3 ms (operating at fW = fXT = 32.768 kHz) 62.5 ms (operating at fW = fXT = 32.768 kHz) 488 s (operating at fW = fBRG = 32.768 kHz) 977 s (operating at fW = fBRG = 32.768 kHz) 1.95 ms (operating at fW = fBRG = 32.768 kHz) 3.91 ms (operating at fW = fBRG = 32.768 kHz) 7.81 ms (operating at fW = fBRG = 32.768 kHz) 15.6 ms (operating at fW = fBRG = 32.768 kHz) 31.3 ms (operating at fW = fBRG = 32.768 kHz) 62.5 ms (operating at fW = fBRG = 32.768 kHz)
2 x 1/fW
5
2 x 1/fW
6
2 x 1/fW
7
2 x 1/fW
8
2 x 1/fW
9
2 x 1/fW
10
2 x 1/fW
11
2 x 1/fW
4
2 x 1/fW
5
2 x 1/fW
6
2 x 1/fW
7
2 x 1/fW
8
2 x 1/fW
9
2 x 1/fW
10
2 x 1/fW
11
Remark
fW: Watch timer clock frequency
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Figure 10-3. Operation Timing of Watch Timer/Interval Timer
5-bit counter
0H Start Count clock fW or fW/29 Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time (T) nT Interval time (T) nT Overflow Overflow
Remarks 1. Assuming that the interrupt time of the watch timer is set to 0.5 seconds. 2. fW: Watch timer clock frequency Values in parentheses apply when count clock fW = 32.768 kHz. n: Number of interval timer WT operations
10.3 Cautions
(1) Operation as watch timer Some time is required before the first watch timer interrupt request (INTWT) is generated after operation is enabled (WTM.WTM1 and WTM.WTM0 bits = 11). Figure 10-4. Example of Generation of Watch Timer Interrupt Request (INTWT) (When Interrupt Period = 0.5 s)
It takes 0.515625 (max.) seconds for the first INTWT to be generated (29 x 1/32768 = 0.015625 (max.) s longer). INTWT is then generated every 0.5 seconds.
WTM0, WTM1 0.515625 s 0.5 s 0.5 s
INTWT
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(2) When watch timer and interval timer BRG operate simultaneously When using the subclock as the count clock for the watch timer, the interval time of interval timer BRG can be set to any value. Changing the interval time does not affect the watch timer (before changing the interval time, stop operation). When using the main clock as the count clock for the watch timer, set the interval time of interval timer BRG to approximately 65.536 kHz. Do not change this value. (3) When interval timer BRG and interval timer WT operate simultaneously When using the subclock as the count clock for interval timer WT, the interval times of interval timers BRG and WT can be set to any values. They can also be changed later (before changing the value, stop operation). When using the main clock as the count clock for interval timer WT, the interval time of interval timer BRG can be set to any value, but cannot be changed later (it can be changed only when interval timer WT stops operation). The interval time of interval timer WT can be set to x 25 to x 212 of the set value of interval timer BRG. It can also be changed later. (4) When watch timer and interval timer WT operate simultaneously The interval time of interval timer WT can be set to a value between 488 s and 62.5 ms. It cannot be changed later. Do not stop interval timer WT (clear (0) the WTM.WTM0 bit) while the watch timer is operating. If the WTM0 bit is set (1) after it had been cleared (0), the watch timer will have a discrepancy of up to 0.5 or 0.25 seconds. (5) When watch timer, interval timer BRG, and interval timer WT operate simultaneously When using the subclock as the count clock for the watch timer, the interval times of interval timers BRG and WT can be set to any values. The interval time of interval timer BRG can be changed later (before changing the value, stop operation). When using the main clock as the count clock for the watch timer, set the interval time of interval timer BRG to approximately 65.536 kHz. It cannot be changed later. The interval time of interval timer WT can be set to a value between 488 s and 62.5 ms. It cannot be changed later. Do not stop interval timer BRG (clear (0) the PRSM.BGCE bit) or interval timer WT (clear (0) the WTM.WTM0 bit) while the watch timer is operating.
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11.1 Watchdog Timer 1
11.1.1 Functions Watchdog timer 1 has the following operation modes. * Watchdog timer * Interval timer The following functions are realized from the above-listed operation modes. * Generation of non-maskable interrupt request signal (INTWDT1) upon overflow of watchdog timer 1Note * Generation of system reset signal (WDTRES1) upon overflow of watchdog timer 1 * Generation of maskable interrupt request signal (INTWDTM1) upon overflow of interval timer Note For non-maskable interrupt servicing due to non-maskable interrupt request signal (INTWDT1, INTWDT2), refer to 17.10 Cautions. Remark Select whether to use watchdog timer 1 in the watchdog timer 1 mode or the interval timer mode with the WDTM1 register.
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Figure 11-1. Block Diagram of Watchdog Timer 1
Internal bus Watchdog timer mode register 1 (WDTM1) RUN1 WDTM14 WDTM13 Watchdog timer clock selection register (WDCS) WDCS2 WDCS1 WDCS0
2 Clear fXW Prescaler fXW/221 fXW/219 fXW/218
Selector
3
fXW/217 fXW/216 fXW/2 fXW/2
15 14
INTWDTM1 Output controller INTWDT1 WDTRES1
fXW/213
Remark
INTWDTM1: Request signal for maskable interrupt through watchdog timer 1 overflow INTWDT1: fXW = fX: Request signal for non-maskable interrupt through watchdog timer 1 overflow Watchdog timer 1 clock frequency WDTRES1: Reset signal through watchdog timer 1 overflow
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11.1.2 Configuration Watchdog timer 1 includes the following hardware. Table 11-1. Configuration of Watchdog Timer 1
Item Control register Configuration Watchdog timer clock selection register (WDCS) Watchdog timer mode register 1 (WDTM1)
11.1.3 Registers The registers that control watchdog timer 1 are as follows. * Watchdog timer clock selection register (WDCS) * Watchdog timer mode register 1 (WDTM1) (1) Watchdog timer clock selection register (WDCS) This register sets the overflow time of watchdog timer 1 and the interval timer. The WDCS register can be read or written in 8-bit or 1-bit units. Reset sets WDCS to 00H.
After reset: 00H
R/W
Address: FFFFF6C1H
WDCS
0
0
0
0
0
WDCS2
WDCS1
WDCS0
WDCS2
WDCS1
WDCS0
Overflow time of watchdog timer 1/interval timer fXW 4 MHz 5 MHz 1.638 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 419.4 ms 10 MHz 0.819 ms 1.638 ms 3.277 ms 6.554 ms 13.11 ms 26.2 ms 52.43 ms 209.7 ms
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
2 /fXW 2 /fXW 2 /fXW 216/fXW 2 /fXW 2 /fXW 2 /fXW 221/fXW
19 18 17 15 14
13
2.048 ms 4.096 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 524.3 ms
Remark
fXW = fX: Watchdog timer 1 clock frequency
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(2) Watchdog timer mode register 1 (WDTM1) This register sets the watchdog timer 1 operation mode and enables/disables count operations. This register is a special register that can be written only in a special sequence (refer to 3.4.7 Special registers). The WDTM1 register can be read or written in 8-bit or 1-bit units. Reset sets WDTM1 to 00H. Caution When the main clock is stopped and the CPU is operating on the subclock, do not access the WDTM1 register. For details, refer to 3.4.8 (1) (b).
After reset: 00H <> WDTM1 RUN1
R/W
Address: FFFFF6C2H
0
0
WDTM14 WDTM13
0
0
0
RUN1 0 1
Selection of operation mode of watchdog timer 1Note 1 Stop counting Clear counter and start counting
WDTM14 WDTM13 Selection of operation mode of watchdog timer 1Note 2 0 0 1 0 1 0 Interval timer mode (Upon overflow, maskable interrupt INTWDTM1 is generated.) Watchdog timer mode 1Note 3 (Upon overflow, non-maskable interrupt INTWDT1 is generated.) Watchdog timer mode 2 (Upon overflow, reset operation WDTRES1 is started.)
1
1
Notes 1. Once the RUN1 bit is set (to 1), it cannot be cleared (to 0) by software. Therefore, when counting is started, it cannot be stopped except reset. 2. Once the WDTM13 and WDTM14 bits are set (to 1), they cannot be cleared (to 0) by software and can be cleared only by reset. 3. For non-maskable interrupt servicing due to non-maskable interrupt request signal (INTWDT1), refer to 17.10 Cautions.
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11.1.4 Operation (1) Operation as watchdog timer 1 Watchdog timer 1 operation to detect a program loop is selected by setting the WDTM1.WDTM14 bit to 1. The count clock (program loop detection time interval) of watchdog timer 1 can be selected using the WDCS.WDCS0 to WDCS.WDCS2 bits. The count operation is started by setting the WDTM1.RUN1 bit to 1. When, after the count operation is started, the RUN1 bit is again set to 1 within the set program loop detection time interval, watchdog timer 1 is cleared and the count operation starts again. If the program loop detection time is exceeded without RUN1 bit being set to 1, reset signal (WDTRES1) through the value of the WDTM1.WDTM13 bit or a non-maskable interrupt request signal (INTWDT1) is generated. The count operation of watchdog timer 1 stops in the STOP mode and IDLE mode. Set the RUN1 bit to 1 before the STOP mode or IDLE mode is entered in order to clear watchdog timer 1. Because watchdog timer 1 operates in the HALT mode, make sure that an overflow will not occur during HALT. Cautions 1. When the subclock is selected for the CPU clock, the count operation of watchdog timer 1 is stopped (the value of watchdog timer 1 is maintained). 2. For non-maskable interrupt servicing due to the INTWDT1 signal, refer to 17.10 Cautions. Table 11-2. Program Loop Detection Time of Watchdog Timer 1
Clock Program Loop Detection Time fXW = 4 MHz 2 /fXW 2 /fXW 2 /fXW 2 /fXW 2 /fXW 2 /fXW 2 /fXW 2 /fXW
21 19 18 17 16 15 14 13
fXW = 5 MHz 1.638 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 419.4 ms
fXW = 10 MHz 0.819 ms 1.683 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 209.7 ms
2.048 ms 4.096 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 524.3 ms
Remark
fXW = fX: Watchdog timer 1 clock frequency
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(2) Operation as interval timer Watchdog timer 1 can be made to operate as an interval timer that repeatedly generates interrupts using the count value set in advance as the interval, by clearing the WDTM1.WDTM14 bit to 0. When watchdog timer 1 operates as an interval timer, the interrupt mask flag (WDTMK) and priority specification flags (WDTPR0 to WDTPR2) of the WDTIC register are valid and maskable interrupt request signals (INTWDTM1) can be generated. The default priority of the INTWDTM1 signal is set to the highest level among the maskable interrupt request signals. The interval timer continues to operate in the HALT mode, but it stops operating in the STOP mode and the IDLE mode. Cautions 1. Once the WDTM14 bit is set to 1 (thereby selecting the watchdog timer 1 mode), the interval timer mode is not entered as long as reset is not performed. 2. When the subclock is selected for the CPU clock, the count operation of the watchdog timer 1 stops (the value of the watchdog timer is maintained). Table 11-3. Interval Time of Interval Timer
Clock fXW = 4 MHz 2 /fXW 2 /fXW 2 /fXW 2 /fXW 2 /fXW 2 /fXW 2 /fXW 2 /fXW
21 19 18 17 16 15 14 13
Interval Time fXW = 5 MHz 1.638 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 419.4 ms fXW = 10 MHz 0.819 ms 1.638 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 209.7 ms
2.048 ms 4.096 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 524.3 ms
Remark
fXW = fX: Watchdog timer 1 clock frequency
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11.2 Watchdog Timer 2
11.2.1 Functions Watchdog timer 2 has the following functions. * Default start watchdog timerNote 1 Reset mode: Reset operation upon overflow of watchdog timer 2 (generation of WDTRES2 signal) Non-maskable interrupt request mode: NMI operation upon overflow of watchdog timer 2 (generation of INTWDT2 signal)Note 2 * Input selectable from main clock and subclock as the source clock Notes 1. Watchdog timer 2 automatically starts in the reset mode following reset release. When watchdog timer 2 is not used, either stop its operation before reset is executed through this function, or clear once watchdog timer 2 and stop it within the next interval time. Also, write to the WDTM2 register for verification purposes only once, even if the default settings (reset mode, interval time: fXX/225) need not be changed. 2. For non-maskable interrupt servicing due to a non-maskable interrupt request signal (INTWDT2), refer to 17.10 Cautions. Figure 11-2. Block Diagram of Watchdog Timer 2
fXX/29 fXT
Clock input controller 2
fXX/218 to fXX/225 16-bit Selector counter or fXT/29 to fXT/216 Clear 3
Output controller
INTWDT2 WDTRES2 (internal reset signal)
3
Watchdog timer enable register (WDTE)
0
WDM21 WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20
Watchdog timer mode register 2 (WDTM2) Internal bus
Remark
fXX: fXT: INTWDT2:
Main clock frequency Subclock frequency Non-maskable interrupt request signal through watchdog timer 2
WDTRES2: Watchdog timer 2 reset signal
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11.2.2 Configuration Watchdog timer 2 includes the following hardware. Table 11-4. Configuration of Watchdog Timer 2
Item Control register Configuration Watchdog timer mode register 2 (WDTM2) Watchdog timer enable register (WDTE)
11.2.3 Registers (1) Watchdog timer mode register 2 (WDTM2) This register sets the overflow time and operation clock of watchdog timer 2. The WDTM2 register can be read or written in 8-bit units. This register can be read any number of times, but it can be written only once following reset release. Reset sets WDTM2 to 67H. Caution When the main clock is stopped and the CPU is operating on the subclock, do not access the WDTM2 register. For details, refer to 3.4.8 (1) (b).
After reset: 67H
R/W
Address: FFFFF6D0H
WDTM2
0
WDM21
WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20
WDM21 0 0 1
WDM20 0 1 -
Selection of operation mode of watchdog timer 2 Stops operation Non-maskable interrupt request mode (generation of INTWDT2) Reset mode (generation of WDTRES2)
Cautions 1. To stop the operation of watchdog timer 2, write "1FH" to the WDTM2 register. 2. For details about bits WDCS0 to WDCS4, refer to Table 11-5 Watchdog Timer 2 Clock Selection. 3. If the WDTM2 register is written twice after a reset, an overflow signal is forcibly output. 4. To intentionally generate an overflow signal, write data to the WDTM2 register only twice, or write a value other than "ACH" to the WDTE register only once.
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Table 11-5. Watchdog Timer 2 Clock Selection
WDCS24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 WDCS23 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x WDCS22 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x WDCS21 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 x WDCS20 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x Selected Clock 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXT 2 /fXT 2 /fXT 2 /fXT 2 /fXT 2 /fXT 2 /fXT 2 /fXT
16 15 14 13 12 11 10 9 25 24 23 22 21 20 19 18
fXX = 20 MHz 13.1 ms 26.2 ms 52.4 ms 104.9 ms 209.7 ms 419.4 ms 838.9 ms 1677.7 ms
fXX = 16 MHz 16.4 ms 32.8 ms 65.5 ms 131.1 ms 262.1 ms 524.3 ms 1048.6 ms 2097.2 ms
fXX = 10 MHz 26.2 ms 52.4 ms 104.9 ms 209.7 ms 419.4 ms 838.9 ms 1677.7 ms 3355.4 ms
15.625 ms (fXT = 32.768 kHz) 31.25 ms (fXT = 32.768 kHz) 62.5 ms (fXT = 32.768 kHz) 125 ms (fXT = 32.768 kHz) 250 ms (fXT = 32.768 kHz) 500 ms (fXT = 32.768 kHz) 1000 ms (fXT = 32.768 kHz) 2000 ms (fXT = 32.768 kHz)
Operation stopped
(2) Watchdog timer enable register (WDTE) The counter of watchdog timer 2 is cleared and counting restarted by writing "ACH" to the WDTE register. The WDTE register can be read or written in 8-bit units. Reset sets WDTE to 9AH.
After reset: 9AH
R/W
Address: FFFFF6D1H
WDTE
Cautions 1. When a value other than "ACH" is written to the WDTE register, an overflow signal is forcibly output. 2. When a 1-bit memory manipulation instruction is executed for the WDTE register, an overflow signal is forcibly output. 3. The read value of the WDTE register is always "9AH" (value that differs from written value "ACH"). 4. To intentionally generate an overflow signal, write a value other than "ACH" to the WDTE register only once, or write data to the WDTM2 register only twice.
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11.2.4 Operation Watchdog timer 2 automatically starts in the reset mode following reset release. The WDTM2 register can be written to only once following reset through byte access. To use watchdog timer 2, write the operation mode and the interval time to the WDTM2 register using 8-bit memory manipulation instructions. After this is done, the operation of watchdog timer 2 cannot be stopped. The watchdog timer 2 program loop detection time interval can be selected by the WDTM2.WDCS24 to WDTM2.WDCS20 bits. Writing ACH to the WDTE register clears the counter of watchdog timer 2 and starts the count operation again. After the count operation starts, write ACH to the WDTE register within the set program loop detection time interval. If the program loop detection time is exceeded without ACH being written to the WDTE register, a reset signal (WDTRES2) or non-maskable interrupt request signal (INTWDT2) is generated depending on the set value of the WDTM2.WDM21 and WDTM2.WDM20 bits. To not use watchdog timer 2, write 1FH to the WDTM2 register. For non-maskable interrupt servicing when the non-maskable interrupt request mode is set, refer to 17.10 Cautions. If the main clock is selected as the source clock of watchdog timer 2, the watchdog timer stops operation in the IDLE/STOP mode. Therefore, clear watchdog timer 2 by writing ACH to the WDTE register before the IDLE/STOP mode is set. Because watchdog timer 2 operates in the HALT mode or when the subclock is selected as its source clock in the IDLE/STOP mode, exercise care that the timer does not overflow in the HALT mode.
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CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO)
12.1 Function
The real-time output function (RTO) transfers preset data to the RTBL0 and RTBH0 registers, and then transfers this data with hardware to an external device via the real-time output latches, upon occurrence of a timer interrupt. The pins through which the data is output to an external device constitute a port called a real-time output port. Because RTO can output signal without jitter, it is suitable for controlling a stepping motor. In the V850ES/KE2, a 6-bit real-time output port channel is provided. The real-time output port can be set in the port mode or real-time output port mode in 1-bit units. The block diagram of RTO is shown below. Figure 12-1. Block Diagram of RTO
Internal bus
Real-time buffer register 0H (RTBH0)
Real-time output latch 0H
2 RTPOUT04, RTPOUT05
Real-time buffer register 0L (RTBL0)
Real-time output latch 0L
4 RTPOUT00 to RTPOUT03
INTTM50
Transfer trigger (H) Selector
INTTM51
Transfer trigger (L)
2 4
RTPOE0 RTPEG0 BYTE0
EXTR0
RTPM05 RTPM04 RTPM03 RTPM02 RTPM01 RTPM00
Real-time output port control register 0 (RTPC0)
Real-time output port mode register 0 (RTPM0)
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12.2 Configuration
RTO includes the following hardware. Table 12-1. Configuration of RTO
Item Registers Control registers Configuration Real-time output buffer register 0 (RTBL0, RTBH0) Real-time output port mode register 0 (RTPM0) Real-time output port control register 0 (RTPC0)
(1) Real-time output buffer register 0 (RTBL0, RTBH0) RTBL0 and RTBH0 are 4-bit registers that hold output data in advance. These registers are mapped to independent addresses in the peripheral I/O register area. They can be read or written in 8-bit or 1-bit units. If an operation mode of 4 bits x 1 channel or 2 bits x 1 channel is specified (RTPC0.BYTE0 bit = 0), data can be individually set to the RTBL0 and RTBH0 registers. The data of both these registers can be read at once by specifying the address of either of these registers. If an operation mode of 6 bits x 1 channel is specified (BYTE0 bit = 1), 8-bit data can be set to both the RTBL0 and RTBH0 registers by writing the data to either of these registers. Moreover, the data of both these registers can be read at once by specifying the address of either of these registers. Table 12-2 shows the operation when the RTBL0 and RTBH0 registers are manipulated.
After reset: 00H
R/W
Address: RTBL0 FFFFF6E0H, RTBH0 FFFFF6E2H
RTBL0 RTBH0 0 0 RTBH05 RTBH04
RTBL03
RTBL02
RTBL01
RTBL00
Cautions 1. When writing to bits 6 and 7 of the RTBH0 register, always write 0. 2. When the main clock is stopped and the CPU is operating on the subclock, do not access the RTBL0 and RTBH0 registers using an access method that causes a wait. For details, refer to 3.4.8 (1) (b).
Table 12-2. Operation During Manipulation of RTBL0 and RTBH0 Registers
Operation Mode Register to Be Manipulated 4 bits x 1 channel, 2 bits x 1 channel 6 bits x 1 channel RTBL0 RTBH0 RTBL0 RTBH0 Higher 4 Bits RTBH0 RTBH0 RTBH0 RTBH0 Read Lower 4 Bits RTBL0 RTBL0 RTBL0 RTBL0 Write Higher 4 Bits Invalid RTBH0 RTBH0 RTBH0
Note
Lower 4 Bits RTBL0 Invalid RTBL0 RTBL0
Note After setting the real-time output port, set output data to the RTBL0 and RTBH0 registers by the time a realtime output trigger is generated.
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12.3 Registers
RTO is controlled using the following two types of registers. * Real-time output port mode register 0 (RTPM0) * Real-time output port control register 0 (RTPC0) (1) Real-time output port mode register 0 (RTPM0) This register selects the real-time output port mode or port mode in 1-bit units. The RTPM0 register can be read or written in 8-bit or 1-bit units. Reset sets RTPM0 to 00H.
After reset: 00H
R/W
Address: FFFFF6E4H
RTPM0
0
0
RTPM05 RTPM04 RTPM03 RTPM02 RTPM01 RTPM00
RTPM0m 0 1
Control of real-time output port (m = 0 to 5) Real-time output disabled Real-time output enabled
Cautions 1. To reflect real-time output signals (RTPOUT00 to RTPOUT05) to the pins (RTP00 to RTP05), set them to the real-time output port with the PMC5 and PFC5 registers. 2. By enabling real-time output operation (RTPC0.RTPOE0 bit = 1), the bits specified as real-time output enabled perform real-time output, and the bits specified as real-time output disabled output 0. 3. If real-time output is disabled (RTPOE0 bit = 0), real-time output signals (RTPOUT00 to RTPOUT05) all output 0, regardless of the RTPM0 register setting.
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(2) Real-time output port control register 0 (RTPC0) This register sets the operation mode and output trigger of the real-time output port. The relationship between the operation mode and output trigger of the real-time output port is as shown in Table 12-3. The RTPC0 register can be read or written in 8-bit or 1-bit units. Reset sets RTPC0 to 00H.
After reset: 00H <> RTPC0
R/W
Address: FFFFF6E5H
RTPOE0 RTPEG0Note 1
BYTE0 EXTR0Note 2
0
0
0
0
RTPOE0 0 1 Disables operation Enables operation
Control of real-time output operation
Note 3
BYTE0 0 1
Specification of channel configuration for real-time output 4 bits x 1 channel, 2 bits x 1 channel 6 bits x 1 channel
Notes 1. The value of the RTPEG0 bit does not affect the operation. 2. For the EXTR0 bit, refer to Table 12-3. 3. When real-time output operation is disabled (RTPOE0 bit = 0), real-time output signals (RTPOUT00 to RTPOUT05) all output 0. Caution Perform the settings for the BYTE0 and EXTR0 bits only when the RTPOE0 bit = 0.
Table 12-3. Operation Modes and Output Triggers of Real-Time Output Port
BYTE0 0 EXTR0 0 1 1 0 1 Operation Mode 4 bits x 1 channel, 2 bits x 1 channel 6 bits x 1 channel RTBH0 (RTP04, RTP05) INTTM51 INTTM50 INTTM50 Setting prohibited RTBL0 (RTP00 to RTP03) INTTM50 No trigger
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12.4 Operation
If the real-time output operation is enabled by setting the RTPC0.RTPOE0 bit to 1, the data of the RTBH0 and RTBL0 registers is transferred to the real-time output latch in synchronization with the generation of the selected transfer trigger (set by the RTPC0.EXTR0 and RTPC0.BYTE0 bits). Of the transferred data, only the data of the bits specified as real-time output enabled by the RTPM0 register is output from bits RTPOUT00 to RTPOUT05. The bits specified as real-time output disabled by the RTPM0 register output 0. If the real-time output operation is disabled by clearing the RTPOE0 bit to 0, the RTPOUT00 to RTPOUT05 signals output 0 regardless of the setting of the RTPM0 register. Figure 12-2. Example of Operation Timing of RTO0 (When EXTR0 and BYTE0 Bits = 00)
INTTM51 (internal)
INTTM50 (internal)
CPU operation
A
B
A
B
A
B
A
B
RTBH0 D01
D02
D03
D04
RTBL0
D11
D12
D13
D14
RT output latch 0 (H)
D01
D02
D03
D04
RT output latch 0 (L)
D11
D12
D13
D14
A: Software processing by INTTM51 interrupt request signal (write to RTBH0 register) B: Software processing by INTTM50 interrupt request signal (write to RTBL0 register)
Remark
For the operation during standby, refer to CHAPTER 19 STANDBY FUNCTION.
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12.5 Usage
(1) Disable real-time output. Clear the RTPC0.RTPOE0 bit to 0. (2) Perform initialization as follows. * Specify the real-time output port mode or port mode in 1-bit units. Set the RTPM0 register. * Channel configuration: Select the trigger and valid edge. Set the RTPC0.EXTR0, RTPC0.BYTE0, and RTPC0.RTPEG0 bits. * Set the initial values to the RTBH0 and RTBL0 registersNote 1. (3) Enable real-time output. Set the RTPOE0 bit to 1. (4) Set the next output value to the RTBH0 and RTBL0 registers by the time the selected transfer trigger is generatedNote 2. (5) Set the next real-time output value to the RTBH0 and RTBL0 registers through interrupt servicing corresponding to the selected trigger. Notes 1. If write to the RTBH0 and RTBL0 registers is performed when the RTPOE0 bit = 0, that value is transferred to real-time output latches 0H and 0L, respectively. 2. Even if write is performed to the RTBH0 and RTBL0 registers when the RTPOE0 bit = 1, data transfer to real-time output latches 0H and 0L is not performed. Caution To reflect the real-time output signals (RTPOUT00 to RTPOUT05) to the pins, set the real-time output ports (RTP00 to RTP05) with the PMC5 and PFC5 registers.
12.6 Cautions
(1) Prevent the following conflicts by software. * Conflict between real-time output disable/enable switching (RTPOE0 bit) and selected real-time output trigger * Conflict between write to the RTBH0 and RTBL0 registers in the real-time output enabled status and the selected real-time output trigger. (2) Before performing initialization, disable real-time output (RTPOE0 bit = 0). (3) Once real-time output has been disabled (RTPOE0 bit = 0), be sure to initialize the RTBH0 and RTBL0 registers before enabling real-time output again (RTPOE0 bit = 0 1).
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12.7 Security Function
A circuit that sets the pin outputs to high impedance as a security function for when malfunctions of a stepping motor controlled by RTO occur is provided on chip. It forcibly resets the pins allocated to RTP00 to RTP05 via external interrupt INTP0 pin edge detection, placing them in the high-impedance state. The ports (P50 to P55 pins) placed in high impedance by INTP0Note 1 pin are initializedNote 2, so settings for these ports must be performed again. Notes 1. Regardless of the port settings, P50 to P55 pins are all placed in high impedance via the INTP0 pin. 2. The bits that are initialized are all the bits corresponding to P50 to P55 pins of the following registers. * P5 register * PM5 register * PMC5 register * PU5 register * PFC5 register The block diagram of the security function is shown below. Figure 12-3. Block Diagram of Security Function
INTP0
Edge detection
INTC EVDD
R RTOST0 RTPOUT00 to RTPOUT05 RTP00 to RTP05
6
This function is set with the PLLCTL.RTOST0 bit.
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(1) PLL control register (PLLCTL) The PLLCTL register is an 8-bit register that controls the RTO security function and PLL. This register can be read or written in 8-bit or 1-bit units. Reset sets PLLCTL to 01H.
After reset: 01H
R/W
Address: FFFFF806H <> <>
Note
<> PLLONNote
PLLCTL
0
0
0
0
0
RTOST0 SELPLL
RTOST0 0 1
Control of RTP00 to RTP05 security function INTP0 pin is not used as trigger for security function INTP0 pin is used as trigger for security function
Note For details on the SELPLL and PLLON bits, refer to CHAPTER 5 CLOCK GENERATION FUNCTION. Cautions 1. Before outputting a value to the real-time output ports (RTP00 to RTP05), select the INTP0 pin interrupt edge detection and then set the RTOST0 bit. 2. To set again the ports (P50 to P55 pins) as real-time output ports after placing them in high impedance via the INTP0 pin, first cancel the security function. [Procedure to set ports again] <1> Cancel the security function and enable port setting by clearing the RTOST0 bit to 0. <2> Set the RTOST0 bit to 1 (only if required). <3> Set again as real-time output port. 3. Be sure to clear bits 4 to 7 to "0". operation. Changing bit 3 does not affect the
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13.1 Overview
The A/D converter converts analog input signals into digital values and has an 8-channel (ANI0 to ANI7) configuration. The A/D converter has the following functions.
Operating voltage (AVREF0): 2.7 to 5.5 V Analog input pin: 8 Trigger mode:
Successive approximation method 10-bit A/D converter
* Software trigger mode * Timer trigger mode (INTTM010) * External trigger mode (ADTRG pin)
Operation mode
* Select mode * Scan mode
A/D conversion time:
* Normal mode: 14 to 100 s @ 4.0 V AVREF0 5.5 V 17 to 100 s @ 2.7 V AVREF0 < 4.0 V * High-speed mode: 3 to 100 s @ 4.5 V AVREF0 5.5 V 4.8 to 100 s @ 4.0 V AVREF0 < 4.5 V 6 to 100 s @ 2.85 V AVREF0 < 4.0 V 14 to 100 s @ 2.7 V AVREF0 < 2.85 V
Power fail detection function
Caution When using the A/D converter, operate with AVREF0 at the same potential as VDD and EVDD.
13.2 Functions
(1) 10-bit resolution A/D conversion 1 analog input channel is selected from the ANI0 to ANI7 pins, and an A/D conversion operation with resolution of 10 bits is repeatedly executed. Every time A/D conversion is completed, an interrupt request signal (INTAD) is generated. (2) Power fail detection function This is a function to detect low voltage in a battery. The results of A/D conversion (the value in the ADCRH register) and the PFT register are compared, and INTAD signal is generated only when the comparison conditions match.
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13.3 Configuration
The A/D converter includes the following hardware. Figure 13-1. Block Diagram of A/D Converter
AVREF0 ANI0 ANI1 ANI2 Sample & hold circuit ADCS bit
ANI4 ANI5 ANI6 ANI7
Selector
ANI3
AVSS
Tap selector
Voltage comparator
AVSS SAR register
Selector
INTTM010 ADTRG Edge detector
INTAD Controller Comparator 3 ADCR/ADCRH register PFT register
EGA1 EGA0 TRG ADTMD ADS2 ADS1 ADS0 ADCS ADMD FR2 FR1 FR0 ADHS1 ADHS0 ADCS2 ADS register ADM register Internal bus
PFEN PFCM PFM register
Table 13-1. Registers of A/D Converter Used by Software
Item Registers Configuration A/D conversion result register (ADCR) A/D conversion result register H (ADCRH): Only higher 8 bits can be read Power fail comparison threshold register (PFT) A/D converter mode register (ADM) Analog input channel specification register (ADS) Power fail comparison mode register (PFM)
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(1) ANI0 to ANI7 pins These are analog input pins for the 8 channels of the A/D converter. They are used to input analog signals to be converted into digital signals. Pins other than those selected as analog input by the ADS register can be used as input ports. (2) Sample & hold circuit The sample & hold circuit samples the analog input signals selected by the input circuit and sends the sampled data to the voltage comparator. This circuit holds the sampled analog input voltage during A/D conversion. (3) Series resistor string The series resistor string is connected between AVREF0 and AVSS and generates a voltage for comparison with the analog input signal. (4) Voltage comparator The voltage comparator compares the value that is sampled and held with the output voltage of the series resistor string. (5) Successive approximation register (SAR) This register compares the sampled analog voltage value with the voltage value from the series resistor string, and converts the comparison result starting from the most significant bit (MSB). When the least significant bit (LSB) has been converted to a digital value (end of A/D conversion), the contents of the SAR register are transferred to the ADCR register. The SAR register cannot be read or written directly. (6) A/D conversion result register (ADCR), A/D conversion result register H (ADCRH) Each time A/D conversion ends, the conversion results are loaded from the successive approximation register and the results of A/D conversion are held in the higher 10 bits of this register (the lower 6 bits are fixed to 0). (7) Controller The controller compares the A/D conversion results (the value of the ADCRH register) with the value of the PFT register when A/D conversion ends or the power fail detection function is used. It generates INTAD signal only when the comparison conditions match. (8) AVREF0 pin This is the analog power supply pin/reference voltage input pin of the A/D converter. Always use the same potential as the VDD pin even when not using the A/D converter. The signals input to the ANI0 to ANI7 pins are converted into digital signals based on the voltage applied across AVREF0 and AVSS. (9) AVSS pin This is the ground potential pin of the A/D converter. Always use the same potential as the VSS pin even when not using the A/D converter.
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(10) A/D converter mode register (ADM) This register sets the conversion time of the analog input to be converted to a digital signal and the conversion operation start/stop. (11) Analog input channel specification register (ADS) This register specifies the input port for the analog voltage to be converted to a digital signal. (12) Power fail comparison mode register (PFM) This register sets the power fail detection mode. (13) Power fail comparison threshold register (PFT) This register sets the threshold to be compared with the ADCR register.
13.4 Registers
The A/D converter is controlled by the following registers. * A/D converter mode register (ADM) * Analog input channel specification register (ADS) * Power fail comparison mode register (PFM) * Power fail comparison threshold register (PFT) * A/D conversion result register, A/D conversion result register H (ADCR, ADCRH)
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(1) A/D converter mode register (ADM) This register sets the conversion time of the analog input signal to be converted into a digital signal as well as conversion start and stop. The ADM register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
After reset: 00H <> ADM ADCS
R/W
Address: FFFFF200H <>
ADMD
FR2
Note 1
FR1
Note 1
FR0
Note 1
ADHS1
Note 1
ADHS0
Note 1
ADCS2
ADCS 0 1
Control of A/D conversion operation Conversion operation stopped Conversion operation enabled
ADMD 0 1 Select mode Scan mode
Control of operation mode
ADHS1 0 1
Selection of 5 V A/D conversion time mode (AVREF0 4.5 V) Normal mode High-speed mode (valid only when AVREF0 4.5 V) Selection of 3 V A/D conversion time mode (AVREF0 2.7 or 2.85 V) Normal mode High-speed mode (valid only when AVREF0 2.7 or 2.85 V)
ADHS0 0 1
ADCS2 0 1
Control of reference voltage generator for boostingNote 2 Reference voltage generator operation stopped Reference voltage generator operation enabled
Notes 1. For details of the FR2 to FR0 bits and the A/D conversion, refer to Table 13-2 A/D Conversion Time. 2. The operation of the reference voltage generator for boosting is controlled by the ADCS bit and it takes 1 s (high-speed mode) or 14 s (normal mode) after operation is started until it is stabilized. Therefore, the ADCS2 bit is set to 1 (A/D conversion is started) at least 1 s (high-speed mode) or 14 s (normal mode) after if the ADCS2 bit was set to 1 (reference voltage generator for boosting is on), the first conversion result is valid. Cautions 1. Changing bits FR2 to FR0, ADHS1, and ADHS0 while the ADCS bit = 1 is prohibited (write access to the ADM register is enabled and rewriting of bits FR2 to FR0, ADHS1, and ADHS0 is prohibited). 2. Setting ADHS1 and ADHS0 bits to 11 is prohibited. 3. Do not access the ADM register when the main clock is stopped and the subclock is operating. register. For details, refer to 3.4.8 (1) (b) Access to special on-chip peripheral I/O
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Table 13-2. A/D Conversion Time
ADHS1 ADHS0 FR2 FR1 FR0 20 MHz@ A/D Conversion Time (s) 16 MHz@ 8 MHz@ 8 MHz@ AVREF0 4.5 V AVREF0 4.0 V AVREF0 2.85 V AVREF0 2.7 V 0 0 0 0 0 0 0 0 0 1 288/fXX 14.4 240/fXX Setting prohibited 0 0 0 1 0 192/fXX Setting prohibited Setting prohibited 144/fXX Setting prohibited 120/fXX Setting prohibited 0 0 1 1 0 96/fXX Setting prohibited 0 0 0 1 1 0 1 0 1 0 Setting prohibited 96/fXX 4.8 6.0 12.0 Setting prohibited 0 1 0 0 1 72/fXX Setting prohibited 0 1 0 1 0 48/fXX Setting prohibited 0 1 0 1 1 24/fXX Setting prohibited 0 0 1 1 1 1 0 0 0 1 224/fXX 11.2 168/fXX Setting prohibited 0 1 1 1 0 112/fXX Setting prohibited 0 1 1 1 1 56/fXX Setting prohibited 1 0 0 0 0 72/fXX 3.6 Setting prohibited Setting prohibited Setting prohibited 1 0 0 0 1 54/fXX Setting prohibited 1 0 0 1 0 36/fXX Setting prohibited 1 0 0 1 x x 1 x x 18/fXX Setting prohibited 1 1 0 1 1 x Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited High-speed mode AVREF0 4.5 V Setting prohibited Setting prohibited Setting prohibited 14.0 10.5 Setting prohibited 28.0 21.0 6.0 9.0 Setting prohibited Setting prohibited Setting prohibited 28.0 21.0 High-speed mode AVREF0 2.7 V High-speed mode AVREF0 2.85 V Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited 18.0 18.0 Normal mode AVREF0 2.7 V Setting prohibited 24.0 24.0 18.0 15.0 36.0 30.0 36.0 30.0 Normal mode AVREF0 2.7 V Conversion Time Mode
0 0
0 0
0 1
1 0
1 0
0
0
1
0
1
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(a) Controlling reference voltage generator for boosting When the ADCS2 bit = 0, power to the A/D converter drops. The converter requires a setup time of 1 s (high-speed mode) or 14 s (normal mode) or more after the ADCS2 bit has been set to 1. Therefore, the result of A/D conversion becomes valid from the first result by setting the ADCS bit to 1 at least 1 s (high-speed mode) or 14 s (normal mode) after the ADCS2 bit has been set to 1. Table 13-3. Setting of ADCS Bit and ADCS2 Bit
ADCS 0 0 1 1 ADCS2 0 1 0 1 A/D Conversion Operation Stopped status (DC power consumption path does not exist) Conversion standby mode (only the reference voltage generator for boosting consumes power) Conversion mode (reference voltage generator stops operation Conversion mode (reference voltage generator is operating
Note 2 Note 1
)
)
Notes 1. If the ADCS and ADCS2 bits are changed from 00B to 10B, the reference voltage generator for boosting automatically turns on. If the ADCS bit is cleared to 0 while the ADCS2 bit is 0, the voltage generator automatically turns off. In the software trigger mode (ADS.TRG bit = 0), use of the first A/D conversion result is prohibited. In the hardware trigger mode (TRG bit = 1), use the A/D conversion result only if A/D conversion is started after the lapse of the oscillation stabilization time of the reference voltage generator for boosting. 2. If the ADCS and ADCS2 bits are changed from 00B to 11B, the reference voltage generator for boosting automatically turns on. If the ADCS bit is cleared to 0 while the ADCS2 bit is 1, the voltage generator stays on. In the software trigger mode (TRG bit = 0), use of the first A/D conversion result is prohibited. In the hardware trigger mode (TRG bit = 1), use the A/D conversion result only if A/D conversion is started after the lapse of the oscillation stabilization time of the reference voltage generator for boosting. Figure 13-2. Operation Sequence
Reference voltage generator for boosting: Operating ADCS2
Comparator control Conversion operation ADCS Conversion standby Conversion operation Conversion stop
Note
Note 1 s (high-speed mode) or 14 s (normal mode) or more are required for the operation of the reference voltage generator for boosting between when the ADCS2 bit is set (1) and when the ADCS bit is set (1).
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(2) Analog input channel specification register (ADS) This register specifies the analog voltage input port for A/D conversion. The ADS register can be read or written in 8-bit or 1-bit units. Reset sets ADS to 00H.
After reset: 00H
R/W
Address: FFFFF201H
ADS
EGA1Note 1 EGA0Note 1
TRG
ADTMDNote 2
0
ADS2
ADS1
ADS0
EGA1Note 1 EGA0Note 1 0 0 1 1 TRG 0 1 ADTMDNote 2 0 1 ADS2 0 1 0 1
Specification of external trigger signal (ADTRG) edge No edge detection Falling edge Rising edge Both rising and falling edges Trigger mode selection
Software trigger mode Hardware trigger mode Specification of hardware trigger mode External trigger (ADTRG pin input) Timer trigger (INTTM010 signal generated) ADS1 ADS0 Specification of analog input channel Select mode Scan mode ANI0 ANI0, ANI1 ANI0 to ANI2 ANI0 to ANI3 ANI0 to ANI4 ANI0 to ANI5 ANI0 to ANI6 ANI0 to ANI7
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7
Notes 1. The EGA1 and EGA0 bits are valid only when the hardware trigger mode (TRG bit = 1) and external trigger mode (ADTRG pin input: ADTMD bit = 1) are selected. 2. The ADTMD bit is valid only when the hardware trigger mode (TRG bit = 1) is selected. Cautions 1. Do not access the ADS register when the main clock is stopped and the subclock is operating. register. 2. Be sure to clear bit 3 to "0". For details, refer to 3.4.8 (1) (b) Access to special on-chip peripheral I/O
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(3) A/D conversion result register, A/D conversion result register H (ADCR, ADCRH) The ADCR and ADCRH registers store the A/D conversion results. These registers are read-only in 16-bit or 8-bit units. However, specify the ADCR register for 16-bit access, and the ADCRH register for 8-bit access. In the ADCR register, the 10 bits of conversion results are read in the higher 10 bits and 0 is read in the lower 6 bits. In the ADCRH register, the higher 8 bits of the conversion results are read. Reset makes these registers undefined.
After reset: Undefined
R
Address: FFFFF204H
ADCR
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
0
0
0
0
0
0
After reset: Undefined 7 ADCRH AD9 6 AD8
R
Address: FFFFF205H 5 AD7 4 AD6 3 AD5 2 AD4 1 AD3 0 AD2
Caution Do not access the ADCR and ADCRH registers when the main clock is stopped and the subclock is operating. For details, refer to 3.4.8 (1) (b) Access to special on-chip peripheral I/O register.
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The following shows the relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and A/D conversion results (ADCR register). SAR = INT ( VIN AVREF0 x 1024 + 0.5)
ADCRNote = SAR x 64 Or, (SAR - 0.5) x INT ( ): VIN: AVREF0: ADCR: AVREF0 1024 VIN < (SAR + 0.5) x AVREF0 1024
Function that returns the integer part of the value in parentheses Analog input voltage Voltage of AVREF0 pin Value in the ADCR register
Note The lower 6 bits of the ADCR register are fixed to 0. The following shows the relationship between the analog input voltage and A/D conversion results. Figure 13-3. Relationship Between Analog Input Voltage and A/D Conversion Results
SAR
ADCR
1023
FFC0H
1022
FF80H
A/D conversion results
1021
FF40H
3
00C0H
2
0080H
1
0040H
0
0000H 1 1 3 2 5 3 2048 1024 2048 1024 2048 1024 2043 1022 2045 1023 2047 1 2048 1024 2048 1024 2048
Input voltage/AVREF0
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(4) Power fail comparison mode register (PFM) This register sets the power fail detection mode. The PFM register compares the value in the PFT register with the value of the ADCRH register. The PFM register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
After reset: 00H <> PFM PFEN
R/W <> PFCM
Address: FFFFF202H
0
0
0
0
0
0
PFEN 0 1
Selection of power fail comparison enable/disable Power fail comparison disabled Power fail comparison enabled
PFCM 0 1
Selection of power fail comparison mode Interrupt request signal (INTAD) generated when ADCR PFT Interrupt request signal (INTAD) generated when ADCR < PFT
Caution Do not access the PFM register when the main clock is stopped and the subclock is operating. For details, refer to 3.4.8 (1) (b) Access to special on-chip peripheral I/O register.
(5) Power fail comparison threshold register (PFT) The PFT register sets the comparison value in the power fail detection mode. The 8-bit data set in the PFT register is compared with the value of the ADCRH register. The PFT register can be read or written in 8-bit units. Reset sets this register to 00H.
After reset: 00H 7 PFT
R/W 6
Address: FFFFF203H 5 4 3 2 1 0
Caution Do not access the PFT register when the main clock is stopped and the subclock is operating. For details, refer to 3.4.8 (1) (b) Access to special on-chip peripheral I/O register.
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13.5 Operation
13.5.1 Basic operation <1> Select the channel whose analog signal is to be converted into a digital signal using the ADS register. Set the ADM.ADHS1 or ADM.ADHS0 bit. <2> Set the ADM.ADCS2 bit to 1 and wait 1 s (high-speed mode) or 14 s (normal mode) or longer. <3> Set the ADM.ADCS bit to 1 to start A/D conversion. (Steps <4> to <10> are executed by hardware.) <4> The sample & hold circuit samples the voltage input to the selected analog input channel. <5> After sampling for a specific time, the sample & hold circuit enters the hold status and holds the input analog voltage until it has been converted into a digital signal. <6> Set bit 9 of the successive approximation register (SAR) to 1. The tap selector sets the voltage tap of the series resistor string to (1/2) x AVREF0. <7> The voltage comparator compares the voltage difference between the voltage tap of the series resistor string and the analog input voltage. If the analog input voltage is greater than (1/2) x AVREF0, the MSB of the SAR register remains set to 1. If the analog input voltage is less than (1/2) x AVREF0, the MSB is cleared to 0. <8> Next, bit 8 of the SAR register is automatically set to 1 and the next comparison starts. Depending on the previously determined value of bit 9, the voltage tap of the series resistor string is selected as follows. * Bit 9 = 1: (3/4) x AVREF0 * Bit 9 = 0: (1/4) x AVREF0 The analog input voltage is compared with one of these voltage taps and bit 8 of the SAR register is manipulated as follows depending on the result of the comparison. Analog input voltage voltage tap: Bit 8 = 1 Analog input voltage voltage tap: Bit 8 = 0 <9> The above steps are repeated until bit 0 of the SAR register has been manipulated. <10> When comparison of all 10 bits of the SAR register has been completed, the valid digital value remains in the SAR register, and the value of the SAR register is transferred and latched to the ADCR register. At the same time, an A/D conversion end interrupt request signal (INTAD) is generated. <11> Repeat steps <4> to <10> until the ADCS bit is cleared to 0. For another A/D conversion, start at <3>. However, when operating the A/D converter with the ADCS2 bit cleared to 0, start at <2>.
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13.5.2 Trigger modes The V850ES/KE2 has the following three trigger modes that set the A/D conversion start timing. These trigger modes are set by the ADS register. * Software trigger mode * External trigger mode (hardware trigger mode) * Timer trigger mode (hardware trigger mode) (1) Software trigger mode This mode is used to start A/D conversion by setting the ADM.ADCS bit to 1 while the ADS.TRG bit is 0. Conversion is repeatedly performed as long as the ADCS bit is not cleared to 0 after completion of A/D conversion. If the ADM, ADS, PFM, or PFT register is written during conversion, A/D conversion is aborted and started again from the beginning. (2) External trigger mode (hardware trigger mode) This is the status in which the ADS.TRG bit is set to 1 and ADS.ADTMD bit is cleared to 0. This mode is used to start A/D conversion by detecting an external trigger (ADTRG) after the ADCS bit has been set to 1. The A/D converter waits for the external trigger (ADTRG) after the ADCS bit is set to 1. The valid edge of the signal input to the ADTRG pin is specified by using the ADS.EGA1 and ADS.EGA0 bits. When the specified valid edge is detected, A/D conversion is started. When A/D conversion is completed, the A/D converter waits for the external trigger (ADTRG) again. If a valid edge is input to the ADTRG pin during A/D conversion, A/D conversion is aborted and started again from the beginning. If the ADM, ADS, PFM, or PFT register is written during conversion, A/D conversion is aborted and the A/D converter waits for an external trigger (ADTRG). (3) Timer trigger mode (hardware trigger mode) This mode is used to start A/D conversion by detecting a timer trigger (INTTM010) after the ADCS bit has been set to 1 with the TGR bit = 1 and ADTMD bit = 1. The A/D converter waits for the timer trigger (INTTM010) after the ADCS bit is set to 1. When the INTTM010 signal is generated, A/D conversion is started. When A/D conversion is completed, the A/D converter waits for the timer trigger (INTTM010) again. If the INTTM010 signal is generated during A/D conversion, A/D conversion is aborted and started again from the beginning. If the ADM, ADS, PFM, or PFT register is written during conversion, A/D conversion is aborted and the A/D converter waits for a timer trigger (INTTM010).
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13.5.3 Operation modes The following two operation modes are available. These operation modes are set by the ADM register. * Select mode * Scan mode (1) Select mode One input analog signal specified by the ADS register while the ADM.ADMD bit = 0 is converted. When conversion is complete, the result of conversion is stored in the ADCR register. At the same time, the A/D conversion end interrupt request signal (INTAD) is generated. However, the INTAD signal may or may not be generated depending on setting of the PFM and PFT registers. For details, refer to 13.5.4 Power fail detection function. If anything is written to the ADM, ADS, PFM, and PFT registers during conversion, A/D conversion is aborted. In the software trigger mode, A/D conversion is started from the beginning again. In the hardware trigger mode, the A/D converter waits for a trigger. If the trigger is detected during conversion in hardware trigger mode, A/D conversion is aborted and started again from the beginning. Figure 13-4. Example of Select Mode Operation Timing (ADS.ADS2 to ADS.ADS0 Bits = 001B)
ANI1 Data 1 Data 2
A/D conversion
Data 1 (ANI1)
Data 2 (ANI1)
ADCR
Data 1 (ANI1)
Data 2 (ANI1)
INTAD
Conversion end Conversion start Set ADCS bit = 1
Conversion end Conversion start Set ADCS bit = 1
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(2) Scan mode In this mode, the analog signals specified by the ADS register and input from the ANI0 pin while the ADM.ADMD bit = 1 are sequentially selected and converted. When conversion of one analog input signal is complete, the conversion result is stored in the ADCR register and, at the same time, the A/D conversion end interrupt request signal (INTAD) is generated. The A/D conversion results of all the analog input signals are stored in the ADCR register. It is therefore recommended to save the contents of the ADCR register to RAM once A/D conversion of one analog input signal has been completed. In the hardware trigger mode (ADS.TRG bit = 1), the A/D converter waits for a trigger after it has completed A/D conversion of the analog signals specified by the ADS register and input from the ANI0 pin. If anything is written to the ADM, ADS, PFM, and PFT registers during conversion, A/D conversion is aborted. In the software trigger mode, A/D conversion is started from the beginning again. In the hardware trigger mode, the A/D converter waits for a trigger. Conversion starts again from the ANI0 pin. If the trigger is detected during conversion in hardware trigger mode, A/D conversion is aborted and started again from the beginning (ANI0 pin).
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Figure 13-5. Example of Scan Mode Operation Timing (ADS.ADS2 to ADS.ADS0 Bits = 011B)
(a) Timing example
ANI0 Data 1 ANI1 Data 2 Data 7 ANI2 Data 3 Data 5
Data 6
ANI3
Data 4
A/D conversion
Data 1 (ANI0)
Data 2 (ANI1)
Data 3 (ANI2)
Data 4 (ANI3)
ADCR
Data 1 (ANI0)
Data 2 (ANI1)
Data 3 (ANI2)
Data 4 (ANI3)
INTAD
Conversion end Conversion start Set ADCS bit = 1
(b) Block diagram
Analog input pin ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 A/D converter ADCR register ADCR
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13.5.4 Power fail detection function The conversion end interrupt request signal (INTAD) can be controlled as follows using the PFM and PFT registers. * If the PFM.PFEN bit = 0, the INTAD signal is generated each time conversion ends. * If the PFEN bit = 1 and the PFM.PFCM bit = 0, the conversion result (ADCRH register) and the value of the PFT register are compared when conversion ends, and the INTAD signal is generated only if ADCRH PFT. * If the PFEN and PFCM bits = 1, the conversion result and the value of the PFT register are compared when conversion ends, and the INTAD signal is generated only if ADCRH < PFT. * Because, when the PFEN bit = 1, the conversion result is overwritten after the INTAD signal has been generated, unless the conversion result is read by the time the next conversion ends, in some cases it may appear as if the actual operation differs from the operation described above (refer to Figure 13-6). Figure 13-6. Power Fail Detection Function (PFCM Bit = 0)
Conversion operation
ANI0
ANI0
ANI0
ANI0
ADCRH
80H
7FH
80H
PFT
80H
INTAD
Note
Note If reading is not performed during this interval, the conversion result changes to the next conversion result.
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13.5.5 Setting method The following describes how to set registers. (1) When using the A/D converter for A/D conversion <1> Set (1) the ADM.ADCS2 bit. <2> Select the channel and conversion time by setting the ADS.ADS2 to ADS.ADS0 bits and the ADM.ADHS1, ADM.ADHS0, and ADM.FR2 to ADM.FR0 bits. <3> Set (1) the ADM.ADCS bit. <4> Transfer the A/D conversion data to the ADCR register. <5> An interrupt request signal (INTAD) is generated. <6> Change the channel by setting the ADS2 to ADS0 bits. <7> Transfer the A/D conversion data to the ADCR register. <8> The INTAD signal is generated. <9> Clear (0) the ADCS bit. <10> Clear (0) the ADCS2 bit. Cautions 1. The time taken from <1> to <3> must be 1 s (high-speed mode) or 14 s (normal mode) or longer. 2. Steps <1> and <2> may be reversed. 3. Step <1> may be omitted. However, if omitted, do not use the first conversion result after <3>. 4. The time taken from <4> to <7> is different from the conversion time set by the ADHS1, ADHS0, and FR2 to FR0 bits. The time taken for <6> and <7> is the conversion time set by the ADHS1, ADHS0, and FR2 to FR0 bits. (2) When using the A/D converter for the power fail detection function <1> Set (1) the PFM.PFEN bit. <2> Set the power fail comparison conditions by using the PFM.PFCM bit. <3> Set (1) the ADM.ADCS2 bit. <4> Select the channel and conversion time by setting the ADS.ADS2 to ADS.ADS0 bits and the ADM.ADHS1, ADM.ADHS0, and ADM.FR2 to ADM.FR0 bits. <5> Set the threshold value in the PFT register. <6> Set (1) the ADM.ADCS bit. <7> Transfer the A/D conversion data to the ADCR register. <8> Compare the ADCRH register with the PFT register. An interrupt request signal (INTAD) is generated when the conditions match. <9> Change the channel by setting the ADS2 to ADS0 bits. <10> Transfer the A/D conversion data to the ADCR register. <11> The ADCRH register is compared with the PFT register. When the conditions match, an INTAD signal is generated. <12> Clear (0) the ADCS bit. <13> Clear (0) the ADCS2 bit. Remark If the operation of the power fail detection function is enabled, all the A/D conversion results are compared, regardless of whether the select mode or scan mode is set.
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13.6 Cautions
(1) Power consumption in standby mode The operation of the A/D converter stops in the standby mode. At this time, the power consumption can be reduced by stopping the conversion operation (the ADM.ADCS bit = 0). Figure 13-7 shows an example of how to reduce the power consumption in the standby mode. Figure 13-7. Example of How to Reduce Power Consumption in Standby Mode
AVREF0
P-ch
ADCS
Series resistor string AVSS
(2) Input range of ANI0 to ANI7 pins Use the A/D converter with the ANI0 to ANI7 pin input voltages within the specified range. If a voltage of AVREF0 or higher or AVSS or lower (even if within the absolute maximum ratings) is input to these pins, the conversion value of the channel is undefined. Also, this may affect the conversion value of other channels. (3) Conflicting operations (a) Conflict between writing to the ADCR register and reading from ADCR register upon the end of conversion Reading the ADCR register takes precedence. After the register has been read, a new conversion result is written to the ADCR register. (b) Conflict between writing to the ADCR register and writing to the ADM register or writing to the ADS register upon the end of conversion Writing to the ADM register or ADS register takes precedence. The ADCR register is not written, and neither is the conversion end interrupt request signal (INTAD) generated.
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(4) Measures against noise To keep a resolution of 10 bits, be aware of noise on the AVREF0 and ANI0 to ANI7 pins. The higher the output impedance of the analog input source, the greater the effect of noise. connect external capacitors as shown in Figure 13-8 to reduce noise. Figure 13-8. Handling of Analog Input Pins Therefore, it is recommended to
If noise of AVREF0 or higher or AVSS or lower could be generated, clamp with a diode with a small VF (0.3 V or lower). Reference voltage input
AVREF0
ANI0 to ANI7 C 0.1 F
AVSS VSS
(5) ANI0/P70 to ANI7/P77 pins The analog input pins (ANI0 to ANI7) function alternately as input port pins (P70 to P77). When performing A/D conversion by selecting any of the ANI0 to ANI7 pins, do not execute an input instruction to port 7 during conversion. This may decrease the conversion resolution. If digital pulses are applied to the pin adjacent to the pin subject to A/D conversion, the value of the A/D conversion may differ from the expected value because of coupling noise. Therefore, do not apply pulses to the pin adjacent to the pin subject to A/D conversion. (6) Input impedance of AVREF0 pin A series resistor string of tens of k is connected between the AVREF0 pin and AVSS pin. Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the AVREF0 pin and AVSS pin, resulting in a large reference voltage error.
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(7) Interrupt request flag (ADIC.ADIF bit) Even when the ADS register is changed, the ADIF bit is not cleared (0). Therefore, if the analog input pin is changed during A/D conversion, the ADIF bit may be set (1) because A/D conversion of the previous analog input pin ends immediately before the ADS register is rewritten. In a such case, note that if the ADIF bit is read immediately after the ADS register has been rewritten, the ADIF bit is set (1) even though A/D conversion of the analog input pin after the change has not been completed. When stopping A/D conversion once and resuming it, clear the ADIF bit (0) before resuming A/D conversion. Figure 13-9. A/D Conversion End Interrupt Request Occurrence Timing
ADS rewrite (ANIn conversion start)
ADS rewrite (ANIm conversion start)
ANIm conversion is not complete even though ADIF is set.
A/D conversion
ANIn
ANIn
ANIm
ANIm
ADCR
ANIn
ANIn
ANIm
ANIm
INTAD
Remark
n = 0 to 7 m = 0 to 7
(8) Conversion results immediately after A/D conversion start If the ADM.ADCS bit is set to 1 within 1 s (high-speed mode) or 14 s (normal mode) after the ADM.ADCS2 bit has been set to 1, or if the ADCS bit is set to 1 with the ADCS2 bit cleared to 0, the converted value immediately after the A/D conversion operation has started may not satisfy the rating. Take appropriate measures such as polling the A/D conversion end interrupt request signal (INTAD) and discarding the first conversion result. (9) Reading A/D conversion result register (ADCR) When the ADM or ADS register has been written, the contents of the ADCR register may become undefined. When the conversion operation is complete, read the conversion results before writing to the ADM or ADS register. A correct conversion result may not be able to be read at a timing other than the above. Accessing the ADCR and ADCRH registers is prohibited when the CPU operates with the subclock and the main clock oscillation (fX) is stopped. For details, refer to 3.4.8 (1) (b) Access to special on-chip peripheral I/O register.
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(10) A/D converter sampling time and A/D conversion start delay time The A/D converter sampling time differs depending on the set value of the ADM register. A delay time exists until actual sampling is started after A/D converter operation is enabled. When using a set in which the A/D conversion time must be strictly observed, care is required for the contents shown in Figure 13-10 and Table 13-4. Figure 13-10. Timing of A/D Converter Sampling and A/D Conversion Start Delay
ADCS bit 1 or ADS register rewrite
ADCS
Sampling timing
INTAD
Wait period Register Sampling write time response time/trigger response time
Sampling time Conversion time Conversion time
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Table 13-4. A/D Converter Conversion Time
ADHS1 ADHS0 FR2 FR1 FR0 Conversion Time Sampling Time Register Write Response Time MIN. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 288/fXX 240/fXX 192/fXX 144/fXX 120/fXX 96/fXX 96/fXX 72/fXX 48/fXX 24/fXX 224/fXX 168/fXX 112/fXX 56/fXX 72/fXX 54/fXX 36/fXX 18/fXX Setting prohibited 176/fXX 176/fXX 132/fXX 88/fXX 88/fXX 48/fXX 48/fXX 36/fXX 24/fXX 12/fXX 176/fXX 132/fXX 88/fXX 44/fXX 24/fXX 18/fXX 12/fXX 6/fXX - 11/fXX 11/fXX 10/fXX 9/fXX 9/fXX 11/fXX 11/fXX 10/fXX 9/fXX 8/fXX 11/fXX 10/fXX 9/fXX 8/fXX 11/fXX 10/fXX 9/fXX 8/fXX -
Note
Trigger Response Time MIN. 7/fXX 7/fXX 6/fXX 5/fXX 5/fXX 7/fXX 7/fXX 6/fXX 5/fXX 4/fXX 7/fXX 6/fXX 5/fXX 4/fXX 7/fXX 6/fXX 5/fXX 4/fXX -
Note
MAX. 12/fXX 12/fXX 11/fXX 10/fXX 10/fXX 12/fXX 12/fXX 11/fXX 10/fXX 9/fXX 12/fXX 11/fXX 10/fXX 9/fXX 12/fXX 11/fXX 10/fXX 9/fXX -
MAX. 8/fXX 8/fXX 7/fXX 6/fXX 6/fXX 8/fXX 8/fXX 7/fXX 6/fXX 5/fXX 8/fXX 7/fXX 6/fXX 5/fXX 8/fXX 7/fXX 6/fXX 5/fXX -
Other than above
Note Each response time is the time after the wait period. For the wait function, refer to 3.4.8 (1) (b) Access to special on-chip peripheral I/O register. Remark fXX: Main clock frequency
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(11) Internal equivalent circuit The following shows the equivalent circuit of the analog input block. Figure 13-11. Internal Equivalent Circuit of ANIn Pin
RIN ANIn COUT CIN
AVREF0 4.5 V 2.7 V
RIN 3 k 60 k
COUT 8 pF 8 pF
CIN 15 pF 15 pF
Remarks 1. The above values are reference values. 2. n = 0 to 7
(12) Variation of A/D conversion results The results of the A/D conversion may vary depending on the fluctuation of the supply voltage, or may be affected by noise. To reduce the variation, take counteractive measures with the program such as averaging the A/D conversion results. (13) A/D conversion result hysteresis characteristics The successive approximation type A/D converter holds the analog input voltage in the internal sample & hold capacitor and then performs A/D conversion. After the A/D conversion has finished, the analog input voltage remains in the internal sample & hold capacitor. As a result, the following phenomena may occur. * When the same channel is used for A/D conversions, if the voltage is higher or lower than the previous A/D conversion, then hysteresis characteristics may appear where the conversion result is affected by the previous value. Thus, even if the conversion is performed at the same potential, the result may vary. * When switching the analog input channel, hysteresis characteristics may appear where the conversion result is affected by the previous channel value. This is because one A/D converter is used for the A/D conversions. Thus, even if the conversion is performed at the same potential, the result may vary. Therefore, to obtain more accurate conversion result, perform A/D conversion twice successively for the same channel, and discard the first conversion result.
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13.7 How to Read A/D Converter Characteristics Table
Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1 LSB (Least Significant Bit). The percentage of 1 LSB with respect to the full scale is expressed by %FSR (Full Scale Range). %FSR indicates the ratio of analog input voltage that can be converted as a percentage, and is always represented by the following formula regardless of the resolution. 1 %FSR = (Max. value of analog input voltage that can be converted - Min. value of analog input voltage that can be converted)/100 = (AVREF0 - 0)/100 = AVREF0/100 1 LSB is as follows when the resolution is 10 bits. 1 LSB = 1/210 = 1/1024 = 0.098 %FSR Accuracy has no relation to resolution, but is determined by overall error. (2) Overall error This shows the maximum error value between the actual measured value and the theoretical value. Zero-scale error, full-scale error, linearity error and errors that are combinations of these express the overall error. Note that the quantization error is not included in the overall error in the characteristics table. Figure 13-12. Overall Error
1......1
Ideal line
Digital output
Overall error
0......0 0 Analog input AVREF0
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(3) Quantization error When analog values are converted to digital values, a 1/2 LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of 1/2 LSB is converted to the same digital code, so a quantization error cannot be avoided. Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. Figure 13-13. Quantization Error
1......1
Digital output
1/2 LSB
Quantization error 1/2 LSB
0......0 0 Analog input AVREF0
(4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2 LSB) when the digital output changes from 0......000 to 0......001. Figure 13-14. Zero-Scale Error
111
Digital output (Lower 3 bits)
Ideal line 100 Zero-scale error 011
010 001 000 -1 0 1 2 3 AVREF0 Analog input (LSB)
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(5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (full scale - 3/2 LSB) when the digital output changes from 1......110 to 1......111. Figure 13-15. Full-Scale Error
Full-scale error
Digital output (Lower 3 bits)
111 100 011 010
000 0 AVREF0-3 AVREF0-2 AVREF0-1 AVREF0 Analog input (LSB)
(6) Differential linearity error While the ideal width of code output is 1 LSB, this indicates the difference between the actual measurement value and the ideal value. This indicates the basic characteristics of the A/D conversion when the voltage applied to the analog input pins of the same channel is consistently increased bit by bit from AVSS to AVREF0. When the input voltage is increased or decreased, or when two or more channels are used, refer to 13.7 (2) Overall error. Figure 13-16. Differential Linearity Error
1......1 Ideal 1 LSB width
Digital output
Differential linearity error 0......0 0 Analog input AVREF0
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(7) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. Figure 13-17. Integral Linearity Error
1......1 Ideal line
Digital output
0......0 0
Integral linearity error AVREF0 Analog input
(8) Conversion time This expresses the time from when the analog input voltage was applied to the time when the digital output was obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Figure 13-18. Sampling Time
Sampling time
Conversion time
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In the V850ES/KE2, two channels of asynchronous serial interface (UART) are provided.
14.1 Features
* Maximum transfer speed: 312.5 kbps * Full-duplex communications On-chip RXBn register On-chip TXBn register * Two-pin configurationNote TXDn: Transmit data output pin RXDn: Receive data input pin * Reception error detection functions * Parity error * Framing error * Overrun error * Interrupt sources: 3 types * Reception error interrupt request signal (INTSREn): * Reception completion interrupt request signal (INTSRn): Interrupt is generated according to the logical OR of the three types of reception errors Interrupt is generated when receive data is transferred from the receive shift register to the RXBn register after serial transfer is completed during a reception enabled state * Transmission completion interrupt request signal (INTSTn): Interrupt is generated when the serial transmission of transmit data (8 or 7 bits) from the transmit shift register is completed * Character length: 7 or 8 bits * Parity functions: Odd, even, 0, or none * Transmission stop bits: 1 or 2 bits * On-chip dedicated baud rate generator Note The ASCK0 pin (external clock input) is available only for UART0.
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14.2 Configuration
Table 14-1. Configuration of UARTn
Item Registers Receive buffer register n (RXBn) Transmit buffer register n (TXBn) Receive shift register Transmit shift register Asynchronous serial interface mode register n (ASIMM) Asynchronous serial interface status register n (ASISn) Asynchronous serial interface transmit status register n (ASIFn) Other Reception control parity check Addition of transmission control parity Configuration
Remark
n = 0, 1
Figure 14-1 shows the configuration of UARTn. (1) Asynchronous serial interface mode register n (ASIMn) The ASIMn register is an 8-bit register for specifying the operation of UARTn. (2) Asynchronous serial interface status register n (ASISn) The ASISn register consists of a set of flags that indicate the error contents when a reception error occurs. The various reception error flags are set (1) when a reception error occurs and are cleared (0) when the ASISn register is read. (3) Asynchronous serial interface transmit status register n (ASIFn) The ASIFn register is an 8-bit register that indicates the status when a transmit operation is performed. This register consists of a transmit buffer data flag, which indicates the hold status of the TXBn register data, and the transmit shift register data flag, which indicates whether transmission is in progress. (4) Reception control parity check The receive operation is controlled according to the contents set in the ASIMn register. A check for parity errors is also performed during a receive operation, and if an error is detected, a value corresponding to the error contents is set in the ASISn register. (5) Receive shift register This is a shift register that converts the serial data that was input to the RXDn pin to parallel data. One byte of data is received, and if a stop bit is detected, the receive data is transferred to the RXBn register. This register cannot be directly manipulated. (6) Receive buffer register n (RXBn) The RXBn register is an 8-bit buffer register for holding receive data. When 7 characters are received, 0 is stored in the MSB. During a reception enabled state, receive data is transferred from the receive shift register to the RXBn register, synchronized with the end of the shift-in processing of one frame. Also, the reception completion interrupt request signal (INTSRn) is generated by the transfer of data to the RXBn register.
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(7) Transmit shift register This is a shift register that converts the parallel data that was transferred from the TXBn register to serial data. When one byte of data is transferred from the TXBn register, the shift register data is output from the TXDn pin. The transmission completion interrupt request signal (INTSTn) is generated synchronized with the completion of transmission of one frame. This register cannot be directly manipulated. (8) Transmit buffer register n (TXBn) The TXBn register is an 8-bit buffer for transmit data. A transmit operation is started by writing transmit data to the TXBn register. (9) Addition of transmission control parity A transmit operation is controlled by adding a start bit, parity bit, or stop bit to the data that is written to the TXBn register, according to the contents that were set in the ASIMn register. Figure 14-1. Block Diagram of UARTn
Internal bus
Asynchronous serial interface mode register n (ASIMn)
Receive buffer register n (RXBn)
Transmit buffer register n (TXBn)
RXDn TXDn
Receive shift register
Transmit shift register
Reception control parity check Parity Framing Overrun
Addition of transmission control parity
INTSTn INTSRn
INTSREn Baud rate generator n
Remark
For the configuration of the baud rate generator, refer to Figure 14-12.
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14.3 Registers
(1) Asynchronous serial interface mode register n (ASIMn) The ASIMn register is an 8-bit register that controls the UARTn transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 01H. Cautions 1. When using UARTn, be sure to set the external pins related to UARTn functions to the control made before setting the CKSRn and BRGCn registers, and then set the UARTEn bit to 1. Then set the other bits. 2. Set the UARTEn and RXEn bits to 1 while a high level is input to the RXDn pin. If these bits are set to 1 while a low level is input to the RXDn pin, reception will be started. (1/2)
After reset: 01H <7> ASIMn (n = 0, 1) UARTEn R/W <6> TXEn Address: ASIM0 FFFFFA00H, ASIM1 FFFFFA10H <5> RXEn 4 PSn1 3 PSn0 2 CLn 1 SLn 0 ISRMn
UARTEn 0 1 Stop clock supply to UARTn. Supply clock to UARTn.
Control of operating clock
* If the UARTEn bit is cleared to 0, UARTn is asynchronously reset
Note
.
* If the UARTEn bit = 0, UARTn is reset. To operate UARTn, first set the UARTEn bit to 1. * If the UARTEn bit is cleared from 1 to 0, all the registers of UARTn are initialized. To set the UARTEn bit to 1 again, be sure to re-set the registers of UARTn.
The output of the TXDn pin goes high when transmission is disabled, regardless of the setting of the UARTEn bit.
TXEn 0 1 Disable transmission Enable transmission
Transmission enable/disable
* Set the TXEn bit to 1 after setting the UARTEn bit to 1 at startup. Clear the UARTEn bit to 0 after clearing the TXEn bit to 0 to stop. * To initialize the transmission unit, clear (0) the TXEn bit, and after letting 2 Clock cycles (base clock) elapse, set (1) the TXEn bit again. If the TXEn bit is not set again, initialization may not be successful. (For details about the base clock, refer to 14.6.1 (1) Base clock.)
Note The ASISn, ASIFn, and RXBn registers are reset.
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(2/2)
RXEn 0 1 Disable reception Enable reception
Note
Reception enable/disable
* Set the RXEn bit to 1 after setting the UARTEn bit to 1 at startup. Clear the UARTEn bit to 0 after clearing the RXEn bit to 0 to stop. * To initialize the reception unit status, clear (0) the RXEn bit, and after letting 2 Clock cycles (base clock) elapse, set (1) the RXEn bit again. If the RXEn bit is not set again, initialization may not be successful. (For details about the base clock, refer to 14.6.1 (1) Base clock.)
PSn1 0 0 1 1
PSn0 0 1 0 1
Transmit operation Don't output parity bit Output 0 parity Output odd parity Output even parity
Receive operation Receive with no parity Receive as 0 parity Judge as odd parity Judge as even parity
* To overwrite the PSn1 and PSn0 bits, first clear (0) the TXEn and RXEn bits. * If "0 parity" is selected for reception, no parity judgment is performed. Therefore, no error interrupt is generated because the ASISn.PEn bit is not set.
CLn 0 1 7 bits 8 bits
Specification of character length of 1 frame of transmit/receive data
* To overwrite the CLn bit, first clear (0) the TXEn and RXEn bits.
SLn 0 1 1 bit 2 bits
Specification of stop bit length of transmit data
* To overwrite the SLn bit, first clear (0) the TXEn bit. * Since reception is always done with a stop bit length of 1, the SLn bit setting does not affect receive operations.
ISRMn 0
Enable/disable of generation of reception completion interrupt request signals when an error occurs Generate a reception error interrupt request signal (INTSREn) as an interrupt when an error occurs. In this case, no reception completion interrupt request signal (INTSRn) is generated.
1
Generate a reception completion interrupt request signal (INTSRn) as an interrupt when an error occurs. In this case, no reception error interrupt request signal (INTSREn) is generated.
* To overwrite the ISRMn bit, first clear (0) the RXEn bit.
Note When reception is disabled, the receive shift register does not detect a start bit. register are retained.
No shift-in
processing or transfer processing to the RXBn register is performed, and the contents of the RXBn When reception is enabled, the receive shift operation starts, synchronized with the detection of the start bit, and when the reception of one frame is completed, the contents of the receive shift register are transferred to the RXBn register. A reception completion interrupt request signal (INTSRn) is also generated in synchronization with the transfer to the RXBn register.
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(2) Asynchronous serial interface status register n (ASISn) The ASISn register, which consists of 3 error flag bits (PEn, FEn and OVEn), indicates the error status when UARTn reception is complete. The ASISn register is cleared to 00H by a read operation. When a reception error occurs, the RXBn register should be read and the error flag should be cleared after the ASISn register is read. This register is read-only in 8-bit units. Reset sets this register to 00H. Cautions 1. When the ASIMn.UARTEn bit or ASIMn.RXEn bit is cleared to 0, or when the ASISn register is read, the PEn, FEn, and OVEn bits are cleared (0). 2. Operation using a bit manipulation instruction is prohibited. 3. When the main clock is stopped and the CPU is operating on the subclock, do not access the ASISn register. For details, refer to 3.4.8 (1) (b).
After reset: 00H 7 ASISn (n = 0, 1) 0
R 6 0
Address: ASIS0 FFFFFA03H, ASIS1 FFFFFA13H 5 0 4 0 3 0 2 PEn 1 FEn 0 OVEn
PEn 0 1
Status flag indicating a parity error When the UARTEn or RXEn bit is cleared to 0, or after the ASISn register has been read When reception was completed, the receive data parity did not match the parity bit
* The operation of the PEn bit differs according to the settings of the ASIMn.PSn1 and ASIMn.PSn0 bits.
FEn 0 1
Status flag indicating framing error When the UARTEn or RXEn bit is cleared to 0, or after the ASISn register has been read When reception was completed, no stop bit was detected
* For receive data stop bits, only the first bit is checked regardless of the stop bit length.
OVEn 0 1
Status flag indicating an overrun error When the UARTEn or RXEn bit is cleared to 0, or after the ASISn register has been read. UARTn completed the next receive operation before reading receive data of the RXBn register.
* When an overrun error occurs, the next receive data value is not written to the RXBn register and the data is discarded.
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(3) Asynchronous serial interface transmit status register n (ASIFn) The ASIFn register, which consists of 2 status flag bits, indicates the status during transmission. By writing the next data to the TXBn register after data is transferred from the TXBn register to the transmit shift register, transmit operations can be performed continuously without suspension even during an interrupt interval. When transmission is performed continuously, data should be written after referencing the TXBFn bit to prevent writing to the TXBn register by mistake. This register is read-only in 8-bit or 1-bit units. Reset sets this register to 00H.
After reset: 00H 7 ASIFn (n = 0, 1) 0
R 6 0
Address: ASIF0 FFFFFA05H, ASIF1 FFFFFA15H 5 0 4 0 3 0 2 0 <1> TXBFn <0> TXSFn
TXBFn 0
Transmission buffer data flag Data to be transferred next to TXBn register does not exist (When the ASIMn.UARTEn or ASIMn.TXEn bit is cleared to 0, or when data has been transferred to the transmission shift register)
1
Data to be transferred next exists in TXBn register (Data exists in TXBn register when the TXBn register has been written to)
* When transmission is performed continuously, data should be written to the TXBn register after confirming that this flag is 0. If writing to TXBn register is performed when this flag is 1, transmit data cannot be guaranteed.
TXSFn 0
Transmit shift register data flag (indicates the transmission status of UARTn) Initial status or a waiting transmission (When the UARTEn or TXEn bit is cleared to 0, or when following transmission completion, the next data transfer from the TXBn register is not performed)
1
Transmission in progress (When data has been transferred from the TXBn register)
* When the transmission unit is initialized, initialization should be executed after confirming that this flag is 0 following the occurrence of a transmission completion interrupt request signal (INTSTn). performed when this flag is 1, transmit data cannot be guaranteed. If initialization is
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(4) Receive buffer register n (RXBn) The RXBn register is an 8-bit buffer register for storing parallel data that had been converted by the receive shift register. When reception is enabled (ASIMn.RXEn bit = 1), receive data is transferred from the receive shift register to the RXBn register, synchronized with the completion of the shift-in processing of one frame. Also, a reception completion interrupt request signal (INTSRn) is generated by the transfer to the RXBn register. information about the timing for generating this interrupt request, refer to 14.5.4 Receive operation. If reception is disabled (ASIMn.RXEn bit = 0), the contents of the RXBn register are retained, and no processing is performed for transferring data to the RXBn register even when the shift-in processing of one frame is completed. Also, the INTSRn signal is not generated. When 7 bits is specified for the data length, bits 6 to 0 of the RXBn register are transferred for the receive data and the MSB (bit 7) is always 0. However, if an overrun error (ASISn.OVEn bit = 1) occurs, the receive data at that time is not transferred to the RXBn register. The RXBn register becomes FFH when a reset is input or ASIMn.UARTEn bit = 0. This register is read-only in 8-bit units. For
After reset: FFH 7 RXBn (n = 0, 1) RXBn7
R 6 RXBn6
Address: RXB0 FFFFFA02H, RXB1 FFFFFA12H 5 RXBn5 4 RXBn4 3 RXBn3 2 RXBn2 1 RXBn1 0 RXBn0
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(5) Transmit buffer register n (TXBn) The TXBn register is an 8-bit buffer register for setting transmit data. When transmission is enabled (ASIMn.TXEn bit = 1), the transmit operation is started by writing data to TXBn register. When transmission is disabled (TXEn bit = 0), even if data is written to TXBn register, the value is ignored. The TXBn register data is transferred to the transmit shift register, and a transmission completion interrupt request signal (INTSTn) is generated, synchronized with the completion of the transmission of one frame from the transmit shift register. For information about the timing for generating this interrupt request, refer to 14.5.2 Transmit operation. When ASIFn.TXBFn bit = 1, writing must not be performed to TXBn register. This register can be read or written in 8-bit units. Reset sets this register to FFH.
After reset: FFH 7 TXBn (n = 0, 1) TXBn7
R/W 6 TXBn6
Address: TXB0 FFFFFA04H, TXB1 FFFFFA14H 5 TXBn5 4 TXBn4 3 TXBn3 2 TXBn2 1 TXBn1 0 TXBn0
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14.4 Interrupt Requests
The following three types of interrupt request signals are generated from UARTn. * Reception error interrupt request signal (INTSREn) * Reception completion interrupt request signal (INTSRn) * Transmission completion interrupt request signal (INTSTn) The default priorities among these three types of interrupt request signals are, from high to low, reception error interrupt, reception completion interrupt, and transmission completion interrupt. Table 14-2. Generated Interrupt Request Signals and Default Priorities
Interrupt Request Signal Reception error interrupt request signal (INTSREn) Reception completion interrupt request signal (INTSRn) Transmission completion interrupt request signal (INTSTn) Priority 1 2 3
(1) Reception error interrupt request signal (INTSREn) When reception is enabled, the INTSREn signal is generated according to the logical OR of the three types of reception errors explained for the ASISn register. Whether the INTSREn signal or the INTSRn signal is generated when an error occurs can be specified according to the ASIMn.ISRMn bit. When reception is disabled, the INTSREn signal is not generated. (2) Reception completion interrupt request signal (INTSRn) When reception is enabled, the INTSRn signal is generated when data is shifted in to the receive shift register and transferred to the RXBn register. The INTSRn signal can be generated in place of the INTSREn signal according to the ASIMn.ISRMn bit even when a reception error has occurred. When reception is disabled, the INTSRn signal is not generated. (3) Transmission completion interrupt request signal (INTSTn) The INTSTn signal is generated when one frame of transmit data containing 7-bit or 8-bit characters is shifted out from the transmit shift register.
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14.5 Operation
14.5.1 Data format Full-duplex serial data transmission and reception can be performed. The transmit/receive data format consists of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in Figure 14-2. The character bit length within one data frame, the type of parity, and the stop bit length are specified according to the ASIMn register. Also, data is transferred LSB first. Figure 14-2. Format of UARTn Transmit/Receive Data
1 data frame
Start bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity bit
Stop bits
Character bits
* Start bit *** 1 bit * Character bits *** 7 bits or 8 bits * Parity bit *** Even parity, odd parity, 0 parity, or no parity * Stop bits *** 1 bit or 2 bits
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14.5.2 Transmit operation When the ASIMn.UARTEn bit is set to 1, a high level is output from the TXDn pin. Then, when the ASIMn.TXEn bit is set to 1, transmission is enabled, and the transmit operation is started by writing transmit data to the TXBn register. (1) Transmission enabled state This state is set by the TXEn bit. * TXEn bit = 1: Transmission enabled state * TXEn bit = 0: Transmission disabled state Since UARTn does not have a CTS (transmission enabled signal) input pin, a port should be used to confirm whether the destination is in a reception enabled state. (2) Starting a transmit operation In the transmission enabled state, a transmit operation is started by writing transmit data to the TXBn register. When a transmit operation is started, the data in the TXBn register is transferred to the transmit shift register. Then, the transmit shift register outputs data to the TXDn pin (the transmit data is transferred sequentially starting with the start bit). The start bit, parity bit, and stop bits are added automatically. (3) Transmission interrupt When the transmit shift register becomes empty, a transmission completion interrupt request signal (INTSTn) is generated. The timing for generating the INTSTn signal differs according to the specification of the stop bit length. The INTSTn signal is generated at the same time that the last stop bit is output. If the data to be transmitted next has not been written to the TXBn register, the transmit operation is suspended. Caution Normally, when the transmit shift register becomes empty, the INTSTn signal is generated. However, the INTSTn signal is not generated if the transmit shift register becomes empty due to reset.
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Figure 14-3. UARTn Transmission Completion Interrupt Timing
(a) Stop bit length: 1
TXDn (output)
Start
D0
D1
D2
D6
D7
Parity
Stop
INTSTn (output)
(b) Stop bit length: 2
TXDn (output)
Start
D0
D1
D2
D6
D7
Parity
Stop
INTSTn (output)
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14.5.3 Continuous transmission operation UARTn can write the next transmit data to the TXBn register at the timing that the transmit shift register starts the shift operation. This enables an efficient transmission rate to be realized by continuously transmitting data even during the transmission completion interrupt service after the transmission of one data frame. In addition, reading the ASIFn.TXSFn bit after the occurrence of a transmission completion interrupt request signal (INTSTn) enables the TXBn register to be efficiently written twice (2 bytes) without waiting for the transmission of 1 data frame. When continuous transmission is performed, data should be written after referencing the ASIFn register to confirm the transmission status and whether or not data can be written to the TXBn register. Caution The values of the ASIF.TXBFn and ASIF.TXSFn bits change 10 11 01 in continuous transmission. Therefore, do not confirm the status based on the combination of the TXBFn and TXSFn bits. Read only the TXBFn bit during continuous transmission.
TXBFn 0 1 Whether or Not Writing to TXBn Register Is Enabled Writing is enabled Writing is not enabled
Caution
When transmission is performed continuously, write the first transmit data (first byte) to the TXBn register and confirm that the TXBFn bit is 0, and then write the next transmit data (second byte) to TXBn register. If writing to the TXBn register is performed when the TXBFn bit is 1, transmit data cannot be guaranteed.
The communication status can be confirmed by referring to the TXSFn bit.
TXSFn 0 1 Transmission is completed. Under transmission. Transmission Status
Cautions 1. When initializing the transmission unit when continuous transmission is completed, confirm that the TXSFn bit is 0 after the occurrence of the transmission completion interrupt, and then execute initialization. If initialization is performed when the TXSFn bit is 1, transmit data cannot be guaranteed. 2. While transmission is being performed continuously, an overrun error may occur if the next transmission is completed before the INTSTn interrupt servicing following the transmission of 1 data frame is executed. An overrun error can be detected by embedding a program that can count the number of transmit data and referencing TXSFn bit.
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Figure 14-4. Continuous Transmission Processing Flow
Set registers
Write transmit data to TXBn register
No
When reading ASIFn register, TXBFn = 0? Yes Write second byte transmit data to TXBn register
Interrupt occurrence
Required number of transfers performed? No
Yes
No
When reading ASIFn register, TXSFn = 1? Yes
When reading ASIFn register, TXSFn = 0? Yes
No
Write transmit data to TXBn register
Wait for interrupt
End of transmission processing
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(1) Starting procedure The procedure to start continuous transmission is shown below. Figure 14-5. Continuous Transmission Starting Procedure
TXDn (output) <1> INTSTn (output)
Start bit <2>
Data (1)
Stop bit <3>
Start bit <4>
Data (2)
Stop bit <5>
TXBn register
FFH
Data (1)
Data (2)
Data (3)
TXSn register ASIFn register (TXBFn, TXSFn bits)
FFH 10 11Note
Data (1)
Data (2)
Data (3)
00
01
11
01
11
01
11
Note Refer to 14.8 Cautions (2).
Transmission Starting Procedure
Internal Operation
ASIFn Register TXBFn TXSFn 0 0 1
Note
* Set transmission mode * Write data (1)
<1> Start transmission unit
0 1
<2> Generate start bit
1 0
1 1 1 1
Start data (1) transmission * Read ASIFn register (confirm that TXBFn bit = 0) * Write data (2) <> <3> INTSTn interrupt occurs * Read ASIFn register (confirm that TXBFn bit = 0) * Write data (3) <4> Generate start bit Start data (2) transmission <> <5> INTSTn interrupt occurs * Read ASIFn register (confirm that TXBFn bit = 0) * Write data (4)
0 0 1
0 0 1
1 1 1
0 0 1
1 1 1
Note Refer to 14.7 Cautions (2).
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(2) Ending procedure The procedure for ending continuous transmission is shown below. Figure 14-6. Continuous Transmission End Procedure
TXDn (output) <6> INTSTn (output) <7>
Start bit <8>
Data (m - 1)
Stop bit <9>
Start bit <10>
Data (m) <11>
Stop bit
TXBn register
Data (m - 1) Data (m - 1)
Data (m)
TXSn register ASIFn register (TXBFn, TXSFn bits)
Data (m)
FFH
11
01
11
01
00
UARTEn bit or TXEn bit
Transmission End Procedure
Internal Operation
ASIFn Register TXBFn TXSFn 1
<6> Transmission of data (m - 2) is in progress <7> INTSTn interrupt occurs * Read ASIFn register (confirm that TXBFn bit = 0) * Write data (m) <8> Generate start bit Start data (m - 1) transmission <> <9> INTSTn interrupt occurs * Read ASIFn register (confirm that TXSFn bit = 1) There is no write data <10> Generate start bit Start data (m) transmission <> <11> Generate INTSTn interrupt * Read ASIFn register (confirm that TXSFn bit = 0) * Clear (0) the UARTEn bit or TXEn bit Initialize internal circuits
1
0 0 1
1 1 1
0 0
1 1
0 0
0 0
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14.5.4 Receive operation The awaiting reception state is set by setting the ASIMn.UARTEn bit to 1 and then setting the ASIMn.RXEn bit to 1. To start the receive operation, start sampling at the falling edge when the falling of the RXDn pin is detected. If the RXDn pin is low level at a start bit sampling point, the start bit is recognized. When the receive operation begins, serial data is stored sequentially in the receive shift register according to the baud rate that was set. A reception completion interrupt request signal (INTSRn) is generated each time the reception of one frame of data is completed. Normally, the receive data is transferred from the RXBn register to memory by this interrupt servicing. (1) Reception enabled state The receive operation is set to the reception enabled state by setting the RXEn bit to 1. * RXEn bit = 1: Reception enabled state * RXEn bit = 0: Reception disabled state In receive disabled state, the reception hardware stands by in the initial state. At this time, the contents of the RXBn register are retained, and no reception completion interrupt or reception error interrupt is generated. (2) Starting a receive operation A receive operation is started by the detection of a start bit. The RXDn pin is sampled using the serial clock from baud rate generator n (BRGn). (3) Reception completion interrupt When the RXEn bit = 1 and the reception of one frame of data is completed (the stop bit is detected), the INTSRn signal is generated and the receive data within the receive shift register is transferred to the RXBn register at the same time. Also, if an overrun error (ASISn.OVEn bit = 1) occurs, the receive data at that time is not transferred to the RXBn register, and either the INTSRn signal or a reception error interrupt request signal (INTSREn) is generated according to the ASIMn.ISRMn bit setting. Even if a parity error (ASISn.PEn bit = 1) or framing error (ASISn.FEn bit = 1) occurs during a reception operation, the receive operation continues until stop bit is received, and after reception is completed, either the INTSRn signal or the INTSREn signal is generated according to the ISRMn bit setting (the receive data within the receive shift register is transferred to the RXBn register). If the RXEn bit is cleared (0) during a receive operation, the receive operation is immediately stopped. The contents of the RXBn register and the ASISn register at this time do not change, and the INTSRn signal or the INTSREn signal is not generated. The INTSRn signal or the INTSREn signal is not generated when the RXEn bit = 0 (reception is disabled).
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Figure 14-7. UARTn Reception Completion Interrupt Timing
RXDn (input)
Start
D0
D1
D2
D6
D7
Parity
Stop
INTSRn (output)
RXBn register
Cautions 1. Be sure to read the RXBn register even when a reception error occurs. If the RXBn register is not read, an overrun error will occur at the next data reception and the reception error status will continue infinitely. 2. Reception is always performed assuming a stop bit length of 1. A second stop bit is ignored.
14.5.5 Reception error The three types of errors that can occur during a receive operation are a parity error, framing error, and overrun error. As a result of data reception, the various flags of the ASISn register are set (1), and a reception error interrupt request signal (INTSREn) or a reception completion interrupt request signal (INTSRn) is generated at the same time. The ASIMn.ISRMn bit specifies whether the INTSREn signal or the INTSRn signal is generated. The type of error that occurred during reception can be detected by reading the contents of the ASISn register during the INTSREn or INTSRn interrupt servicing. The contents of the ASISn register are cleared (0) by reading the ASISn register. Table 14-3. Reception Error Causes
Error Flag PEn Reception Error Parity error Cause The parity specification during transmission did not match the parity of the reception data No stop bit was detected The reception of the next data was completed before data was read from the RXBn register
FEn OVEn
Framing error Overrun error
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(1) Separation of reception error interrupt request signal A reception error interrupt request signal can be separated from the INTSRn signal and generated as the INTSREn signal by clearing the ISRMn bit to 0. Figure 14-8. When Reception Error Interrupt Request Signal Is Separated from INTSRn Signal (ISRMn Bit = 0)
(a) No error occurs during reception
(b) An error occurs during reception
INTSRn signal (Reception completion interrupt) INTSREn signal (Reception error interrupt)
INTSRn signal (Reception completion interrupt) INTSREn signal (Reception error interrupt)
INTSRn does not occur
Figure 14-9. When Reception Error Interrupt Request Signal Is Included in INTSRn Signal (ISRMn Bit = 1)
(a) No error occurs during reception
(b) An error occurs during reception
INTSRn signal (Reception completion interrupt) INTSREn signal (Reception error interrupt)
INTSRn signal (Reception completion interrupt) INTSREn signal (Reception error interrupt)
INTSREn does not occur
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14.5.6 Parity types and corresponding operation A parity bit is used to detect a bit error in communication data. Normally, the same type of parity bit is used on the transmission and reception sides. (1) Even parity (i) During transmission The parity bit is controlled so that the number of bits with the value "1" within the transmit data including the parity bit is even. The parity bit value is as follows. * If the number of bits with the value "1" within the transmit data is odd: 1 * If the number of bits with the value "1" within the transmit data is even: 0 (ii) During reception The number of bits with the value "1" within the receive data including the parity bit is counted, and a parity error is generated if this number is odd. (2) Odd parity (i) During transmission In contrast to even parity, the parity bit is controlled so that the number of bits with the value "1" within the transmit data including the parity bit is odd. The parity bit value is as follows. * If the number of bits with the value "1" within the transmit data is odd: 0 * If the number of bits with the value "1" within the transmit data is even: 1 (ii) During reception The number of bits with the value "1" within the receive data including the parity bit is counted, and a parity error is generated if this number is even. (3) 0 parity During transmission the parity bit is set to "0" regardless of the transmit data. During reception, no parity bit check is performed. Therefore, no parity error is generated regardless of whether the parity bit is "0" or "1". (4) No parity No parity bit is added to the transmit data. During reception, the receive operation is performed as if there were no parity bit. Since there is no parity bit, no parity error is generated.
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14.5.7 Receive data noise filter The RXDn signal is sampled at the rising edge of the prescaler output base clock (fUCLK). If the same sampling value is obtained twice, the match detector output changes, and this output is sampled as input data. Therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (refer to Figure 14-11). Refer to 14.6.1 (1) Base clock regarding the base clock. Also, since the circuit is configured as shown in Figure 14-10, internal processing during a receive operation is delayed by up to 2 clocks according to the external signal status. Figure 14-10. Noise Filter Circuit
Base clock
fUCLK
RXDn
In
Q
Internal signal A
In LD_EN
Q
Internal signal B
Match detector
Figure 14-11. Timing of RXDn Signal Judged as Noise
Base clock
RXDn (input)
Internal signal A
Match
Mismatch (judged as noise)
Match
Mismatch (judged as noise)
Internal signal B
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14.6 Dedicated Baud Rate Generator n (BRGn)
A dedicated baud rate generator, which consists of a source clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception by UARTn. The dedicated baud rate generator output can be selected as the serial clock for each channel. Separate 8-bit counters exist for transmission and for reception. 14.6.1 Baud rate generator n (BRGn) configuration Figure 14-12. Configuration of Baud Rate Generator n (BRGn)
UARTEn
fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1,024 ASCK0Note 2 Match detector 1/2 Baud rate Selector fUCLKNote 1 8-bit counter UARTEn and TXEn bits (or RXEn bit)
CKSRn: TPSn3 to TPSn0
BRGCn: MDLn7 to MDLn0
Notes 1.
Set fUCLK so as to satisfy the following conditions. * VDD = 4.5 to 5.5 V: fUCLK 12 MHz * VDD = 2.7 to 4.5 V: fUCLK 6 MHz
2. Remark
ASCK0 pin input can be used only by UART0. fXX: Main clock frequency
fUCLK: Base clock
(1) Base clock When the ASIMn.UARTEn bit = 1, the clock selected according to the CKSRn.TPSn3 to CKSRn.TPSn0 bits is supplied to the transmission/reception unit. This clock is called the base clock (fUCLK). When the UARTEn bit = 0, fUCLK is fixed to low level.
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14.6.2 Serial clock generation A serial clock can be generated according to the settings of the CKSRn and BRGCn registers. The base clock to the 8-bit counter is selected by the CKSRn.TPSn3 to CKSRn.TPSn0 bits. The 8-bit counter divisor value can be set by the BRGCn.MDLn7 to BRGCn.MDLn0 bits. (1) Clock select register n (CKSRn) The CKSRn register is an 8-bit register for selecting the basic block using the TPSn3 to TPSn0 bits. The clock selected by the TPSn3 to TPSn0 bits becomes the base clock (fUCLK) of the transmission/reception module. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution Clear the ASIMn.UARTEn bit to 0 before rewriting the TPSn3 to TPSn0 bits.
After reset: 00H 7 CKSRn (n = 0, 1) 0
R/W 6 0
Address: CKSR0 FFFFFA06H, CKSR1 FFFFFA16H 5 0 4 0 3 TPSn3 2 TPSn2 1 TPSn1 0 TPSn0
TPSn3 0 0 0 0 0 0 0 0 1 1 1 1
TPSn2 0 0 0 0 1 1 1 1 0 0 0 0
TPSn1 0 0 1 1 0 0 1 1 0 0 1 1
TPSn0 0 1 0 1 0 1 0 1 0 1 0 1 fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1,024 External clock
Note 2
Base clock (fUCLK)
Note 1
(ASCK0 pin)
Other than above
Setting prohibited
Notes 1. Set fUCLK so as to satisfy the following conditions. * VDD = 4.5 to 5.5 V: fUCLK 12 MHz * VDD = 2.7 to 4.5 V: fUCLK 6 MHz 2. ASCK0 pin input clock can be used only by UART0. Setting of UART1 and UART2 is prohibited. Remark fXX: Main clock frequency
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(2) Baud rate generator control register n (BRGCn) The BRGCn register is an 8-bit register that controls the baud rate (serial transfer speed) of UARTn. This register can be read or written in 8-bit units. Reset sets this register to FFH. Caution If the MDLn7 to MDLn0 bits are to be overwritten, the ASIMn.TXEn and ASIMn.RXEn bits should be cleared to 0 first.
After reset: FFH 7 BRGCn (n = 0, 1) MDLn7
R/W 6 MDLn6
Address: BRGC0 FFFFFA07H, BRGC1 FFFFFA17H 5 MDLn5 4 MDLn4 3 MDLn3 2 MDLn2 1 MDLn1 0 MDLn0
MDLn7 MDLn6 MDLn5 MDLn4 MDLn3 MDLn2 MDLn1 MDLn0 Set value (k) 0 0 0 0 ... 0 0 0 0 ... 0 0 0 0 ... 0 0 0 0 ... 0 1 1 1 ... x 0 0 0 ... x 0 0 1 ... x 0 1 0 ... - 8 9 10 ...
Serial clock
Setting prohibited fUCLK/8 fUCLK/9 fUCLK/10 ... fUCLK/250 fUCLK/251 fUCLK/252 fUCLK/253 fUCLK/254 fUCLK/255
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
1 1 1 1 1 1
0 0 1 1 1 1
1 1 0 0 1 1
0 1 0 1 0 1
250 251 252 253 254 255
Remarks 1. fUCLK: Frequency [Hz] of base clock selected by CKSR0.TPSn3 to CKSR0.TPSn0 bits 2. k: Value set by MDLn7 to MDLn0 bits (k = 8, 9, 10, ..., 255) 3. The baud rate is the output clock for the 8-bit counter divided by 2. 4. x: don't care
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(3) Baud rate The baud rate is the value obtained by the following formula.
Baud rate [bps] =
fUCLK 2xk
fUCLK = Frequency [Hz] of base clock selected by CKSRn.TPSn3 to CKSRn.TPSn0 bits. k = Value set by BRGCn.MDLn7 to BRGCn.MDLn0 bits (k = 8, 9, 10, ..., 255)
(4) Baud rate error The baud rate error is obtained by the following formula.
Error (%) =
Actual baud rate (baud rate with error) Target baud rate (normal baud rate)
-1 x 100 [%]
Cautions 1. Make sure that the baud rate error during transmission does not exceed the allowable error of the reception destination. 2. Make sure that the baud rate error during reception is within the allowable baud rate range during reception, which is described in 14.6.4 during reception. Allowable baud rate range
Example: Base clock frequency = 10 MHz = 10,000,000 Hz Setting of BRGCn.MDLn7 to BRGCn.MDLn0 bits = 00100001B (k = 33) Target baud rate = 153,600 bps Baud rate = 10,000,000/(2 x 33) = 151,515 [bps] Error = (151,515/153,600 - 1) x 100 = -1.357 [%]
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14.6.3 Baud rate setting example Table 14-4. Baud Rate Generator Setting Data
fXX = 20 MHz fUCLK fXX/512 fXX/256 fXX/128 fXX/64 fXX/32 fXX/16 fXX/64 fXX/8 fXX/32 fXX/32 fXX/2 fXX/4 fXX/16 fXX/2 fXX/16 fXX/2 fXX/2 fXX/2 fXX/4 k 41H (65) 41H (65) 41H (65) 41H (65) 41H (65) 41H (65) 0FH (15) 41H (65) 0DH (13) 0AH (10) 95H (149) 41H (65) 0DH (13) 59H (89) 0AH (10) 41H (65) 2BH (43) 21H (33) 08H (8) ERR 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -0.13 0.16 0.16 0.32 0.00 0.16 0.94 -1.36 0 fUCLK fXX/1024 fXX/1024 fXX/512 fXX/256 fXX/128 fXX/64 fXX/64 fXX/32 fXX/2 fXX/32 fXX/2 fXX/16 fXX/2 fXX/2 fXX/16 fXX/8 fXX/2 fXX/4 fXX/2 fXX = 16 MHz k 1AH (26) 0DH (13) 0DH (13) 0DH (13) 0DH (13) 0DH (13) 0CH (12) 0DH (13) A7H (167) 08H (8) 77H (119) 0DH (13) 53H (83) 47H (71) 08H (8) 0DH (13) 23H (35) 0DH (13) 0DH (13) ERR 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -0.20 0.00 0.04 0.16 0.40 0.60 0.00 0.16 -0.79 0.16 -1.54 fUCLK fXX/256 fXX/128 fXX/64 fXX/32 fXX/16 fXX/8 fXX/32 fXX/4 fXX/16 fXX/16 fXX fXX/2 fXX/8 fXX fXX/8 fXX fXX fXX fXX/2 fXX = 10 MHz k 41H (65) 41H (65) 41H (65) 41H (65) 41H (65) 41H (65) 0FH (15) 41H (65) 0DH (13) 0AH (10) 95H (149) 41H (65) 0DH (13) 59H (89) 0AH (10) 41H (65) 2BH (43) 21H (33) 08H (8) ERR 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0 -0.13 0.16 0.16 0.32 0.00 0.16 0.94 -1.36 0.00
Baud Rate (bps) 300 600 1200 2400 4800 9600 10400 19200 24000 31250 33600 38400 48000 56000 62500 76800 115200 153600 312500
Caution
The allowable frequency of the base clock (fUCLK) is as follows. * VDD = 4.5 to 5.5 V: fUCLK 12 MHz * VDD = 2.7 to 4.5 V: fUCLK 6 MHz
Remark
fXX: fUCLK: k: ERR:
Main clock frequency Base clock frequency Set values of BRGCn.MDLn7 to BRGCn.MDLn0 bits Baud rate error [%]
n = 0 to 2
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14.6.4 Allowable baud rate range during reception The degree to which a discrepancy from the transmission destination's baud rate is allowed during reception is shown below. Caution The equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range. Figure 14-13. Allowable Baud Rate Range During Reception
Latch timing UARTn transfer rate
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FL 1 data frame (11 x FL)
Minimum allowable transfer rate
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmin
Maximum allowable transfer rate
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmax
As shown in Figure 14-13, after the start bit is detected, the receive data latch timing is determined according to the counter that was set by the BRGCn register. If all data up to the final data (stop bit) is in time for this latch timing, the data can be received normally. If this is applied to 11-bit reception, the following is theoretically true. FL = (Brate)-1 Brate: UARTn baud rate k: FL: BRGCn register set value 1-bit data length
When the latch timing margin is 2 base clocks, the minimum allowable transfer rate (FLmin) is as follows.
FL min = 11x FL - k-2 2k x FL = 21k + 2 2k
FL
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Therefore, the transfer destination's maximum receivable baud rate (BRmax) is as follows.
BRmax = (FLmin/11)-1 =
22k 21k + 2 Brate
Similarly, the maximum allowable transfer rate (FLmax) can be obtained as follows.
10 k+2 21k - 2 x FL max = 11x FL - x FL = FL 11 2xk 2xk 21k - 2 FL max = FL x 11 20k
Therefore, the transfer destination's minimum receivable baud rate (BRmin) is as follows.
BRmin = (FLmax/11)-1 =
20k 21k - 2
Brate
The allowable baud rate error of UARTn and the transfer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values. Table 14-5. Maximum and Minimum Allowable Baud Rate Error
Division Ratio (k) Maximum Allowable Baud Rate Error 8 20 50 100 255 +3.53% +4.26% +4.56% +4.66% +4.72% Minimum Allowable Baud Rate Error -3.61% -4.31% -4.58% -4.67% -4.73%
Remarks 1. The reception precision depends on the number of bits in one frame, the base clock frequency, and the division ratio (k). The higher the base clock frequency and the larger the division ratio (k), the higher the precision. 2. k: BRGCn register set value
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14.6.5 Transfer rate during continuous transmission During continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of the base clock longer than normal. However, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit. Figure 14-14. Transfer Rate During Continuous Transmission
1 data frame
Start bit of second byte Bit 7 FL Parity bit FL Stop bit FLstp Start bit FL Bit 0 FL
Start bit FL
Bit 0 FL
Bit 1 FL
Representing the 1-bit data length by FL, the stop bit length by FLstp, and the base clock frequency by fUCLK yields the following equation. FLstp = FL + 2/fUCLK Therefore, the transfer rate during continuous transmission is as follows (when the stop bit length = 1). Transfer rate = 11 x FL + (2/fUCLK)
14.7 Cautions
Cautions to be observed when using UARTn are shown below. (1) When the supply of clocks to UARTn is stopped (for example, in IDLE or STOP mode), operation stops with each register retaining the value it had immediately before the supply of clocks was stopped. The TXDn pin output also holds and outputs the value it had immediately before the supply of clocks was stopped. However, operation is not guaranteed after the supply of clocks is restarted. Therefore, after the supply of clocks is restarted, the circuits should be initialized by clearing the ASIMn.UARTEn, ASIMn.RXEn, and ASIMn.TXEn bits to 000. (2) UARTn has a 2-stage buffer configuration consisting of the TXBn register and the transmission shift register, and has status flags (ASIFn.TXBFn and ASIFn.TXSFn bits) that indicate the status of each buffer. If the TXBFn and TXSFn bits are read in continuous transmission, the value changes 10 11 01. For the timing to write the next data to the TXBn register, read only the TXBFn bit during continuous transmission.
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CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0)
In the V850ES/KE2, two channels of clocked serial interface 0 (CSI0) are provided.
15.1 Features
* * * * * *
Maximum transfer speed: 5 Mbps Master mode/slave mode selectable Transmission data length: 8 bits or 16 bits can be set MSB/LSB-first selectable for transfer data Eight clock signals can be selected (7 master clocks and 1 slave clock) 3-wire type SO0n: SI0n: Serial transmit data output Serial receive data input
SCK0n: Serial clock I/O
* Interrupt sources: 1 type
* Transmission/reception completion interrupt request signal (INTCSI0n)
* Transmission/reception mode or reception-only mode selectable * Two transmission buffer registers (SOTBFn/SOTBFLn, SOTBn/SOTBLn) and two reception buffer registers
(SIRBn/SIRBLn, SIRBEn/SIRBELn) are provided on chip
* Single transfer mode/continuous transfer mode selectable
Remark n = 0, 1
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15.2 Configuration
CSI0n is controlled via the CSIM0n register. (1) Clocked serial interface mode register 0n (CSIM0n) The CSIM0n register is an 8-bit register that specifies the operation of CSI0n. (2) Clocked serial interface clock selection register n (CSICn) The CSICn register is an 8-bit register that controls the CSI0n serial transfer operation. (3) Serial I/O shift register 0n (SIO0n) The SIO0n register is a 16-bit shift register that converts parallel data into serial data. The SIO0n register is used for both transmission and reception. Data is shifted in (reception) and shifted out (transmission) from the MSB or LSB side. The actual transmission/reception operations are started up by accessing the buffer register. (4) Serial I/O shift register 0nL (SIO0nL) The SIO0nL register is an 8-bit shift register that converts parallel data into serial data. The SIO0nL register is used for both transmission and reception. Data is shifted in (reception) and shifted out (transmission) from the MSB or LSB side. The actual transmission/reception operations are started up by access of the buffer register . (5) Clocked serial interface receive buffer register n (SIRBn) The SIRBn register is a 16-bit buffer register that stores receive data. (6) Clocked serial interface receive buffer register nL (SIRBnL) The SIRBnL register is an 8-bit buffer register that stores receive data. (7) Clocked serial interface read-only receive buffer register n (SIRBEn) The SIRBEn register is a 16-bit buffer register that stores receive data. The SIRBEn register is the same as the SIRBn register. It is used to read the contents of the SIRBn register. (8) Clocked serial interface read-only receive buffer register nL (SIRBEnL) The SIRBEnL register is an 8-bit buffer register that stores receive data. The SIRBEnL register is the same as the SIRBnL register. It is used to read the contents of the SIRBnL register. (9) Clocked serial interface transmit buffer register n (SOTBn) The SOTBn register is a 16-bit buffer register that stores transmit data. (10) Clocked serial interface transmit buffer register nL (SOTBLnL) The SOTBnL register is an 8-bit buffer register that stores transmit data. (11) Clocked serial interface initial transmit buffer register n (SOTBFn) The SOTBFn register is a 16-bit buffer register that stores the initial transmit data in the continuous transfer mode.
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(12) Clocked serial interface initial transmit buffer register nL (SOTBFnL) The SOTBFnL register is an 8-bit buffer register that stores initial transmit data in the continuous transfer mode. (13) Selector The selector selects the serial clock to be used. (14) Serial clock controller Controls the serial clock supply to the shift register. Also controls the clock output to the SCK0n pin when the internal clock is used. (15) Serial clock counter Counts the serial clock output or input during transmission/reception, and checks whether 8-bit or 16-bit data transmission/reception has been performed. (16) Interrupt controller Controls the interrupt request timing. Remark n = 0, 1
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Figure 15-1. Block Diagram of Clocked Serial Interface
fXX/26 fXX/25 fXX/24 fXX/23 fXX/22 fXX/2 TO50, TO51 SCK0n Selector
Serial clock controller Clock start/stop control & clock phase control SCK0n
Interrupt controller
INTCSI0n
Transmission control
Transmission data control
Initial transmit buffer register (SOTBFn/SOTBFnL)
Control signal
SO selection
SO0n
Transmit buffer register (SOTBn/SOTBnL)
SI0n
Shift register (SIOn/SIO0nL)
SO latch
Receive buffer register (SIRBn/SIRBnL)
Remarks 1. n = 0, 1 2. fXX: Main clock
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15.3 Registers
(1) Clocked serial interface mode register 0n (CSIM0n) The CSIM0n register controls the CSI0n operation. This register can be read or written in 8-bit or 1-bit units (however, CSOTn bit is read-only). Reset sets CSIM0n to 00H. Caution Overwriting the CSIM0n.TRMDn, CSIM0n.CCLn, CSIM0n.DIRn, CSIM0n.CSITn, and
CSIM0n.AUTOn bits can be done only when the CSOTn bit = 0. If these bits are overwritten at any other time, the operation cannot be guaranteed.
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After reset: 00H <7> CSIM0n (n = 0, 1) CSI0En
R/W <6> TRMDn
Address: CSIM00 FFFFFD00H, CSIM01 FFFFFD10H 5 CCLn <4> DIRn 3 CSITn 2 AUTOn 1 0 <0> CSOTn
CSI0En 0 1 Disable CSI0n operation. Enable CSI0n operation.
Note
CSI0n operation enable/disable
The internal CSI0n circuit can be reset
asynchronously by clearing the CSI0En bit to 0. For the SCK0n and SO0n
pin output status when the CSI0En bit = 0, refer to 15.5 Output Pins.
TRMDn 0 1 Receive-only mode Transmission/reception mode
Specification of transmission/reception mode
When the TRMDn bit = 0, reception is performed and the SO0n pin outputs a low level. Data reception is started by reading the SIRBn register. When the TRMDn bit = 1, transmission/reception is started by writing data to the SOTBn register.
CCLn 0 1 8 bits 16 bits
Specification of data length
DIRn 0 1
Specification of transfer direction mode (MSB/LSB) First bit of transfer data is MSB First bit of transfer data is LSB
CSITn 0 1 No delay
Control of delay of interrupt request signal
Delay mode (interrupt request signal is delayed 1/2 cycle compared to the serial clock)
The delay mode (CSITn bit = 1) is valid only in the master mode (CSICn.CKS0n2 to CSICn.CSK0n0 bits are not 111B). In the slave mode (CKS0n2 to CKS0n0 bits are 111B), do not set the delay mode.
AUTOn 0 1
Specification of single transfer mode or continuous transfer mode Single transfer mode Continuous mode
CSOTn 0 1 Communication stopped Communication in progress
Communication status flag
The CSOTn bit is cleared (0) by writing 0 to the CSI0En bit.
Note The CSOTn bit and the SIRBn, SIRBnL, SIRBE, SIRBEnL, SIOn, and SIOnL registers are reset.
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(2) Clocked serial interface clock selection register n (CSICn) The CSICn register is an 8-bit register that controls the CSI0n transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets CSICn to 00H. Caution The CSICn register can be overwritten only when the CSIM0n.CSI0En bit = 0.
After reset: 00H 7 CSICn (n = 0, 1)
CKPn 0 DAPn 0 (Type 1)
R/W 6 0
Address: CSIC0 FFFFFD01H, CSIC1 FFFFFD11H 5 0 4 CKPn 3 DAPn 2 CKS0n2 1 CKS0n1 0 CKS0n0
0
Specification of timing of transmitting/receiving data to/from SCK0n
SCK0n (I/O) SO0n (output) SI0n (input) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
0
1
(Type 2)
SCK0n (I/O) SO0n (output) SI0n (input)
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
1
0
(Type 3)
SCK0n (I/O) SO0n (output) SI0n (input)
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
1
1
(Type 4)
SCK0n (I/O) SO0n (output) SI0n (input) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
CKS0n2 CKS0n1 CKS0n0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2
2
Serial clock
Note
Mode Master mode Master mode Master mode Master mode Master mode Master mode Master mode Slave mode
3
4
5
6
Clock generated by TO5n External clock (SCK0n pin)
Note
Set the serial clock so as to satisfy the following conditions. * VDD = 4.0 to 5.5 V: Serial clock 5 MHz * VDD = 2.7 to 4.0 V: Serial clock 2.5 MHz
Remark
fXX: Main clock frequency
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(3) Clocked serial interface receive buffer registers n, nL (SIRBn, SIRBnL) The SIRBn register is a 16-bit buffer register that stores receive data. When the receive-only mode is set (CSIM0n.TRMDn bit = 0), the reception operation is started by reading data from the SIRBn register. This register is read-only in 16-bit units. When the lower 8 bits are used as the SIRBnL register, this register is read-only in 8-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSIM0n.CSI0En bit. Cautions 1. Read the SIRBn register only when a 16-bit data length has been set (CSIM0n.CCLn bit = 1). Read the SIRBnL register only when an 8-bit data length has been set (CCLn bit = 0). 2. When the single transfer mode has been set (CSIM0n.AUTOn bit = 0), perform a read operation only in the idle state (CSIM0n.CSOTn bit = 0). If the SIRBn or SIRBnL register is read during data transfer, the data cannot be guaranteed.
(a) SIRBn register
After reset: 0000H 15 SIRBn (n = 0, 1) 14 13 R 12 Address: SIRB0 FFFFFD02H, SIRB1 FFFFFD12H 11 10 9 8 7 6 5 4 3 2 1 0
SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(b) SIRBnL register
After reset: 00H 7 SIRBnL (n = 0, 1) SIRBn7 R 6 SIRBn6 Address: SIRB0L FFFFFD02H, SIRB1L FFFFFD12H 5 SIRBn5 4 SIRBn4 3 SIRBn3 2 SIRBn2 1 SIRBn1 0 SIRBn0
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(4) Clocked serial interface read-only receive buffer registers n, nL (SIRBEn, SIRBEnL) The SIRBEn register is a 16-bit buffer register that stores receive data. The SIRBEn register is the same as the SIRBn register. Even if the SIRBEn register is read, the next operation will not start. The SIRBEn register is used to read the contents of the SIRBn register when the serial reception is not continued. This register is read-only in 16-bit units. However, when the lower 8 bits are used as the SIRBEnL register, the register is read-only in 8-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSIM0n.CSI0En bit. Cautions 1. The receive operation is not started even if data is read from the SIRBEn and SIRBEnL registers. 2. The SIRBEn register can be read only if a 16-bit data length has been set (CSIM0n.CCLn bit = 1). The SIRBEnL register can be read only if an 8-bit data length has been set (CCLn bit = 0).
(a) SIRBEn register
After reset: 0000H 15 SIRBEn (n = 0, 1) 14 R 13 Address: SIRBE0 FFFFFD06H, SIRBE1 FFFFFD16H 12 11 10 9 8 7 6 5 4 3 2 1 0
SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(B) SIRBEnL register
After reset: 00H 7 SIRBEnL (n = 0, 1) R 6 Address: SIRBE0L FFFFFD06H, SIRBE1L FFFFFD16H 5 4 3 2 1 0
SIRBEn7 SIRBEn6 SIRBEn5 SIRBEn4 SIRBEn3 SIRBEn2 SIRBEn1 SIRBEn0
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(5) Clocked serial interface transmit buffer registers n, nL (SOTBn, SOTBnL) The SOTBn register is a 16-bit buffer register that stores transmit data. When the transmission/reception mode is set (CSIM0n.TRMDn bit = 1), the transmission operation is started by writing data to the SOTBn register. This register can be read or written in 16-bit units. However, when the lower 8 bits are used as the SOTBnL register, the register is read-only in 8-bit units. After reset, this register is initialized. Cautions 1. Access the SOTBn register only when a 16-bit data length has been set (CSIM0n.CCLn bit = 1). Access the SOTBnL register only when an 8-bit data length has been set (CCLn bit = 0). 2. When the single transfer mode is set (CSIM0n.AUTOn bit = 0), perform access only in the idle state (CSIM0n.CSOTn bit = 0). If the SOTBn and SOTBnL registers are accessed during data transfer, the data cannot be guaranteed.
(a) SOTBn register
After reset: 0000H 15 SOTBn (n = 0, 1) 14 R/W 13 12 Address: SOTB0 FFFFFD04H, SOTB1 FFFFFD14H 11 10 9 8 7 6 5 4 3 2 1 0
SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(b) SOTBnL register
After reset: 00H 7 SOTBnL (n = 0, 1) R/W 6 Address: SOTB0L FFFFFD04H, SOTB1L FFFFFD14H 5 4 3 2 1 0
SOTBn7 SOTBn6 SOTBn5 SOTBn4 SOTBn3 SOTBn2 SOTBn1 SOTBn0
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(6) Clocked serial interface initial transmit buffer registers n, nL (SOTBFn, SOTBFnL) The SOTBFn register is a 16-bit buffer register that stores initial transmission data in the continuous transfer mode. The transmission operation is not started even if data is written to the SOTBFn register. This register can be read or written in 16-bit units. However, when the lower 8 bits are used as the SOTBFnL register, the register can be read or written in 8-bit units. After reset, this register is initialized. Caution Access the SOTBFn register and SOTBFnL register only when a 16-bit data length has been set (CSIM0n.CCLn bit = 1), and only when an 8-bit data length has been set (CCLn bit = 0), respectively, and only in the idle state (CSIM0n.CSOTn bit = 0). If the SOTBFn and SOTBFnL registers are accessed during data transfer, the data cannot be guaranteed.
(a) SOTBFn register
After reset: 0000H 15 SOTBFn (n = 0, 1) 14 R/W 13 12 Address: SOTBF0 FFFFFD08H, SOTBF1 FFFFFD18H 11 10 9 8 7 6 5 4 3 2 1 0
SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(b) SOTBFnL register
After reset: 00H 7 SOTBFnL (n = 0, 1) R/W 6 Address: SOTBF0L FFFFFD08H, SOTBF1L FFFFFD18H 5 4 3 2 1 0
SOTBFn7 SOTBFn6 SOTBFn5 SOTBFn4 SOTBFn3 SOTBFn2 SOTBFn1 SOTBFn0
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(7)
Serial I/O shift registers n, nL (SIO0n, SIO0nL) The SIO0n register is a 16-bit shift register that converts parallel data into serial data. The transfer operation is not started even if the SIO0n register is read. This register is read-only in 16-bit units. However, when the lower 8 bits are used as the SIO0nL register, the register is read-only in 8-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSIM0n.CSI0En bit. Caution Read the SIO0n register and SIO0nL register only when a 16-bit data length has been set (CSIM0n.CCLn bit = 1), and only when an 8-bit data length has been set (CCLn bit = 0), respectively, and only in the idle state (CSIM0n.CSOTn bit = 0). If the SIO0n and SIO0nL registers are read during data transfer, the data cannot be guaranteed.
(a) SIO0n register
After reset: 0000H 15 SIO0n (n = 0, 1) 14 13 R 12 Address: SIO00 FFFFFD0AH, SIO01 FFFFFD1AH 11 10 9 8 7 6 5 4 3 2 1 0
SIOn15 SIOn14 SIOn13 SIOn12 SIOn11 SIOn10 SIOn9 SIOn8 SIOn7 SIOn6 SIOn5 SIOn4 SIOn3 SIOn2 SIOn1 SIOn0
(b) SIO0nL register
After reset: 00H 7 SIO0nL (n = 0, 1) SIOn7 R 6 SIOn6 Address: SIO00L FFFFFD0AH, SIO01L FFFFFD1AH 5 SIOn5 4 SIOn4 3 SIOn3 2 SIOn2 1 SIOn1 0 SIOn0
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Table 15-1. Use of Each Buffer Register
Register Name SIRBn (SIRBnL) R/W Single Transfer Transmission/Reception Mode Read Function Storing received dataNote 2 Receive-Only Mode * Reading starts reception * Storing received data * First, read dummy data and start transfer. * To perform reception of the next data after reception is complete, read the received data from this register. Continuous TransferNote 1 Transmission/Reception Mode Storing up to the (N - 1)th received data (other than the last)Note 2 When reception is complete, read the received data from this register. Repeat this operation until the (N - 1)th data has been received. Receive-Only Mode * Reading starts reception * Storing up to the (N - 2)th data (other than the last two) When reception is complete, read the received data from this register. Repeat this operation until the (N - 2)th data has been received. (Supplement) Do not read the (N - 1)th data from this register. If read, a reception operation starts and continuous transfer cannot be completed. Storing the (N - 1)th received dataNote 2 Read the (N - 1)th received data from this register when the (N - 1)th or Nth (last) data has been received. Storing the Nth (last) received dataNote 2 When the Nth (last) data has been received, read the Nth (last) data. -
Use method
When transmission and reception are complete, read the received data from this register.
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SIRBEn (SIRBEnL)
Read
Function Use method Not used.
-
Storing the data received lastNote 2 If reception of the next data will not be performed after reception is complete, read the received data from this register. Not used
-
SIO0n (SIO0nL)
Read
Function Use method Not used.
- Not used
-
Storing the Nth (last) received dataNote 2 When the Nth (last) transmission/reception is complete, read the Nth (last) data.
SOTBn (SOTBnL)
Write
Function
* Starting transmission/reception when written * Storing the data to be transmitted * When transmission/reception is complete, write the data to be transmitted next. - Not used Not used
-
* Starting transmission/reception when written * Storing the data to be transmitted second and subsequently When transmission/reception is complete, write the data to be transmitted next to this register to start the next transmission/reception. Not used
Use method
Not used
SOTBFn (SOTBFnL)
Write
Function Use method
-
Storing the data to be transmitted firstNote 2 Before starting transmission/reception (writing to SOTBn), write the data to be transmitted first. Not used
-
Notes 1. It is assumed that the number of data to be transmitted is N. 2. Neither reading nor writing will start communication. Remark In the 16-bit mode, the registers not enclosed in parentheses are used; in the 8-bit mode, the registers in parentheses are used.
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15.4 Operation
15.4.1 Transmission/reception completion interrupt request signal (INTCSI0n) The INTCSI0n signal is set (1) upon completion of data transmission/reception. Writing to the CSIM0n register clears (0) the INTCSI0n signal. Caution The delay mode (CSIM0n.CSITn bit = 1) is valid only in the master mode (CSICn.CKS0n2 to CSICn.CKS0n0 bits are not 111B). The delay mode cannot be set when the slave mode is set (CKS0n2 to CKS0n0 bits = 111B).
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Figure 15-2. Timing Chart of INTCSI0n Signal Output in Delay Mode
(a) Transmit/receive type 1
Input clock
SCK0n (I/O)
SI0n (input)
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO0n (output)
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Reg_R/W
INTCSI0n signal
CSOTn bit Delay
(b) Transmit/receive type 4
Input clock
SCK0n (I/O)
SI0n (input)
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO0n (output)
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Reg_R/W
INTCSI0n signal
CSOTn bit Delay
Remarks 1. Reg_R/W: Internal signal. This signal indicates that the SIRBn/SIRBnL register read or the SOTBn/SOTBnL register write was performed. 2. n = 0, 1
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15.4.2 Single transfer mode (1) Usage In the receive-only mode (CSIM0n.TRMDn bit = 0), communication is started by reading the SIRBn/SIRBnL register. In the transmission/reception mode (TRMDn bit = 1), communication is started by writing to the SOTBn/SOTBnL register. In the slave mode, the operation must be enabled beforehand (CSIM0n.CSI0En bit = 1). When communication is started, the value of the CSIM0n.CSOTn bit becomes 1 (transmission execution status). Upon communication completion, the transmission/reception completion interrupt request signal (INTCSI0n) is generated, and the CSOTn bit is cleared (0). The next data communication request is then waited for. Caution Remark When the CSOTn bit = 1, do not manipulate the CSI0n register. n = 0, 1
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Figure 15-3. Timing Chart in Single Transfer Mode (1/2)
(a) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, when AAH is received and 55H is transmitted, transmit/receive type 1
SCK0n (I/O)
SO0n (output)
0
1
0
1
0
1
0
1
(55H)
SI0n (input)
1
0
1
0
1
0
1
0
(AAH)
Reg_R/W SOTBnL register SIO0nL register SIRBnL register
Write 55H to SOTBnL register
55H (transmit data)
ABH
56H
ADH
5AH
B5H
6AH
D5H
AAH
AAH
CSOTn bit INTCSI0n signal
Remarks 1. Reg_R/W: Internal signal. This signal indicates that the SIRBn/SIRBnL register read or the SOTBn/SOTBnL register write was performed. 2. For the transmit/receive types, refer to 15.3 (2) register n (CSICn). 3. n = 0, 1 Clocked serial interface clock selection
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Figure 15-3. Timing Chart in Single Transfer Mode (2/2)
(b) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, when AAH is received and 55H is transmitted, transmit/receive type 2
SCK0n (I/O)
SO0n (output)
0
1
0
1
0
1
0
1
(55H)
SI0n (input)
1
0
1
0
1
0
1
0
(AAH)
Reg_R/W SOTBnL register SIO0nL register SIRBnL register CSOTn bit INTCSI0n signal
Write 55H to SOTBnL register
55H (transmit data)
ABH
56H
ADH
5AH
B5H
6AH
D5H
AAH
AAH
Remarks 1. Reg_R/W: Internal signal. This signal indicates that the SIRBn/SIRBnL register read or the SOTBn/SOTBnL register write was performed. 2. For the transmit/receive types, refer to 15.3 (2) register n (CSICn). 3. n = 0, 1 Clocked serial interface clock selection
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15.4.3 Continuous transfer mode (1) Usage (receive-only: 8-bit data length) <1> Set the continuous transfer mode (CSIM0n.AUTOn bit = 1) and the receive-only mode (CSIM0n.TRMDn bit = 0). <2> Read the SIRBnL register (start transfer with dummy read). <3> When the transmission/reception completion interrupt request signal (INTCSI0n) has been generated, read the SIRBnL registerNote (reserve next transfer). <4> Repeat step <3> (N - 2) times. (N: Number of transfer data) Ignore the interrupt triggered by reception of the (N - 1)th data (at this time, the SIRBEnL register can be read). <5> Following generation of the last INTCSI0n signal, read the SIRBEnL register and the SIO0nL registerNote. Note When transferring N number of data, receive data is loaded by reading the SIRBnL register from the first data to the (N - 2)th data. The (N - 1)th data is loaded by reading the SIRBEnL register, and the Nth (last) data is loaded by reading the SIO0nL register (refer to Table 15-1 Use of Each Buffer Register).
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Figure 15-4. Continuous Transfer (Receive-Only) Timing Chart
* Transmit/receive type 1, 8-bit data length
SCK0n (I/O) SI0n (input) SIO0nL register SIRBnL register
din-1
din-2
din-3
din-4
din-5 din-5
din-1 SIRBn (dummy) SIRBn (1)
din-2
din-3 SIRBn (d2)
din-4 SIRBn (d3) SIRBEn (d4) SIO0n (d5)
Reg-RD
CSOTn bit INTCSI0n signal SO0n (output)
L
rq_clr trans_rq <1> <2> <3> <4>
Period during which next transfer can be reserved
<3>
<3>
<5>
Remarks 1. Reg_RD: Internal signal. This signal indicates that the SIRBnL register has been read. rq_clr: trans_rq: 2. n = 0, 1 Internal signal. Transfer request clear signal. Internal signal. Transfer request signal.
In the case of the continuous transfer mode, two transfer requests are set at the start of the first transfer. Following the INTCSI0n signal, transfer is continued if the SIRBnL register can be read within the next transfer reservation period. If the SIRBnL register cannot be read, transfer ends and the SIRBnL register does not receive the new value of the SIO0nL register. The last data can be obtained by reading the SIO0nL register following completion of the transfer.
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(2) Usage (transmission/reception: 8-bit data length) <1> Set the continuous transfer mode (CSIM0n.AUTOn bit = 1) and the transmission/reception mode (CSIM0n.TRMDn bit = 1). <2> Write the first data to the SOTBFnL register. <3> Write the 2nd data to the SOTBnL register (start transfer). <4> When the transmission/reception completion interrupt request signal (INTCSI0n) has been generated, write the next data to the SOTBnL register (reserve next transfer). Read the SIRBnL register to load the receive data. <5> Repeat step <4> as long as data to be sent remains. <6> When the INTCSI0n signal is generated, read the SIRBnL register to load the (N - 1)th receive data (N: Number of transfer data). <7> Following the last INTCSI0n signal, read the SIO0nL register to load the Nth (last) receive data.
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Figure 15-5. Continuous Transfer (Transmission/Reception) Timing Chart
* Transmit/receive type 1, 8-bit data length
SCK0n (I/O) SO0n (output) SI0n (input) SOTBFnL register SOTBnL register SIO0nL register SIRBnL register dout-1 dout-2 dout-3 dout-4 dout-5 din-5 din-1 SOTBn (d3) SIRBn (d1) din-2 din-3 SOTBn (d4) SIRBn (d2) din-4 SOTBn (d5) SIRBn (d3) SIRBn (d4) SIOn (d5) dout-1 din-1 dout-2 din-2 dout-3 din-3 dout-4 din-4 dout-5 din-5
SOTBFn (d1) Reg_WR SOTBn (d2) Reg_RD
CSOTn bit INTCSI0n signal rq_clr trans_rq <1> <2> <3> <4> <5> <4> <6> Period during which next transfer can be reserved <5> <4> <5> <7> <8>
Remarks 1. Reg_WR: Internal signal. This signal indicates that the SOTBnL register has been written. Reg_RD: Internal signal. This signal indicates that the SIRBnL register has been read. rq_clr: trans_rq: 2. n = 0, 1 Internal signal. Transfer request clear signal. Internal signal. Transfer request signal.
In the case of the continuous transfer mode, two transfer requests are set at the start of the first transfer. Following the INTCSI0n signal, transfer is continued if the SOTBnL register can be written within the next transfer reservation period. If the SOTBnL register cannot be written, transfer ends and the SIRBnL register does not receive the new value of the SIO0nL register. The last receive data can be obtained by reading the SIO0nL register following completion of the transfer.
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(3) Next transfer reservation period In the continuous transfer mode, the next transfer must be prepared with the period shown in Figure 15-6. Figure 15-6. Timing Chart of Next Transfer Reservation Period (1/2)
(a) When data length: 8 bits, transmit/receive type 1
SCK0n (I/O)
INTCSI0n signal Reservation period: 7 SCK0n cycles
(b) When data length: 16 bits, transmit/receive type 1
SCK0n (I/O)
INTCSI0n signal Reservation period: 15 SCK0n cycles
Remark
n = 0, 1
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Figure 15-6. Timing Chart of Next Transfer Reservation Period (2/2)
(c) When data length: 8 bits, transmit/receive type 2
SCK0n (I/O) INTCSI0n signal Reservation period: 6.5 SCK0n cycles
(d) When data length: 16 bits, transmit/receive type 2
SCK0n (I/O) INTCSI0n signal Reservation period: 14.5 SCK0n cycles
Remark
n = 0, 1
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(4) Cautions To continue continuous transfers, it is necessary to either read the SIRBn register or write to the SOTBn register during the transfer reservation period. If access is performed to the SIRBn register or the SOTBn register when the transfer reservation period is over, the following occurs. (i) In case of conflict between transfer request clear and register access Since transfer request clear has higher priority, the next transfer request is ignored. Therefore, transfer is interrupted, and normal data transfer cannot be performed. Figure 15-7. Transfer Request Clear and Register Access Conflict
Transfer reservation period SCK0n (I/O) INTCSI0n signal
rq_clr
Reg_R/W
Remarks 1. rq_clr:
Internal signal. Transfer request clear signal. SOTBn/SOTBnL register write was performed.
Reg_R/W: Internal signal. This signal indicates that the SIRBn/SIRBnL register read or the 2. n = 0, 1
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(ii) In case of conflict between transmission/reception completion interrupt request signal (INTCSI0n) generation and register access Since continuous transfer has stopped once, executed as a new continuous transfer. In the slave mode, a bit phase error transfer error results (refer to Figure 15-8). In the transmission/reception mode, the value of the SOTBFn register is retransmitted, and illegal data is sent. Figure 15-8. Interrupt Request and Register Access Conflict
Transfer reservation period SCK0n (I/O) INTCSI0n signal
0
1
2
3
4
rq_clr
Reg_R/W
Remarks 1. rq_clr: Internal signal. Transfer request clear signal. Reg_R/W: Internal signal. This signal indicates that the SIRBn/SIRBnL register read or the SOTBn/SOTBnL register write was performed. 2. n = 0, 1
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15.5 Output Pins
The following describes the output pins. For the setting of each pin, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. (1) SCK0n pin When the CSI0n operation is disabled (CSIM0n.CSI0En bit = 0), the SCK0n pin output status is as follows. Table 15-2. SCK0n Pin Output Status
CKPn 0 1 CKS0n2 Don't care 1 Other than above CKS0n1 Don't care 1 CKS0n0 Don't care 1 SCK0n Pin Output Fixed to high level High impedance Fixed to low level
Remark (2) SO0n pin
n = 0, 1
When the CSI0n operation is disabled (CSI0En bit = 0), the SO0n pin output status is as follows. Table 15-3. SO0n Pin Output Status
TRMDn 0 1 DAPn Don't care 0 1 AUTOn Don't care Don't care 0 CCLn Don't care Don't care 0 DIRn Don't care Don't care 0 1 1 0 1 1 0 0 1 1 0 1 SO0n Pin Output Fixed to low level SO latch value (low level) SOTBn7 bit value SOTBn0 bit value SOTBn15 bit value SOTBn0 bit value SOTBFn7 bit value SOTBFn0 bit value SOTBFn15 bit value SOTBFn0 bit value
Remark
n = 0, 1
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CHAPTER 16 I2C BUS
To use the I2C bus function, use the P38/SDA0 and P39/SCL0 pins as the SDA0 and SCL0 pins, respectively, and set them to N-ch open-drain output. In the V850ES/KE2, one channel of I2C bus is provided.
16.1 Features
The I2C0 has the following two modes. * Operation stop mode * I2C (Inter IC) bus mode (multimaster supported) (1) Operation stop mode This mode is used when serial transfers are not performed. consumption. (2) I2C bus mode (multimaster supported) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCL0) line and a serial data bus (SDA0) line. This mode complies with the I2C bus format and the master device can generate "start condition", "address", "transfer direction specification", "data", and "stop condition" data to the slave device, via the serial data bus. The slave device automatically detects these received state and data by hardware. This function can simplify the part of application program that controls the I2C bus. Since the SCL0 and SDA0 pins are used for N-ch open drain outputs, I2C0 requires pull-up resistors for the serial clock line and the serial data bus line. It can therefore be used to reduce power
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Figure 16-1. Block Diagram of I2C0
Internal bus IIC status register 0 (IICS0) MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 IIC control register 0 (IICC0) IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
SDA0 Noise eliminator
Slave address register 0 (SVA0)
Match signal
Clear Set
Start condition generator
DFC0
IIC shift register 0 (IIC0)
DQ
SO latch CL01, CL00
Stop condition generator
TRC0 N-ch open-drain output
Data retention time correction circuit
Output control ACK detector Start condition detector Stop condition detector
ACK generator
Wakeup controller
SCL0 Noise eliminator DFC0 N-ch open-drain output
Serial clock counter Serial clock wait controller
Interrupt request signal generator IICS0.MSTS0, EXC0, COI0 IIC shift register 0 (IIC0)
INTIIC0
Serial clock controller
IICC0.STT0, SPT0 IICS0.MSTS0, EXC0, COI0 fxx Prescaler
Bus status detector
CLD0 DAD0 SMC0 DFC0 CL01 CL00 IIC clock select register 0 (IICCL0)
CLX0
STCF0 IICBSY0 STCEN0 IICRSV0 IIC flag register 0 (IICF0)
IIC function expansion register 0 (IICX0)
Internal bus
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A serial bus configuration example is shown below. Figure 16-2. Serial Bus Configuration Example Using I2C Bus
+VDD +VDD
Master CPU1 Slave CPU1 Address 1
SDA SCL
Serial data bus Serial clock
SDA SCL
Master CPU2 Slave CPU2 Address 2
SDA SCL
Slave CPU3 Address 3
SDA SCL
Slave IC Address 4
SDA SCL
Slave IC Address N
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16.2 Configuration
I2C0 includes the following hardware. Table 16-1. Configuration of I2C0
Item Registers Configuration IIC shift register 0 (IIC0) Slave address register 0 (SVA0) Control registers IIC control register 0 (IICC0) IIC status register 0 (IICS0) IIC flag register 0 (IICCF0) IIC clock selection register 0 (IICCL0) IIC function expansion register 0 (IICX0)
(1) IIC shift register 0 (IIC0) The IIC0 register is used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8bit serial data. The IIC0 register can be used for both transmission and reception. Write and read operations to the IIC0 register are used to control the actual transmit and receive operations. The IIC0 register can be read or written in 8-bit units. Reset sets IIC0 to 00H. (2) Slave address register 0 (SVA0) The SVA0 register sets local addresses when in slave mode. The SVA0 register can be read or written in 8-bit units. Reset sets SVA0 to 00H. (3) SO latch The SO latch is used to retain the SDA0 pin's output level. (4) Wakeup controller This circuit generates an interrupt request signal (INTIIC0) when the address received by this register matches the address value set to the SVA0 register or when an extension code is received. (5) Prescaler This selects the sampling clock to be used. (6) Serial clock counter This counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive operations and is used to verify that 8-bit data was sent or received. (7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIIC0). An I2C interrupt is generated following either of two triggers. * Falling of the eighth or ninth clock of the serial clock (set by IICC0.WTIM0 bit) * Interrupt request generated when a stop condition is detected (set by IICC0.SPIE0 bit)
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(8) Serial clock controller In master mode, this circuit generates the clock output via the SCL0 pin from a sampling clock. (9) Serial clock wait controller This circuit controls the wait timing. (10) ACK generator, stop condition detector, start condition detector, and ACK detector These circuits are used to generate and detect various statuses. (11) Data hold time correction circuit This circuit generates the hold time for data corresponding to the falling edge of the serial clock. (12) Start condition generator This circuit generates a start condition when the IICC0.STT0 bit is set. However, in the communication reservation disabled status (IICF0.IICRSV0 bit = 1), when the bus is not released (IICF0.IICBSY0 bit = 1), start condition requests are ignored and the IICF0.STCF0 bit is set to 1. (13) Stop condition generator A stop condition is generated when the IIC0.SPT0 bit is set (1). (14) Bus status detector This circuit detects whether or not the bus is released by detecting start conditions and stop conditions. However, as the bus status cannot be detected immediately following operation, the initial status is set by the IICF0.STCEN0 bit.
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16.3 Registers
I2C0 is controlled by the following registers. * IIC control register 0 (IICC0) * IIC status register 0 (IICS0) * IIC flag register 0 (IICF0) * IIC clock selection register 0 (IICCL0) * IIC function expansion register 0 (IICX0) The following registers are also used. * IIC shift register 0 (IIC0) * Slave address register 0 (SVA0) Remark For the alternate-function pin settings, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. (1) IIC control register 0 (IICC0) The IICC0 register is used to enable/stop I2C0 operations, set wait timing, and set other I2C operations. The IICC0 register can be read or written in 8-bit or 1-bit units. However, set the SPIE0, WTIM0, and ACKE0 bits when the IICE0 bit is 0 or during the wait period. When setting the IICE0 bit from "0" to "1", these bits can also be set at the same time. Reset sets this register to 00H.
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(1/4)
After reset: 00H <7> IICC0 IICE0 R/W <6> LREL0 Address: IICC0 FFFFFD82H <5> WREL0 <4> SPIE0 <3> WTIM0 <2> ACKE0 <1> STT0 <0> SPT0
IICE0 0 1
I C0 operation enable/disable specification Stop operation. Reset the IICS0 register Enable operation.
Note 1
2
. Stop internal operation.
Be sure to set this bit to 1 when the SCL0 and SDA0 lines are high level. Condition for clearing (IICE0 bit = 0) * Cleared by instruction * Reset Condition for setting (IICE0 bit = 1) * Set by instruction
LREL0 0 1
Note 2
Exit from communications Normal operation This exits from the current communications and sets standby mode. This setting is automatically cleared to 0 after being executed. Its uses include cases in which a locally irrelevant extension code has been received. The SCL0 and SDA0 lines are set to high impedance. The STT0, SPT0, IICS0.MSTS0, IICS0.EXC0, IICS0.COI0, IICS0.TRC0, IICS0.ACKD0, and IICS0.STD0 bits are cleared to 0.
The standby mode following exit from communications remains in effect until the following communications entry conditions are met. * After a stop condition is detected, restart is in master mode. * An address match or extension code reception occurs after the start condition. Condition for clearing (LREL0 bit = 0) * Automatically cleared after execution * Reset Condition for setting (LREL0 bit = 1) * Set by instruction
WREL0 0 1
Note 2
Wait cancellation control Do not cancel wait Cancel wait. This setting is automatically cleared to 0 after wait is canceled. Condition for setting (WREL0 bit = 1) * Set by instruction
Condition for clearing (WREL0 bit = 0) * Automatically cleared after execution * Reset
Notes 1. 2. Caution
The IICS0 register, and the IICF0.STCF0, IICF0.IICBSY0, IICCL0.CLD0, and IICCL0.DAD0 bits are reset. This flag's signal is invalid when the IICE0 bit = 0. If the I2C0 operation is enabled (IICE0 bit = 1) when the SCL0 line is high level and the SDA0 line is low level, the start condition is detected immediately. To avoid this, after enabling the I2C0 operation, immediately set the LREL0 bit to 1 with a bit manipulation instruction.
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(2/4)
Note
SPIE0 0 1
Enable/disable generation of interrupt request when stop condition is detected Disable Enable Condition for setting (SPIE0 bit = 1) * Set by instruction
Condition for clearing (SPIE0 bit = 0) * Cleared by instruction * Reset
WTIM0 0
Note
Control of wait and interrupt request generation Interrupt request is generated at the eighth clock's falling edge. Master mode: After output of eight clocks, clock output is set to low level and wait is set. Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device.
1
Interrupt request is generated at the ninth clock's falling edge. Master mode: After output of nine clocks, clock output is set to low level and wait is set. Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device.
An interrupt is generated at the falling of the 9th clock during address transfer independently of the setting of this bit. The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. For a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after ACK is issued. However, when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. Condition for clearing (WTIM0 bit = 0) * Cleared by instruction * Reset Condition for setting (WTIM0 bit = 1) * Set by instruction
ACKE0 0 1
Note
Acknowledgment control Disable acknowledgment. Enable acknowledgment. During the ninth clock period, the SDA0 line is set to low level.
The ACKE0 bit setting is invalid for address reception. In this case, ACK is generated when the addresses match. However, the ACKE0 bit setting is valid for address reception of the extension code. Condition for clearing (ACKE0 bit = 0) * Cleared by instruction * Reset Condition for setting (ACKE0 bit = 1) * Set by instruction
Note This flag's signal is invalid when the IICE0 bit = 0.
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2
(3/4)
STT0 0 1 Do not generate a start condition. When bus is released (in STOP mode): Generate a start condition (for starting as master). The SDA0 line is changed from high level to low level while the SCL0 line is high level and then the start condition is generated. Next, after the rated amount of time has elapsed, the SCL0 line is changed to low level (wait status). When a third party is communicating * When communication reservation function is enabled (IICF0.IICRSV0 bit = 0) Functions as the start condition reservation flag. When set to 1, automatically generates a start condition after the bus is released. * When communication reservation function is disabled (IICRSV0 bit = 1) The IICF0.STCF0 bit is set to 1 and the information set (1) to the STT0 bit is cleared. No start condition is generated. In the wait state (when master device): Generates a restart condition after releasing the wait. Cautions concerning set timing For master reception: Cannot be set to 1 during transfer. Can be set to 1 only when the ACKE0 bit has been cleared to 0 and slave has been notified of final reception. For master transmission: A start condition may not be generated normally during the ACK period. Set to 1 during the wait period that follows output of the ninth clock. * Cannot be set to 1 at the same time as the SPT0 bit. * When the STT0 bit is set to 1, setting the STT0 bit to 1 again is disabled until the setting is cleared to 0. Condition for clearing (STT0 bit = 0) * When the STT0 bit is set to 1 in the communication reservation disabled status * Cleared when start condition is generated by master device * When the LREL0 bit = 1 (exit from communications) * When the IICE0 bit = 0 (operation stop) * Reset Condition for setting (STT0 bit = 1) * Set by instruction Start condition trigger
Remark
The STT0 bit is 0 if it is read after data setting.
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SPT0 0 1 Stop condition is not generated. Stop condition is generated (termination of master device's transfer). After the SDA0 line goes to low level, either set the SCL0 line to high level or wait until the SCL0 pin goes to high level. Next, after the rated amount of time has elapsed, the SDA0 line is changed from low level to high level and a stop condition is generated. Cautions concerning setting timing For master reception: Cannot be set to 1 during transfer. Can be set to 1 only when the ACKE0 bit has been cleared to 0 and during the wait period after slave has been notified of final reception. For master transmission: A stop condition may not be generated normally during the ACK period. Set to 1 during the wait period that follows output of the ninth clock. * Cannot be set to 1 at the same time as the STT0 bit. * The SPT0 bit can be set to 1 only when in master mode
Note
Stop condition trigger
.
* When the WTIM0 bit has been cleared to 0, if the SPT0 bit is set to 1 during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. The WTIM0 bit should be changed from 0 to 1 during the wait period following output of eight clocks, and the SPT0 bit should be set to 1 during the wait period that follows output of the ninth clock. * When the SPT0 bit is set to 1, setting the SPT0 bit to 1 again is disabled until the setting is cleared to 0. Condition for clearing (SPT0 bit = 0) * Cleared by loss in arbitration * Automatically cleared after stop condition is detected * When the LREL0 bit = 1 (exit from communications) * When the IICE0 bit = 0 (operation stop) * Reset Condition for setting (SPT0 bit = 1) * Set by instruction
Note Set the SPT0 bit to 1 only in master mode. However, the SPT0 bit must be set to 1 and a stop condition generated before the first stop condition is detected following the switch to operation enable status. For details, refer to 16.14 Cautions. Caution When the IICS0.TRC0 bit is set to 1, the WREL0 bit is set to 1 during the ninth clock and wait is canceled, after which the TRC0 bit is cleared to 0 and the SDA0 line is set to high impedance. Remark The SPT0 bit is 0 if it is read after data setting.
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(2) IIC status register 0 (IICS0) The IICS0 register indicates the status of the I2C0 bus. The IICS0 register is read-only, in 8-bit or 1-bit units. However, the IICS0 register can only be read when the IICC0.STT0 bit is 1 or during the wait period. Reset sets this register to 00H. Caution When the main clock is stopped and the CPU is operating on the subclock, do not access the IICS0 register. For details, refer to 3.4.8 (1) (b). (1/3)
After reset: 00H <7> IICS0 MSTS0 R <6> ALD0 Address: IICS0 FFFFFD86H <5> EXC0 <4> COI0 <3> TRC0 <2> ACKD0 <1> STD0 <0> SPD0
MSTS0 0 1
Master device status Slave device status or communication standby status Master device communication status Condition for setting (MSTS0 bit = 1) * When a start condition is generated
Condition for clearing (MSTS0 bit = 0) * When a stop condition is detected * When the ALD0 bit = 1 (arbitration loss) * Cleared by the IICC0.LREL0 bit = 1 (exit from communications) * When the IICC0.IICE0 bit changes from 1 to 0 (operation stop) * Reset
ALD0 0 1
Detection of arbitration loss This status means either that there was no arbitration or that the arbitration result was a "win". This status indicates the arbitration result was a "loss". The MSTS0 bit is cleared to 0. Condition for setting (ALD0 bit = 1)
Note
Condition for clearing (ALD0 bit = 0) * Automatically cleared after the IICS0 register is read * Reset * When the IICE0 bit changes from 1 to 0 (operation stop)
* When the arbitration result is a "loss".
Note The ALD0 bit is also cleared when a bit manipulation instruction is executed for another bit in the IICS0 register.
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EXC0 0 1 Extension code was not received. Extension code was received. Condition for setting (EXC0 bit = 1) * When the higher four bits of the received address data is either "0000" or "1111" (set at the rising edge of the eighth clock). Detection of extension code reception
Condition for clearing (EXC0 bit = 0) * When a start condition is detected * When a stop condition is detected * Cleared by the LREL0 bit = 1 (exit from communications) * When the IICE0 bit changes from 1 to 0 (operation stop) * Reset
COI0 0 1 Addresses do not match. Addresses match.
Detection of matching addresses
Condition for clearing (COI0 bit = 0) * When a start condition is detected * When a stop condition is detected * Cleared by the LREL0 bit = 1 (exit from communications) * When the IICE0 bit changes from 1 to 0 * Reset
Condition for setting (COI0 bit = 1) * When the received address matches the local address (SVA0 register) (set at the rising edge of the eighth clock).
TRC0 0 1
Detection of transmit/receive status Receive status (other than transmit status). The SDA0 line is set for high impedance. Transmit status. The value in the SO latch is enabled for output to the SDA0 line (valid starting at the rising edge of the first byte's ninth clock).
Condition for clearing (TRC0 bit = 0) * When a stop condition is detected * Cleared by the LREL0 bit = 1 (exit from communications) * When the IICE0 bit changes from 1 to 0 (operation stop) * Cleared by the IICC0.WREL0 bit = 1 * Reset Master * When "1" is output to the first byte's LSB (transfer direction specification bit) Slave * When a start condition is detected When not used for communication
Note
Condition for setting (TRC0 bit = 1) Master * When a start condition is generated * When "0" is output to the first byte's LSB (transfer direction specification bit) Slave * When "1" is input in the first byte's LSB (transfer direction specification bit)
(wait release)
* When the ALD0 bit changes from 0 to 1 (arbitration loss)
Note The IICS0.TRC0 bit is cleared to 0 and the SDA0 line become high impedance when the IICC0.WREL0 bit is set to 1 and wait state is released at the ninth clock with the TRC0 bit = 1.
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ACKD0 0 1 ACK was not detected. ACK was detected. Condition for setting (ACKD0 bit = 1) * After the SDA0 pin is set to low level at the rising edge of the SCL0 pin's ninth clock Detection of ACK
Condition for clearing (ACKD0 bit = 0) * When a stop condition is detected * At the rising edge of the next byte's first clock * Cleared by the LREL0 bit = 1 (exit from communications) * When the IICE0 bit changes from 1 to 0 (operation stop) * Reset
STD0 0 1 Start condition was not detected.
Detection of start condition
Start condition was detected. This indicates that the address transfer period is in effect Condition for setting (STD0 bit = 1) * When a start condition is detected
Condition for clearing (STD0 bit = 0) * When a stop condition is detected * At the rising edge of the next byte's first clock following address transfer * Cleared by the LREL0 bit = 1 (exit from communications) * When the IICE0 bit changes from 1 to 0 (operation stop) * Reset
SPD0 0 1 Stop condition was not detected.
Detection of stop condition
Stop condition was detected. The master device's communication is terminated and the bus is released. Condition for setting (SPD0 bit = 1) * When a stop condition is detected
Condition for clearing (SPD0 bit = 0) * At the rising edge of the address transfer byte's first clock following setting of this bit and detection of a start condition * When the IICE0 bit changes from 1 to 0 (operation stop) * Reset
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(3) IIC flag register 0 (IICF0) IICF0 is a register that set the operation mode of I2C0 and indicate the status of the I2C bus. These registers can be read or written in 8-bit or 1-bit units. However, the STCF0 and IICBSY0 bits are readonly. The IICRSV0 bit can be used to enable/disable the communication reservation function (refer to 16.13 Communication Reservation). The STCEN0 bit can be used to set the initial value of the IICBSY0 bit (refer to 16.14 Cautions). The IICRSV0 and STCEN0 bits can be written only when the operation of I2C0 is disabled (IICC0.IICE0 bit = 0). When operation is enabled, the IICF0 register can be read. Reset sets this register to 00H.
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After reset: 00H <7> IICF0 STCF0
R/WNote <6> IICBSY0
Address: IICF0 FFFFFD8AH 5 0 4 0 3 0 2 0 <1> <0>
STCEN0 IICRSV0
STCF0 0 1 Generate start condition
IICC0.STT0 clear flag
Start condition generation unsuccessful: clear STT0 flag Condition for setting (STCF0 bit = 1) * Generating start condition unsuccessful and the STT0 bit cleared to 0 when communication reservation is disabled (IICRSV0 bit = 1).
Condition for clearing (STCF0 bit = 0) * Clearing by setting the STT0 bit = 1 * When the IICE0 bit = 0 * Reset
IICBSY0 0 1
I2C0 bus status flag Bus release status (initial communication status when STCEN0 bit = 1) Bus communication status (initial communication status when STCEN0 bit = 0) Condition for setting (IICBSY0 bit = 1) * Detection of start condition * Setting of the IICE0 bit when the STCEN0 bit = 0
Condition for clearing (IICBSY0 bit = 0) * Detection of stop condition * When the IICE0 bit = 0 * Reset
STCEN0 0 1
Initial start enable trigger After operation is enabled (IICE0 bit = 1), enable generation of a start condition upon detection of a stop condition. After operation is enabled (IICE0 bit = 1), enable generation of a start condition without detecting a stop condition. Condition for setting (STCEN0 bit = 1) * Setting by instruction
Condition for clearing (STCEN0 bit = 0) * Detection of start condition * Reset
IICRSV0 0 1
Communication reservation function disable bit Enable communication reservation Disable communication reservation Condition for setting (IICRSV0 bit = 1) * Setting by instruction
Condition for clearing (IICRSV0 bit = 0) * Clearing by instruction * Reset
Note Bits 6 and 7 are read-only bits. Cautions 1. Write to the STCEN0 bit only when the operation is stopped (IICE0 bit = 0). 2. As the bus release status (IICBSY0 bit = 0) is recognized regardless of the actual bus status when the STCEN0 bit = 1, when generating the first start condition (STT0 bit = 1), it is necessary to verify that no third party communications are in progress in order to prevent such communications from being destroyed. 3. Write to the IICRSV0 bit only when the operation is stopped (IICE0 bit = 0).
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(4) IIC clock selection register 0 (IICCL0) The IICCL0 register is used to set the transfer clock for the I2C0 bus. The IICCL0 register can be read or written in 8-bit or 1-bit units. However, the CLD0 and DAD0 bits are readonly. The SMC0, CL01 and CL00 bits are set in combination with the IICX0.CLX0 bit (refer to 16.3 (6) I2C0 transfer clock setting method). Set the IICCL0 register when the IICC0.IICE0 bit = 0. Reset sets this register to 00H.
After reset: 00H 7 IICCL0 0
R/W
Note
Address: IICCL0 FFFFFD84H <5> CLD0 <4> DAD0 3 SMC0 2 DFC0 1 CL01 0 CL00
6 0
CLD0 0 1
Detection of SCL0 pin level (valid only when IICC0.IICE0 bit = 1) The SCL0 pin was detected at low level. The SCL0 pin was detected at high level. Condition for setting (CLD0 bit = 1) * When the SCL0 pin is at high level
Condition for clearing (CLD0 bit = 0) * When the SCL0 pin is at low level * When the IICE0 bit = 0 (operation stop) * Reset
DAD0 0 1
Detection of SDA0 pin level (valid only when IICE0 bit = 1) The SDA0 pin was detected at low level. The SDA0 pin was detected at high level. Condition for setting (DAD0 bit = 1) * When the SDA0 pin is at high level
Condition for clearing (DAD0 bit = 0) * When the SDA0 pin is at low level * When IICE0 bit = 0 (operation stop) * Reset
SMC0 0 1 Operates in standard mode. Operates in high-speed mode.
Operation mode switching
DFC0 0 1 Digital filter off. Digital filter on.
Digital filter operation control
Digital filter can be used only in high-speed mode. In high-speed mode, the transfer clock does not vary regardless of DFC0 bit set/clear. The digital filter is used for noise elimination in high-speed mode.
Note Bits 4 and 5 are read-only bits.
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(5) IIC function expansion register 0 (IICX0) These registers set the function expansion of I2C0 (valid only in high-speed mode). These registers can be read or written in 8-bit or 1-bit units. The CLX0 bit is set in combination with the IICCL0.SMC0, IICCL0.CL01, and IICCL0.CL00 bits (refer to 16.3 (6) I2C0 transfer clock setting method). Set the IICX0 register when the IICC0.IICE0 bit = 0. Reset sets this register to 00H.
After reset: 00H 7 IICX0 0
R/W 6 0
Address: IICX0 FFFFFD85H 5 0 4 0 3 0 2 0 1 0 <0> CLX0
(6) I2C0 transfer clock setting method The I2C0 transfer clock frequency (fSCL) is calculated using the following expression. fSCL = 1/(m x T + tR + tF) m = 12, 24, 48, 54, 86, 88, 172, 198 (refer to Table 16-2 Selection Clock Setting.) T: tR: tF: 1/fXX SCL0 rise time SCL0 fall time
For example, the I2C0 transfer clock frequency (fSCL) when fXX = 20 MHz, m = 54, tR = 200 ns, and tF = 50 ns is calculated using following expression. fSCL = 1/(54 x 50 ns + 200 ns + 50 ns) 339 kHz
m x T + tR + tF tR m/2 x T tF m/2 x T
SCL0
SCL0 inversion
SCL0 inversion
SCL0 inversion
The selection clock is set using a combination of the IICCL0.SMC0, IICCL0.CL01, and IICCL0.CL00 bits and the IICX0.CLX0 bit.
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Table 16-2. Selection Clock Setting
IICX0 Bit 0 CLX0 0 0 0 0 0 0 0 1 1 1 1 Bit 3 SMC0 0 0 0 0 1 1 1 0 1 1 1 IICCL0 Bit 1 CL01 0 0 1 1 0 1 1 x 0 1 1 Bit 0 CL00 0 1 0 1 x 0 1 x x 0 1 fXX/2 fXX/2 fXX fXX/3 fXX/2 fXX fXX/3 Setting prohibited fXX/2 fXX Setting prohibited fXX/24 fXX/12 8.00 MHz to 8.38 MHz 4.00 MHz to 4.19 MHz High-speed mode (SMC0 bit = 1) fXX/88 fXX/172 fXX/86 fXX/198 fXX/48 fXX/24 fXX/54 4.0 MHz to 8.38 MHz 8.38 MHz to 16.76 MHz 4.19 MHz to 8.38 MHz 16.0 MHz to 19.8 MHz 8 MHz to 16.76 MHz 4 MHz to 8.38 MHz 16 MHz to 20 MHz High-speed mode (SMC0 bit = 1) Normal mode (SMC0 bit = 0) Selection Clock Transfer Clock (fXX/m) Settable Internal System Clock Frequency (fXX) Range Operation Mode
Remark
x:
don't care
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(7) IIC shift register 0 (IIC0) The IIC0 shift register is used for serial transmission/reception (shift operations) that is synchronized with the serial clock. The IIC0 shift register can be read or written in 8-bit units, but data should not be written to the IIC0 shift register during a data transfer. Access (read/write) the IIC0 shift register only during the wait period. Accessing this register in communication states other than the wait period is prohibited. However, for the master device, the IIC0 shift register can be written once only after the transmission trigger bit (IICC0.STT0 bit) has been set to 1. When the IIC0 shift register is written during wait, the wait is cancelled and data transfer is started. Reset sets this register to 00H.
After reset: 00H 7 IIC0
R/W 6
Address: IIC0 FFFFFD80H 5 4 3 2 1 0
(8) Slave address register 0 (SVA0) The SVA0 register holds the I2C bus's slave addresses. However, rewriting this register is prohibited when the IICS0.STD0 bit = 1 (start condition detection). The SVA0 register can be read or written in 8-bit units, but bit 0 is fixed to 0. Reset sets this register to 00H.
After reset: 00H 7 SVA0
R/W 6
Address: SVA0 FFFFFD83H 5 4 3 2 1 0 0
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16.4 Functions
16.4.1 Pin configuration The serial clock pin (SCL0) and serial data bus pin (SDA0) are configured as follows. SCL0 .............. This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. SDA0 .............. This pin is used for serial data input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-up resistor is required. Figure 16-3. Pin Configuration Diagram
VDD
Slave device
Master device SCL0 Clock output VDD (Clock input) SDA0 Data output SDA0 Data output Clock input SCL0 (Clock output)
Data input
Data input
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16.5 I2C Bus Definitions and Control Methods
The following section describes the I2C bus's serial data communication format and the status generated by the I2C bus. The transfer timing for the "start condition", "address", "transfer direction specification", "data", and "stop condition" generated via the I2C bus's serial data bus is shown below. Figure 16-4. I2C Bus's Serial Data Transfer Timing
SCL0
1 to 7
8
9
1 to 8
9
1 to 8
9
SDA0 Start Address condition R/W ACK Data ACK Data ACK Stop condition
The master device generates the start condition, slave address, and stop condition. ACK can be generated by either the master or slave device (normally, it is generated by the device that receives 8bit data). The serial clock (SCL0) is continuously output by the master device. However, in the slave device, the SCL0's lowlevel period can be extended and a wait can be inserted. 16.5.1 Start condition A start condition is met when the SCL0 pin is at high level and the SDA0 pin changes from high level to low level. The start conditions for the SCL0 pin and SDA0 pin are generated when the master device starts a serial transfer to the slave device. Start conditions can be detected when the device is used as a slave. Figure 16-5. Start Conditions
H SCL0
SDA0
A start condition is generated when the IICC0.STT0 bit is set to 1 after a stop condition has been detected (IICS0.SPD0 bit = 1). When a start condition is detected, IICS0.STD0 bit is set to 1.
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16.5.2 Addresses The 7 bits of data that follow the start condition are defined as an address. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines. Therefore, each slave device connected via the bus lines must have a unique address. The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data matches the data values stored in the SVA0 register. If the address data matches the SVA0 values, the slave device is selected and communicates with the master device until the master device generates a start condition or stop condition. Figure 16-6. Address
SCL0
1
2
3
4
5
6
7
8
9
SDA0
AD6
AD5
AD4
AD3 Address
AD2
AD1
AD0
R/W
Note
INTIIC0
Note The interrupt request signal (INTIIC0) is generated if a local address or extension code is received during slave device operation.
The slave address and the eighth bit, which specifies the transfer direction as described in 16.5.3 written to the IIC0 register. The slave address is assigned to the higher 7 bits of the IIC0 register.
Transfer
direction specification below, are together written to the IIC0 register and are then output. Received addresses are
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16.5.3 Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device. When the transfer direction specification bit has a value of 1, it indicates that the master device is receiving data from a slave device. Figure 16-7. Transfer Direction Specification
SCL0
1
2
3
4
5
6
7
8
9
SDA0
AD6
AD5
AD4
AD3
AD2
AD1
AD0
R/W
Transfer direction specification Note INTIIC0
Note The interrupt request signal (INTIIC0) is generated if a local address or extension code is received during slave device operation.
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16.5.4 ACK ACK is used to confirm the serial data status of the transmitting and receiving devices. The receiving device returns ACK for every 8 bits of data it receives. The transmitting device normally receives ACK after transmitting 8 bits of data. When ACK is returned from the receiving device, the reception is judged as normal and processing continues. The detection of ACK is confirmed with the IICS0.ACKD0 bit. When the master device is the receiving device, after receiving the final data, it does not return ACK and generates the stop condition. When the slave device is the receiving device and does not return ACK, the master device generates either a stop condition or a restart condition, and then stops the current transmission. Failure to return ACK may be caused by the following factors. (a) Reception was not performed normally. (b) The final data was received. (c) The receiving device (slave) does not exist for the specified address. When the receiving device sets the SDA0 line to low level during the ninth clock, ACK is generated (normal reception). When the IICC0.ACKE0 bit is set to 1, automatic ACK generation is enabled. Transmission of the eighth bit following the 7 address data bits causes the IICS0.TRC0 bit to be set. Normally, set the ACKE0 bit to 1 for reception (TRC0 bit = 0). When the slave device is receiving (when TRC0 bit = 0), if the slave device cannot receive data or does not need to receive any more data, clear the ACKE0 bit to 0 to indicate to the master that no more data can be received. Similarly, when the master device is receiving (when TRC0 bit = 0) and the subsequent data is not needed, clear the ACKE0 bit to 0 to prevent ACK from being generated. This notifies the slave device (transmitting device) of the end of the data transmission (transmission stopped). Figure 16-8. ACK
SCL0
1
2
3
4
5
6
7
8
9
SDA0
AD6
AD5
AD4
AD3
AD2
AD1
AD0
R/W ACK
When the local address is received, ACK is automatically generated regardless of the value of the ACKE0 bit. No ACK is generated if the received address is not a local address (NACK). When receiving the extension code, set the ACKE0 bit to 1 in advance to generate ACK. The ACK generation method during data reception is based on the wait timing setting, as described by the following. * When 8-clock wait is selected (IICC0.WTIM0 bit = 0): ACK is generated at the falling edge of the SCL0n pin's eighth clock if the ACKE0 bit is set to 1 before the wait state cancellation. * When 9-clock wait is selected (IICC0.WTIM0 bit = 1): ACK is generated if the ACKE0 bit is set to 1 in advance.
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16.5.5 Stop condition When the SCL0 pin is at high level, changing the SDA0 pin from low level to high level generates a stop condition. A stop condition is generated when serial transfer from the master device to the slave device has been completed. Stop conditions can be detected when the device is used as a slave. Figure 16-9. Stop Condition
H SCL0
SDA0
A stop condition is generated when the IICC0.SPT0 bit is set to 1. When the stop condition is detected, the IICS0.SPD0 bit is set to 1 and the interrupt request signal (INTIIC0) is generated when the IICC0.SPIE0 bit is set to 1.
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16.5.6 Wait state The wait state is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL0 pin to low level notifies the communication partner of the wait status. When wait status has been canceled for both the master and slave devices, the next data transfer can begin. Figure 16-10. Wait State (1/2)
(a) When master device has a nine-clock wait and slave device has an eight-clock wait (master: transmission, slave: reception, and IICC0.ACKE0 bit = 1)
Master Master returns to high Wait after output impedance but slave is in wait state (low level). of ninth clock. IIC0 data write (cancel wait)
IIC0
SCL0
6
7
8
9
1
2
3
Slave Wait after output of eighth clock. IIC0 SCL0 FFH is written to IIC0 register or IICC0.WREL0 bit is set to 1.
ACKE0
H
Transfer lines
Wait state from slave 6 7 8 9
Wait state from master 1 2 3
SCL0
SDA0
D2
D1
D0
ACK
D7
D6
D5
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Figure 16-10. Wait State (2/2)
(b) When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKE0 = 1)
Master IIC0 Master and slave both wait after output of ninth clock. IIC0 data write (cancel wait)
SCL0 Slave IIC0 SCL0
6
7
8
9
1
2
3
FFH is written to IIC0 register or WREL0 bit is set to 1.
ACKE0 Transfer lines SCL0
H Wait state from master and slave 6 7 8 9 Wait state from slave 1 2 3
SDA0
D2
D1
D0
ACK
D7
D6
D5
Generated according to previously set ACKE0 bit value
A wait state is automatically generated after a start condition is generated. Moreover, a wait state is automatically generated depending on the setting of the IICC0.WTIM0 bit. Normally, when the IICC0.WREL0 bit is set to 1 or when FFH is written to the IIC0 register, the wait status is canceled and the transmitting side writes data to the IIC0 register to cancel the wait status. The master device can also cancel the wait status via either of the following methods. * By setting the IICC0.STT0 bit to 1 * By setting the IICC0.SPT0 bit to 1
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16.5.7 Wait state cancellation method In the case of I2C0, wait state can be canceled normally in the following ways. * By writing data to the IIC0 register * By setting the IICC0.WREL0 bit to 1 (wait state cancellation) * By setting the IICC0.STT0 bit to 1 (start condition generation)Note * By setting the IICC0.SPT0 bit to 1 (stop condition generation)Note Note Master only If any of these wait state cancellation actions is performed, I2C0 will cancel wait state and restart communication. When canceling wait state and sending data (including address), write data to the IIC0 register. To receive data after canceling wait state, or to complete data transmission, set the WREL0 bit to 1. To generate a restart condition after canceling wait state, set the STT0 bit to 1. To generate a stop condition after canceling wait state, set the SPT0 bit to 1. Execute cancellation only once for each wait state. For example, if data is written to the IIC0 register following wait state cancellation by setting the WREL0 bit to 1, conflict between the SDA0 line change timing and IIC0 register write timing may result in the data output to the SDA0 line may be incorrect. Even in other operations, if communication is stopped halfway, clearing the IICC0.IICE0 bit to 0 will stop communication, enabling wait state to be cancelled. If the I2C bus dead-locks due to noise, etc., setting the IICC0.LREL0 bit to 1 causes the communication operation to be exited, enabling wait state to be cancelled.
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16.6 I2C Interrupt Request Signals (INTIIC0)
The following shows the value of the IICS0 register at the INTIIC0 interrupt request signal generation timing and at the INTIIC0 signal timing. Remark ST: R/W: ACK: D7 to D0: SP: Start condition Transfer direction specification Acknowledge Data Stop condition
AD6 to AD0: Address
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16.6.1 Master device operation (1) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception)
<1> When IICC0.WTIM0 bit = 0
IICC0.SPT0 bit = 1 ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 1000X110B 2: IICS0 register = 1000X000B 3: IICS0 register = 1000X000B (WTIM0 bit = 1 4: IICS0 register = 1000XX00B 5: IICS0 register = 00000001B
Note
D7 to D0
ACK 2
D7 to D0
ACK 3
SP 4 5
)
Note To generate a stop condition, set the WTIM0 bit to 1 and change the timing of the generation of the interrupt request signal (INTIIC0). Remark : X: : Always generated Generated only when IICC0.SPIE0 bit = 1 don't care
<2> When WTIM0 bit = 1
SPT0 bit = 1 ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 1000X110B 2: IICS0 register = 1000X100B 3: IICS0 register = 1000XX00B 4: IICS0 register = 00000001B D7 to D0 ACK 2 D7 to D0 ACK SP 3 4
Remark
: Always generated : Generated only when SPIE0 bit = 1 X: don't care
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(2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart)
<1> When WTIM0 bit = 0
IICC0.STT0 bit = 1 ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 1000X110B 2: IICS0 register = 1000X000B (WTIM0 bit = 1
Note 1
SPT0 bit = 1 R/W ACK 4 D7 to D0 ACK 5 SP 6 7
D7 to D0
ACK 2
ST 3
AD6 to AD0
) )
3: IICS0 register = 1000XX00B (WTIM0 bit = 0 4: IICS0 register = 1000X110B 5: IICS0 register = 1000X000B (WTIM0 bit = 1 6: IICS0 register = 1000XX00B 7: IICS0 register = 00000001B
Note 2
Note 3
)
Notes 1. To generate a start condition, set the WTIM0 bit to 1 and change the timing of the generation of the interrupt request signal (INTIIC0). 2. Clear the WTIM0 bit to 0 to make the settings original. 3. To generate a stop condition, set the WTIM0 bit to 1 and change the timing of the generation of the interrupt request signal (INTIIC0). Remark X: : Always generated : Generated only when SPIE0 bit = 1 don't care
<2> When WTIM0 bit = 1
STT0 bit = 1 ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 1000X110B 2: IICS0 register = 1000XX00B 3: IICS0 register = 1000X110B 4: IICS0 register = 1000XX00B 5: IICS0 register = 00000001B D7 to D0 ACK 2 ST AD6 to AD0 R/W ACK 3 D7 to D0 ACK 4 SPT0 bit = 1 SP 5
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
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(3) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIM0 bit = 0
SPT0 bit = 1 ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 1010X110B 2: IICS0 register = 1010X000B 3: IICS0 register = 1010X000B (WTIM0 bit = 1 4: IICS0 register = 1010XX00B 5: IICS0 register = 00000001B
Note
D7 to D0
ACK 2
D7 to D0
ACK 3
SP 4 5
)
Note To generate a stop condition, set the WTIM0 bit to 1 and change the timing of the generation of the interrupt request signal (INTIIC0). Remark X: : Always generated : Generated only when SPIE0 bit = 1 don't care
<2> When WTIM0 bit = 1
SPT0 bit = 1 ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 1010X110B 2: IICS0 register = 1010X100B 3: IICS0 register = 1010XX00B 4: IICS0 register = 00000001B D7 to D0 ACK 2 D7 to D0 ACK SP 3 4
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
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16.6.2 Slave device operation (when receiving slave address data (address match)) (1) Start ~ Address ~ Data ~ Data ~ Stop
<1> When IICC0.WTIM0 bit = 0
ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 0001X110B 2: IICS0 register = 0001X000B 3: IICS0 register = 0001X000B 4: IICS0 register = 00000001B D7 to D0 ACK 2 D7 to D0 ACK 3 SP 4
Remark X:
: Always generated : Generated only when IICC0.SPIE0 bit = 1 don't care
<2> When WTIM0 bit = 1
ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 0001X110B 2: IICS0 register = 0001X100B 3: IICS0 register = 0001XX00B 4: IICS0 register = 00000001B D7 to D0 ACK 2 D7 to D0 ACK SP 3 4
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
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(2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop
<1> When WTIM0 bit = 0 (after restart, address match)
ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 0001X110B 2: IICS0 register = 0001X000B 3: IICS0 register = 0001X110B 4: IICS0 register = 0001X000B 5: IICS0 register = 00000001B D7 to D0 ACK 2 ST AD6 to AD0 R/W ACK 3 D7 to D0 ACK 4 SP 5
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
<2> When WTIM0 bit = 1 (after restart, address match)
ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 0001X110B 2: IICS0 register = 0001XX00B 3: IICS0 register = 0001X110B 4: IICS0 register = 0001XX00B 5: IICS0 register = 00000001B D7 to D0 ACK ST 2 AD6 to AD0 R/W ACK 3 D7 to D0 ACK 4 SP 5
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
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(3) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop
<1> When WTIM0 bit = 0 (after restart, extension code reception)
ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 0001X110B 2: IICS0 register = 0001X000B 3: IICS0 register = 0010X010B 4: IICS0 register = 0010X000B 5: IICS0 register = 00000001B D7 to D0 ACK 2 ST AD6 to AD0 R/W ACK 3 D7 to D0 ACK 4 SP 5
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
<2> When WTIM0 bit = 1 (after restart, extension code reception)
ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 0001X110B 2: IICS0 register = 0001XX00B 3: IICS0 register = 0010X010B 4: IICS0 register = 0010X110B 5: IICS0 register = 0010XX00B 6: IICS0 register = 00000001B D7 to D0 ACK 2 ST AD6 to AD0 R/W ACK 3 4 D7 to D0 ACK SP 5 6
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
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(4) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop
<1> When WTIM0 bit = 0 (after restart, address mismatch (= not extension code))
ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 0001X110B 2: IICS0 register = 0001X000B 3: IICS0 register = 00000110B 4: IICS0 register = 00000001B D7 to D0 ACK 2 ST AD6 to AD0 R/W ACK 3 D7 to D0 ACK SP 4
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
<2> When WTIM0 bit = 1 (after restart, address mismatch (= not extension code))
ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 0001X110B 2: IICS0 register = 0001XX00B 3: IICS0 register = 00000110B 4: IICS0 register = 00000001B D7 to D0 ACK 2 ST AD6 to AD0 R/W ACK 3 D7 to D0 ACK SP 4
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
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16.6.3 Slave device operation (when receiving extension code) Always under communication when receiving the extension code. (1) Start ~ Code ~ Data ~ Data ~ Stop
<1> When IICC0.WTIM0 bit = 0
ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 0010X010B 2: IICS0 register = 0010X000B 3: IICS0 register = 0010X000B 4: IICS0 register = 00000001B D7 to D0 ACK 2 D7 to D0 ACK 3 SP 4
Remark X:
: Always generated : Generated only when IICC0.SPIE0 bit = 1 don't care
<2> When WTIM0 bit = 1
ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 0010X010B 2: IICS0 register = 0010X110B 3: IICS0 register = 0010X100B 4: IICS0 register = 0010XX00B 5: IICS0 register = 00000001B 2 D7 to D0 ACK 3 D7 to D0 ACK SP 4 5
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
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(2) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop
<1> When WTIM0 bit = 0 (after restart, address match)
ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 0010X010B 2: IICS0 register = 0010X000B 3: IICS0 register = 0001X110B 4: IICS0 register = 0001X000B 5: IICS0 register = 00000001B D7 to D0 ACK 2 ST AD6 to AD0 R/W ACK 3 D7 to D0 ACK 4 SP 5
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
<2> When WTIM0 bit = 1 (after restart, address match)
ST AD6 to AD0 R/W ACK 1 2 D7 to D0 ACK 3 ST AD6 to AD0 R/W ACK 4 D7 to D0 ACK SP 5 6
1: IICS0 register = 0010X010B 2: IICS0 register = 0010X110B 3: IICS0 register = 0010XX00B 4: IICS0 register = 0001X110B 5: IICS0 register = 0001XX00B 6: IICS0 register = 00000001B
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
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(3) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop
<1> When WTIM0 bit = 0 (after restart, extension code reception)
ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 0010X010B 2: IICS0 register = 0010X000B 3: IICS0 register = 0010X010B 4: IICS0 register = 0010X000B 5: IICS0 register = 00000001B D7 to D0 ACK 2 ST AD6 to AD0 R/W ACK 3 D7 to D0 ACK 4 SP 5
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
<2> When WTIM0 bit = 1 (after restart, extension code reception)
ST AD6 to AD0 R/W ACK 1 2 D7 to D0 ACK 3 ST AD6 to AD0 R/W ACK 4 5 D7 to D0 ACK 6 SP 7
1: IICS0 register = 0010X010B 2: IICS0 register = 0010X110B 3: IICS0 register = 0010XX00B 4: IICS0 register = 0010X010B 5: IICS0 register = 0010X110B 6: IICS0 register = 0010XX00B 7: IICS0 register = 00000001B
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
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(4) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop
<1> When WTIM0 bit = 0 (after restart, address mismatch (= not extension code))
ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 0010X010B 2: IICS0 register = 0010X000B 3: IICS0 register = 00000110B 4: IICS0 register = 00000001B D7 to D0 ACK 2 ST AD6 to AD0 R/W ACK 3 D7 to D0 ACK SP 4
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
<2> When WTIM0 bit = 1 (after restart, address mismatch (= not extension code))
ST AD6 to AD0 R/W ACK 1 2 D7 to D0 ACK ST 3 AD6 to AD0 R/W ACK 4 D7 to D0 ACK SP 5
1: IICS0 register = 0010X010B 2: IICS0 register = 0010X110B 3: IICS0 register = 0010XX00B 4: IICS0 register = 00000110B 5: IICS0 register = 00000001B
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
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16.6.4 Operation without communication (1) Start ~ Code ~ Data ~ Data ~ Stop
ST
AD6 to AD0
R/W
ACK
D7 to D0
ACK
D7 to D0
ACK
SP 1
1: IICS0 register = 00000001B
Remark
: Generated only when IICC0.SPIE0 bit = 1
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16.6.5 Arbitration loss operation (operation as slave after arbitration loss) When used as master in the multi-master system, check the arbitration result by reading the IICS0.MSTS0 bit for checking arbitration result by each INTIIC0 interrupt occurrence. (1) When arbitration loss occurs during transmission of slave address data
<1> When IICC0.WTIM0 bit = 0
ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 0101X110B 2: IICS0 register = 0001X000B 3: IICS0 register = 0001X000B 4: IICS0 register = 00000001B D7 to D0 ACK 2 D7 to D0 ACK 3 SP 4
Remark X:
: Always generated : Generated only when IICC0.SPIE0 bit = 1 don't care
<2> When WTIM0 bit = 1
ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 0101X110B 2: IICS0 register = 0001X100B 3: IICS0 register = 0001XX00B 4: IICS0 register = 00000001B D7 to D0 ACK 2 D7 to D0 ACK SP 3 4
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
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(2) When arbitration loss occurs during transmission of extension code
<1> When WTIM0 bit = 0
ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 0110X010B 2: IICS0 register = 0010X000B 3: IICS0 register = 0010X000B 4: IICS0 register = 00000001B D7 to D0 ACK 2 D7 to D0 ACK 3 SP 4
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
<2> When WTIM0 bit = 1
ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 0110X010B 2: IICS0 register = 0010X110B 3: IICS0 register = 0010X100B 4: IICS0 register = 0010XX00B 5: IICS0 register = 00000001B 2 D7 to D0 ACK 3 D7 to D0 ACK SP 4 5
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
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16.6.6 Operation when arbitration loss occurs (no communication after arbitration loss) When used as master in the multi-master system, check the arbitration result by reading the IICS0.MSTS0 bit for checking arbitration result by each INTIIC0 interrupt occurrence. (1) When arbitration loss occurs during transmission of slave address data
ST
AD6 to AD0
R/W
ACK 1
D7 to D0
ACK
D7 to D0
ACK
SP 2
1: IICS0 register = 01000110B 2: IICS0 register = 00000001B
Remark
: Always generated : Generated only when IICC0.SPIE0 bit = 1
(2) When arbitration loss occurs during transmission of extension code
ST
AD6 to AD0
R/W
ACK 1
D7 to D0
ACK
D7 to D0
ACK
SP 2
1:
IICS0 register = 0110X010B
IICC0.LREL0 bit is set to 1 by software 2: IICS0 register = 00000001B
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
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(3) When arbitration loss occurs during data transfer
<1> When IICC0.WTIM0 bit = 0
ST
AD6 to AD0
R/W
ACK 1
D7 to D0
ACK 2
D7 to D0
ACK
SP 3
1: IICS0 register = 10001110B 2: IICS0 register = 01000000B 3: IICS0 register = 00000001B
Remark
: Always generated : Generated only when SPIE0 bit = 1
<2> When WTIM0 bit = 1
ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 10001110B 2: IICS0 register = 01000100B 3: IICS0 register = 00000001B D7 to D0 ACK 2 D7 to D0 ACK SP 3
Remark
: Always generated : Generated only when SPIE0 bit = 1
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(4) When arbitration loss occurs due to restart condition during data transfer
<1> Not extension code (Example: Address mismatch)
ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 1000X110B 2: IICS0 register = 01000110B 3: IICS0 register = 00000001B D7 to Dn ST AD6 to AD0 R/W ACK 2 D7 to D0 ACK SP 3
Remarks 1.
: Always generated : Generated only when SPIE0 bit = 1 X: don't care
2. Dn = D6 to D0 <2> Extension code
ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 1000X110B 2: IICS0 register = 0110X010B IICC0.LREL0 bit is set to 1 by software 3: IICS0 register = 00000001B D7 to Dn ST AD6 to AD0 R/W ACK 2 D7 to D0 ACK SP 3
Remarks 1.
: Always generated : Generated only when SPIE0 bit = 1 X: don't care
2. Dn = D6 to D0
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(5) When arbitration loss occurs due to stop condition during data transfer
ST
AD6 to AD0
R/W
ACK 1
D7 to Dn
SP 2
1: IICS0 register = 1000X110B 2: IICS0 register = 01000001B
Remarks 1.
: Always generated : Generated only when SPIE0 bit = 1 X: don't care
2. Dn = D6 to D0
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(6) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a restart condition
<1> When WTIM0 bit = 0
IICC0.STT0 bit = 1 ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 1000X110B 2: IICS0 register = 1000X000B (WTIM0 bit = 1) 3: IICS0 register = 1000X100B (WTIM0 bit = 0) 4: IICS0 register = 01000000B 5: IICS0 register = 00000001B D7 to D0 ACK 2 3 D7 to D0 ACK 4 D7 to D0 ACK SP 5
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
<2> When WTIM0 bit = 1
IICC0.STT0 bit = 1 ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 1000X110B 2: IICS0 register = 1000X100B 3: IICS0 register = 01000100B 4: IICS0 register = 00000001B D7 to D0 ACK 2 D7 to D0 ACK 3 D7 to D0 ACK SP 4
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
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(7) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition
<1> When WTIM0 bit = 0
STT0 bit = 1 ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 1000X110B 2: IICS0 register = 1000X000B (WTIM0 bit = 1) 3: IICS0 register = 1000XX00B 4: IICS0 register = 01000001B D7 to D0 ACK 2 3 SP 4
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
<2> When WTIM0 bit = 1
STT0 bit = 1 ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 1000X110B 2: IICS0 register = 1000XX00B 3: IICS0 register = 01000001B D7 to D0 ACK 2 SP 3
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
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(8) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a stop condition
<1> When WTIM0 bit = 0
IICC0.SPT0 bit = 1 ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 1000X110B 2: IICS0 register = 1000X000B (WTIM0 bit = 1) 3: IICS0 register = 1000X100B (WTIM0 bit = 0) 4: IICS0 register = 01000100B 5: IICS0 register = 00000001B D7 to D0 ACK 2 3 D7 to D0 ACK 4 D7 to D0 ACK SP 5
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
<2> When WTIM0 bit = 1
IICC0.SPT0 bit = 1 ST AD6 to AD0 R/W ACK 1 1: IICS0 register = 1000X110B 2: IICS0 register = 1000X100B 3: IICS0 register = 01000100B 4: IICS0 register = 00000001B D7 to D0 ACK 2 D7 to D0 ACK 3 D7 to D0 ACK SP 4
Remark X:
: Always generated : Generated only when SPIE0 bit = 1 don't care
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16.7 Interrupt Request Signal (INTIIC0) Generation Timing and Wait Control
The setting of the IICC0.WTIM0 bit determines the timing by which the INTIIC0 signal is generated and the corresponding wait control, as shown below. Table 16-3. INTIIC0 Signal Generation Timing and Wait Control
WTIM0 Bit During Slave Device Operation Address 0 1 9 9
Notes 1, 2
During Master Device Operation Address 9 9 Data Reception 8 9 Data Transmission 8 9
Data Reception 8 9
Note 2
Data Transmission 8 9
Note 2
Notes 1, 2
Note 2
Note 2
Notes 1.
The slave device's INTIIC0 signal and wait period occurs at the falling edge of the ninth clock only when there is a match with the address set to the SVA0 register. At this point, ACK is generated regardless of the value set to the IICC0.ACKE0 bit. For a slave device that has received an extension code, the INTIIC0 signal occurs at the falling edge of the eighth clock. When the address does not match after restart, the INTIIC0 signal is generated at the falling edge of the ninth clock, but no wait occurs.
2.
If the received address does not match the contents of the SVA0 register and extension codes have not been received, neither the INTIIC0 signal nor a wait occurs.
Remark The numbers in the table indicate the number of the serial clock's clock signals. Interrupt requests and wait control are both synchronized with the falling edge of these clock signals. (1) During address transmission/reception * Slave device operation: * Master device operation: Interrupt and wait timing are determined depending on the conditions in Notes 1 and 2 above regardless of the WTIM0 bit. Interrupt and wait timing occur at the falling edge of the ninth clock regardless of the WTIM0 bit. (2) During data reception * Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit. (3) During data transmission * Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
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(4) Wait cancellation method The four wait cancellation methods are as follows. * By writing data to the IIC0 register * By setting the IICC0.WREL0 bit (canceling wait state) * By setting the IICC0.STT0 bit (generating start condition)Note * By setting the IICC0.SPT0 bit (generating stop condition)Note Note Master only When an 8-clock wait has been selected (WTIM0 bit = 0), whether or not ACK has been generated must be determined prior to wait cancellation. (5) Stop condition detection The INTIIC0 signal is generated when a stop condition is detected.
16.8 Address Match Detection Method
When in I2C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match detection is performed automatically by hardware. An INTIIC0 interrupt request signal occurs when a local address has been set to the SVA0 register and when the address set to the SVA0 register matches the slave address sent by the master device, or when an extension code has been received.
16.9 Error Detection
In I2C bus mode, the status of the serial data bus (SDA0) during data transmission is captured by the IIC0 register of the transmitting device, so the IIC0 register data prior to transmission can be compared with the transmitted IIC0 register data to enable detection of transmission errors. A transmission error is judged as having occurred when the compared data values do not match.
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16.10 Extension Code
(1) When the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (EXC0) is set for extension code reception and an interrupt request signal (INTIIC0) is issued at the falling edge of the eighth clock. The local address stored in the SVA0 register is not affected. (2) If 11110xx0 is set to the SVA0 register by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follows. Note that the INTIIC0 signal occurs at the falling edge of the eighth clock. * Higher 4 bits of data match: IICS0.EXC0 bit = 1 * 7 bits of data match: IICS0.COI0 bit = 1 (3) Since the processing after the INTIIC0 signal occurs differs according to the data that follows the extension code, such processing is performed by software. The slave that has received an extension code is always under communication, even if the addresses mismatch. For example, when operation as a slave is not desired after the extension code is received, set the IICC0.LREL0 bit to 1 and the CPU will enter the next communication wait state. Table 16-4. Extension Code Bit Definitions
Slave Address 0000 0000 0000 0000 1111 000 000 001 010 0xx R/W Bit 0 1 X X X General call address Start byte CBUS address Address that is reserved for different bus format 10-bit slave address specification Description
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16.11 Arbitration
When several master devices simultaneously generate a start condition (when the IICC0.STT0 bit is set to 1 before the IICS0.STD0 bit is set to 1), communication among the master devices is performed as the number of clocks is adjusted until the data differs. This kind of operation is called arbitration. When one of the master devices loses in arbitration, an arbitration loss flag (IICS0.ALD0 bit) is set (1) via the timing by which the arbitration loss occurred, and the SCL0 and SDA0 lines are both set for high impedance, which releases the bus. The arbitration loss is detected based on the timing of the next interrupt request signal (INTIIC0) (the eighth or ninth clock, when a stop condition is detected, etc.) and the ALD0 bit = 1 setting that has been made by software. For details of interrupt request timing, refer to 16.6 I2C Interrupt Request Signals (INTIIC0). Figure 16-11. Arbitration Timing Example
Master 1 SCL0 Hi-Z
SDA0 Master 2 SCL0
Hi-Z Master 1 loses arbitration
SDA0 Transfer lines SCL0
SDA0
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Table 16-5. Status During Arbitration and Interrupt Request Generation Timing
Status During Arbitration During address transmission Read/write data after address transmission During extension code transmission Read/write data after extension code transmission During data transmission During ACK transfer period after data reception When restart condition is detected during data transfer When stop condition is detected during data transfer When the SDA0 pin is at low level while attempting to generate a restart condition When stop condition is detected while attempting to generate a restart condition When the SDA0 pin is at low level while attempting to generate a stop condition When the SCL0 pin is at low level while attempting to generate a restart condition At falling edge of eighth or ninth clock following byte transfer
Note 1
Interrupt Request Generation Timing At falling edge of eighth or ninth clock following byte transfer
Note 1
When stop condition is generated (when IICC0.SPIE0 bit = 1) At falling edge of eighth or ninth clock following byte transfer
Note 2
Note 2
Note 1
When stop condition is generated (when SPIE0 bit = 1)
Notes 1.
When the IICC0.WTIM0 bit = 1, an interrupt request occurs at the falling edge of the ninth clock. When the WTIM0 bit = 0 and the extension code's slave address is received, an interrupt request occurs at the falling edge of the eighth clock.
2.
When there is a possibility that arbitration will occur, set the SPIE0 bit = 1 for master device operation.
16.12 Wakeup Function
The I2C bus slave function is a function that generates an interrupt request signal (INTIIC0) when a local address or extension code has been received. This function makes processing more efficient by preventing unnecessary interrupt requests from occurring when addresses do not match. When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has generated a start condition) to a slave device. However, when a stop condition is detected, the IICC0.SPIE0 bit is set regardless of the wake up function, and this determines whether interrupt requests are enabled or disabled.
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16.13 Communication Reservation
16.13.1 When communication reservation function is enabled (IICF0.IICRSV0 bit = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used. * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released when the IICC0.LREL0 bit was set to "1"). If the IICC0.STT0 bit is set (1) while the bus is not used, a start condition is automatically generated and wait status is set after the bus is released (after a stop condition is detected). A communication is automatically started as the master by setting the IICC0.SPIE0 bit to 1, detecting the bus release due to an interrupt request (INTIIC0) occurrence (detecting a stop condition), and then writing the address to the IIC0 register. Before detecting a stop condition, data written to the IIC0 register is set to invalid. When the STT0 bit has been set (1), the operation mode (as start condition or as communication reservation) is determined according to the bus status. If the bus has been released.............................................. a start condition is generated If the bus has not been released (standby mode) .............. communication reservation To detect which operation mode has been determined for the STT0 bit, set the STT0 bit (1), wait for the wait period, then check the IICS0.MSTS0 bit. Wait periods, which should be set via software, are listed in Table 16-6. These wait periods can be set via the settings for the IICX0.CLX0, IICCL0.SMC0, IICCL0.CL01, and IICCL0.CL00 bits. Table 16-6. Wait Periods
CLX0 0 0 0 0 0 0 0 1 1 SMC0 0 0 0 0 1 1 1 1 1 CL01 0 0 1 1 0 1 1 0 1 CL00 0 1 0 1 1/0 0 1 1/0 0 Selected Clock fXX/2 fXX/2 fXX fXX/3 fXX/2 fXX fXX/3 fXX/2 fXX Wait Period 46 clocks 86 clocks 43 clocks 102 clocks 30 clocks 15 clocks 36 clocks 18 clocks 9 clocks
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The communication reservation timing is shown below. Figure 16-12. Communication Reservation Timing
Program processing STT0=1
Write to IIC0
Hardware processing
Communication reservation
Set SPD0 and INTIIC0
Set STD0
SCL0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
SDA0
Generated by master with bus access
IIC0: STT0: STD0: SPD0:
IIC shift register 0 Bit 1 of IIC control register 0 (IICC0) Bit 1 of IIC status register 0 (IICS0) Bit 0 of IIC status register 0 (IICS0)
Communication reservations are accepted via the following timing.
After the IICS0.STD0 bit is set to 1, a
communication reservation can be made by setting the IICC0.STT0 bit to 1 before a stop condition is detected. Figure 16-13. Timing for Accepting Communication Reservations
SCL0
SDA0
STD0
SPD0
Standby mode
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The communication reservation flowchart is illustrated below. Figure 16-14. Communication Reservation Flowchart
DI
STT0 = 1
; Sets STT0 flag (communication reservation).
Define communication reservation
; Defines that communication reservation is in effect (defines and sets user flag to any part of RAM).
Wait
; Gets wait period set by software (refer to Table 16-6).
Note
(Communication reservation) Yes MSTS0 = 0?
; Confirmation of communication reservation
No (Generate start condition) Cancel communication reservation ; Clear user flag.
IIC0 xxH
; IIC0 write operation
EI
Note The communication reservation operation executes a write to the IIC0 register when a stop condition interrupt request occurs.
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16.13.2 When communication reservation function is disabled (IICF0.IICRSV0 bit = 1) When the IICC0.STT0 bit is set when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. The following two statuses are included in the status where bus is not used. * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released when the IICC0.LREL0 bit was set to 1) To confirm whether the start condition was generated or request was rejected, check the IICF0.STCF0 flag. The time shown in Table 16-7 is required until the STCF0 flag is set after setting the STT0 bit = 1. Therefore, secure the time by software. Table 16-7. Wait Periods
CL01 0 0 1 1 CL00 0 1 0 1 Selected Clock fXX/2 fXX/2 fXX fXX/3 Wait Period 6 clocks 6 clocks 3 clocks 9 clocks
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16.14 Cautions
(1) When IICF0.STCEN0 bit = 0 Immediately after I2C0 operation is enabled, the bus communication status (IICF0.IICBSY0 bit = 1) is recognized regardless of the actual bus status. To execute master communication in the status where a stop condition has not been detected, generate a stop condition and then release the bus before starting the master communication. Use the following sequence for generating a stop condition. <1> Set the IICCL0 register. <2> Set the IICC0.IICE0 bit. <3> Set the IICC0.SPT0 bit. (2) When IICF0.STCEN0 bit = 1 Immediately after I2C0 operation is enabled, the bus released status (IICBSY0 bit = 0) is recognized regardless of the actual bus status. To generate the first start condition (IICC0.STT0 bit = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. (3) When the IICC0.IICE0 bit of the V850ES/KE2 is set to 1 while communications with other devices are in progress, the start condition may be detected depending on the status of the communication line. Be sure to set the IICC0.IICE0 bit to 1 when the SCL0 and SDA0 lines are high level. (4) Determine the operation clock frequency by the IICCL0 and IICX0 registers before enabling the operation (IICC0.IICE0 bit = 1). To change the operation clock frequency, clear the IICC0.IICE0 bit to 0 once. (5) After the IICC0.STT0 and IICC0.SPT0 bits have been set to 1, they must not be re-set without being cleared to 0 first. (6) If transmission has been reserved, set the IICC0.SPIE0 bit to 1 so that an interrupt request is generated by the detection of a stop condition. After an interrupt request has been generated, the wait state will be released by writing communication data to I2C0, then transferring will begin. If an interrupt is not generated by the detection of a stop condition, transmission will halt in the wait state because an interrupt request was not generated. However, it is not necessary to set the SPIE0 bit to 1 for the software to detect the IICS0.MSTS0 bit.
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16.15 Communication Operations
The following shows three operation procedures with the flowchart. (1) Master operation in single master system The flowchart when using the V850ES/KE2 as the master in a single master system is shown below. This flowchart is broadly divided into the initial settings and communication processing. Execute the initial settings at startup. If communication with the slave is required, prepare the communication and then execute communication processing. (2) Master operation in multimaster system In the I2C0 bus multimaster system, whether the bus is released or used cannot be judged by the I2C bus specifications when the bus takes part in a communication. Here, when data and clock are at a high level for a certain period (1 frame), the V850ES/KE2 takes part in a communication with bus released state. This flowchart is broadly divided into the initial settings, communication waiting, and communication processing. The processing when the V850ES/KE2 looses in arbitration and is specified as the slave is omitted here, and only the processing as the master is shown. slave. Execute the initial settings at startup to take part in a communication. Then, wait for the communication request as the master or wait for the specification as the The actual communication is performed in the communication processing, and it supports the transmission/reception with the slave and the arbitration with other masters. (3) Slave operation An example of when the V850ES/KE2 is used as the slave is shown below. When used as the slave, operation is started by an interrupt. Execute the initial settings at startup, then wait for the INTIIC0 interrupt occurrence (communication waiting). When the INTIIC0 interrupt occurs, the communication status is judged and its result is passed as a flag over to the main processing. By checking the flags, necessary communication processing is performed.
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16.15.1 Master operation in single master system Figure 16-15. Master Operation in Single Master System
START Initialize I2C busNote Set ports IICX0 0XH IICCL0 XXH SVA0 XXH
Initial settings
Refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions to set the I2C mode before this function is used. Transfer clock selection Local address setting Start condition setting
IICF0 0XH Set STCEN0, IICRSV0 = 0 IICC0 XXH ACKE0 = WTIM0 = SPIE0 = 1 IICE0 = 1
STCEN0 = 1? No SPT0 = 1
Yes
Communication start preparation (stop condition generation)
INTIIC0 interrupt occurred? Yes
No Waiting for stop condition detection
STT0 = 1
Communication start preparation (start condition generation) Communication start (address, transfer direction specification)
Write IIC0
INTIIC0 interrupt occurred? Yes No ACKD0 = 1? Yes
Communication processing
No Waiting for ACK detection
TRC0 = 1? Yes Write IIC0
No ACKE0 = 1 WTIM0 = 0 Transmission start
WREL0 = 1
Reception start
INTIIC0 interrupt occurred? Yes
No Waiting for data transmission
INTIIC0 interrupt occurred? Yes
No Waiting for data reception
ACKD0 = 1? Yes No
No
Read IIC0
Transfer completed? Transfer completed? Yes Yes ACKE0 = 0 WTIM0 = WREL0 = 1 No SPT0 = 1 END INTIIC0 interrupt occurred? Yes
No
Restarted? Yes
No Waiting for ACK detection
2 Note Release the I C0 bus (SCL0, SDA0 pins = high level) in conformity with the specifications of the product
in communication. For example, when the EEPROMTM outputs a low level to the SDA0 pin, set the SCL0 pin to the output port and output clock pulses from that output port until when the SDA0 pin is constantly high level. Remark For the transmission and reception formats, conform to the specifications of the product in communication.
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16.15.2 Master operation in multimaster system Figure 16-16. Master Operation in Multimaster System (1/3)
START Refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions to set the I2C mode before this function is used. Transfer clock selection
Set ports IICX0 0XH IICCL0 XXH SVA0 XXH IICF0 0XH Set STCEN0, IICRSV0 = 0 IICC0 XXH ACKE0 = WTIM0 = SPIE0 = 1 IICE0 = 1
Local address setting
Start condition setting
Initial settings
Confirm bus statusNote
Bus release status for a certain period
Confirmation of bus status is in progress No INTIIC0 interrupt occurred? Yes No
STCEN0 = 1? Yes
No SPT0 = 1 Communication start preparation (stop condition generation)
SPD0 = 1? Yes
INTIIC0 interrupt occurred? Yes
No Waiting for stop condition detection
Slave operation SPD0 = 1? Yes
No
Slave operation
1
* Waiting for slave specification from another master * Waiting for communication start request (depending on user program)
Communication processing
Master operation started?
No (no communication start request) SPIE0 = 0
Yes (communication start request issued) SPIE0 = 1
INTIIC0 interrupt occurred? Yes
No Waiting for communication request
IICRSV0 = 0? Yes A
No
Slave operation
B
Communication Communication reservation enable reservation disable
Note Confirm that the bus release status (IICCL0.CLD0 bit = 1, IICCL0.DAD0 bit = 1) has been maintained for a certain period (1 frame, for example). When the SDA0 pin is constantly low level, determine whether to release the I2C0 bus (SCL0, SDA0 pins = high level) by referring to the specifications of the product in communication.
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Figure 16-16. Master Operation in Multimaster System (2/3)
A
Communication reservation enabled
STT0 = 1
Communication start preparation (start condition generation) Securing wait time by software (refer to Table 16-6)
Communication processing
Wait
MSTS0 = 1? Yes
No
INTIIC0 interrupt occurred? Yes No Wait status after stop condition detection and start condition generation by communication reservation function
No Waiting for bus release (communication reserved)
EXC0 = 1 or COI0 =1? Yes Slave operation
C
B
Communication reservation disabled
IICBSY0 = 0? Yes
No
D
Communication processing
STT0 = 1
Communication start preparation (start condition generation) Securing wait time by software (refer to Table 16-7)
Wait
STCF0 = 0? Yes
No
INTIIC0 interrupt occurred? Yes
No Waiting for bus release
C EXC0 = 1 or COI0 =1? No D Yes
Stop condition detection Slave operation
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Figure 16-16. Master Operation in Multimaster System (3/3)
C Communication start (address, transfer direction specification)
Write IIC0
INTIIC0 interrupt occurred? Yes MSTS0 = 1? Yes No ACKD0 = 1? Yes TRC0 = 1?
Communication processing
No Waiting for ACK detection
No
2
No ACKE0 = 1 WTIM0 = 0
Yes WTIM0 = 1
WREL0 = 1 Write IIC0 Transmission start INTIIC0 interrupt occurred? INTIIC0 interrupt occurred? Yes MSTS0 = 1? Yes ACKD0 = 1? Yes Yes No Transfer completed? Yes INTIIC0 interrupt occurred? Restarted? Yes STT0 = 1 No Yes SPT0 = 1 MSTS0 = 1? END Yes C WTIM0 = WREL0 = 1 ACKE0 = 0 No Transfer completed? No Yes 2 Read IIC0 No Waiting for data transmission Yes MSTS0 = 1?
Reception start
No Waiting for data transmission No
2
No
No Waiting for ACK detection
No 2
Communication processing
2
EXC0 = 1 or COI0 = 1? No 1 Not in communication
Yes
Slave operation
Remarks 1. Conform the transmission and reception formats to the specifications of the product in communication. 2. When using the V850ES/KE2 as the master in the multimaster system, read the IICS0.MSTS0 bit for each INTIIC0 interrupt occurrence to confirm the arbitration result. 3. When using the V850ES/KE2 as the slave in the multimaster system, confirm the status using the IICS0 and IICF0 registers for each INTIIC0 interrupt occurrence to determine the next processing.
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16.15.3 Slave operation The following shows the processing procedure of the slave operation. Basically, the operation of the slave device is event-driven. communication) is necessary. The following description assumes that data communication does not support extension codes. Also, it is assumed that the INTIIC0 interrupt servicing performs only status change processing and that the actual data communication is performed during the main processing. Figure 16-17. Software Outline During Slave Operation Therefore, processing by an INTIIC0 interrupt (processing requiring a significant change of the operation status, such as stop condition detection during
INTIIC0 Interrupt servicing Setting, etc. I2C Data Setting, etc.
Flag
Main processing
Therefore, the following three flags are prepared so that the data transfer processing can be performed by transmitting these flags to the main processing instead of the INTIIC0 signal. (1) Communication mode flag This flag indicates the following communication statuses. Clear mode: Data communication not in progress ACK from master not detected, address mismatch) (2) Ready flag This flag indicates that data communication is enabled. This is the same status as an INTIIC0 interrupt during normal data transfer. This flag is set in the interrupt processing block and cleared in the main processing block. The ready flag for the first data for transmission is not set in the interrupt processing block, so the first data is transmitted without clearance processing (the address match is regarded as a request for the next data). (3) Communication direction flag This flag indicates the direction of communication and is the same as the value of the IICS0.TRC0 bit. The following shows the operation of the main processing block during slave operation. Start I2C0 and wait for the communication enabled status. When communication is enabled, perform transfer using the communication mode flag and ready flag (the processing of the stop condition and start condition is performed by interrupts, conditions are confirmed by flags). For transmission, repeat the transmission operation until the master device stops returning ACK. When the master device stops returning ACK, transfer is complete. Communication mode: Data communication in progress (valid address detection stop condition detection,
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For reception, receive the required number of data and do not return ACK for the next data immediately after transfer is complete. After that, the master device generates the stop condition or restart condition. This causes exit from communications. Figure 16-18. Slave Operation Flowchart (1)
START
Set ports
Refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions to set the I2C mode before this function is used.
IICX0 0XH
Initial settings
IICCL0 XXH
Transfer clock selection
SVA0 XXH
Local address setting
IICF0 0XH Set IICRSV0 IICC0 XXH ACKE0 = WTIM0 = 1 SPIE0 = 0, IICE0 = 1
Start condition setting
No
Communication mode flag = 1? Yes No Communication direction flag = 1? Yes WREL0 = 1 Write IIC0 Transmission start Communication mode flag = 1? Communication mode flag = 1? Yes Yes Communication direction flag = 1? Yes No No Ready flag = 1? Yes Yes Read IIC0 Clear ready flag Clear ready flag Ready flag = 1? No No Reception start
Communication processing
No
No
Communication direction flag = 1? Yes
Yes ACKD0 = 1? No Clear communication mode flag WREL0 = 1
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The following shows an example of the processing of the slave device by an INTIIC0 interrupt (it is assumed that no extension codes are used here). During an INTIIC0 interrupt, the status is confirmed and the following steps are executed. <1> When a stop condition is detected, communication is terminated. <2> When a start condition is detected, the address is confirmed. If the address does not match, communication is terminated. If the address matches, the communication mode is set and wait is released, and operation returns from the interrupt (the ready flag is cleared). <3> For data transmission/reception, when the ready flag is set, operation returns from the interrupt while the I2C0 bus remains in the wait status. Remark <1> to <3> in the above correspond to <1> to <3> in Figure 16-19 Slave Operation Flowchart (2). Figure 16-19. Slave Operation Flowchart (2)
INTIIC0 occurred
Yes SPD0 = 1? No
<1>
Yes STD0 = 1? No <3> Set ready flag
<2>
No COI0 = 1? Yes
Communication direction flag TRC0 Set communication mode flag Clear ready flag
Clear communication direction flag, ready flag, and communication mode flag
Interrupt servicing completed
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16.16 Timing of Data Communication
When using I2C bus mode, the master device generates an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the IICS0.TRC0 bit that specifies the data transfer direction and then starts serial communication with the slave device. The IIC0 register's shift operation is synchronized with the falling edge of the serial clock (SCL0 pin). The transmit data is transferred to the SO latch and is output (MSB first) via the SDA0 pin. Data input via the SDA0 pin is captured by the IIC0 register at the rising edge of the SCL0 pin. The data communication timing is shown below.
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Figure 16-20. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3)
(a) Start condition ~ address
Processing by master device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 H Transmit L L H H IIC0 address IIC0 data
Transfer lines SCL0 SDA0 1 2 3 4 5 6 7 8 W 9 ACK 1 D7 2 D6 3 D5 4 D4
AD6 AD5 AD4 AD3 AD2 AD1 AD0 Start condition
Processing by slave device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 (when EXC0 = 1) TRC0 L Receive H H L L L Note IIC0 FFH Note
Note To cancel slave wait, write FFH to IIC0 or set WREL0.
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Figure 16-20. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3)
(b) Data
Processing by master device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 H Transmit L L H H H L L L IIC0 data IIC0 data
Transfer lines SCL0 SDA0 8 D0 9 ACK 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 D5
Processing by slave device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 L Receive L L H H L L L Note Note IIC0 FFH Note IIC0 FFH Note
Note To cancel slave wait, write FFH to IIC0 or set WREL0.
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Figure 16-20. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3)
(c) Stop condition
Processing by master device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 (when SPIE0 = 1) TRC0 H Transmit L H H IIC0 data IIC0 address
Transfer lines SCL0 SDA0 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 ACK Stop condition IIC0 FFH Note 1 2
AD6 AD5 Start condition
Processing by slave device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 H H L L L Note IIC0 FFH Note
Note
(when SPIE0 = 1) TRC0 L Receive
Note To cancel slave wait, write FFH to IIC0 or set WREL0.
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Figure 16-21. Example of Slave to Master Communication (When 8-Clock Wait for Master and 9-Clock Wait for Slave Are Selected) (1/3)
(a) Start condition ~ address
Processing by master device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 Transfer lines SCL0 SDA0 1 2 3 4 5 6 7 8 R 9 ACK 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 L Note L H IIC0 address IIC0 FFH Note
AD6 AD5 AD4 AD3 AD2 AD1 AD0 Start condition
Processing by slave device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 H H L L L L IIC0 data
Note To cancel master wait, write FFH to IIC0 or set WREL0.
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Figure 16-21. Example of Slave to Master Communication (When 8-Clock Wait for Master and 9-Clock Wait for Slave Are Selected) (2/3)
(b) Data
Processing by master device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 L Receive L L L H H L L Note Note IIC0 FFH Note IIC0 FFH Note
Transfer lines SCL0 SDA0 8 D0 9 ACK 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 D5
Processing by slave device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 H Transmit L L H H L L L L IIC0 data IIC0 data
Note To cancel master wait, write FFH to IIC0 or set WREL0.
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Figure 16-21. Example of Slave to Master Communication (When 8-Clock Wait for Master and 9-Clock Wait for Slave Are Selected) (3/3)
(c) Stop condition
Processing by master device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 (when SPIE0 = 1) TRC0 Transfer lines SCL0 SDA0 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 NACK Stop condition 1 AD6 Start condition Note IIC0 FFH Note IIC0 address
Processing by slave device IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 H H L L L IIC0 data
(when SPIE0 = 1) TRC0
Note To cancel master wait, write FFH to IIC0 or set WREL0.
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17.1 Overview
The V850ES/KE2 is provided with a dedicated interrupt controller (INTC) for interrupt servicing and realize an interrupt function that can service interrupt requests from a total of 35 sources. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution. The V850ES/KE2 can process interrupt requests from the on-chip peripheral hardware and external sources. Moreover, exception processing can be started by the TRAP instruction (software exception) or by generation of an exception event (fetching of an illegal opcode) (exception trap). 17.1.1 Features
Interrupt Source Interrupt function Non-maskable interrupt Maskable interrupt External Internal External Internal WDT1 TMP TM0 TMH TM5 WT BRG UART CSI0 IIC KR AD Total Exception function Exception trap Software exception 1 channel (NMI pin) 2 channels (WDT1, WDT2) 8 channels (all edge detection interrupts) 1 channel 3 channels 2 channels 2 channels 2 channels 2 channels 1 channel 6 channels 2 channels 1 channel 1 channel 1 channel 24 channels 16 channels (TRAP00H to TRAP0FH) 16 channels (TRAP10H to TRAP1FH) 2 channels (ILGOP/DBG0) V850ES/KE2
Table 17-1 lists the interrupt/exception sources.
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Table 17-1. Interrupt Source List (1/2)
Type Classification Default Priority Name Trigger Interrupt Exception Source Code Handler Address Restored Interrupt PC Control Register Reset Interrupt - RESET RESET pin input Internal reset input from WDT1, WDT2 Nonmaskable Interrupt - - NMI INTWDT1 NMI pin valid edge input WDT1 overflow (when nonmaskable interrupt selected) - INTWDT2
Note 2
Pin WDT1 WDT2 Pin WDT1
0000H
00000000H
Undefined
-
0010H 0020H
00000010H 00000020H
nextPC Note 1
- -
WDT2 overflow (when nonmaskable interrupt selected)
WDT2
0030H
Note 2
00000030H
Note 1
-
Software exception
Exception
- - -
TRAP0n TRAP1n ILGOP/ DBG0
TRAP instruction TRAP instruction Illegal opcode/DBTRAP instruction
- - -
004nH 005nH
00000040H 00000050H 00000060H
nextPC nextPC nextPC
- - -
Note 2
Note 2
Exception Exception trap Maskable Interrupt
0060H
0
INTWDTM1 WDT1 overflow (when interval WDT1 timer selected)
0080H
00000080H
nextPC
WDT1IC
1 2 3 4 5 6 7 10 11 12 13 14 15 16
INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTTM010 INTTM011 INTTM50 INTTM51 INTCSI00 INTCSI01 INTSRE0
INTP0 pin valid edge input INTP1 pin valid edge input INTP2 pin valid edge input INTP3 pin valid edge input INTP4 pin valid edge input INTP5 pin valid edge input INTP6 pin valid edge input TM01 and CR010 match TM01 and CR011 match TM50 and CR50 match TM51 and CR51 match CSI00 transfer completion CSI01 transfer completion UART0 reception error occurrence
Pin Pin Pin Pin Pin Pin Pin TM01 TM01 TM50 TM51 CSI00 CSI01 UART0
0090H 00A0H 00B0H 00C0H 00D0H 00E0H 00F0H 0120H 0130H 0140H 0150H 0160H 0170H 0180H
00000090H
nextPC
PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 TM0IC10 TM0IC11 TM5IC0 TM5IC1 CSI0IC0 CSI0IC1 SREIC0
000000A0H nextPC 000000B0H nextPC 000000C0H nextPC 000000D0H nextPC 000000E0H nextPC 000000F0H nextPC 00000120H 00000130H 00000140H 00000150H 00000160H 00000170H 00000180H nextPC nextPC nextPC nextPC nextPC nextPC nextPC
17 18
INTSR0 INTST0
UART0 reception completion UART0 transmission completion
UART0 UART0
0190H 01A0H
00000190H 000001AH
nextPC nextPC
SRIC0 STIC0
19
INTSRE1
UART1 reception error occurrence
UART1
01B0H
000001B0H nextPC
SREIC1
20 21
INTSR1 INTST1
UART1 reception completion UART1 transmission completion
UART1 UART1
01C0H 01D0H
000001C0H nextPC 000001D0H nextPC
SRIC1 STIC1
Notes 1. For restoration in the case of INTWDT1 and INTWDT2, refer to 17.10 Cautions. 2. n = 0 to FH
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Table 17-1. Interrupt Source List (2/2)
Type Classification Default Priority Name Trigger Interrupt Exception Source Code Handler Address Restored Interrupt PC Control Register Maskable Interrupt 22 INTTMH0 TMH0 and CMP00/CMP01 match 23 INTTMH1 TMH1 and CMP10/CMP11 match 25 26 27 28 29 30 INTIIC0 INTAD INTKR INTWTI INTWT INTBRG I C0 transfer completion A/D conversion completion Key return interrupt Watch timer interval Watch timer reference time 8-bit counter of prescaler 3 and PRSCM match 45 46 47 INTP7 INTP7 pin valid edge input Pin TMP TMP 0390H 03A0H 03B0H 00000390H nextPC PIC7 TP0OVIC TP0CCIC0
2
TMH0
01E0H
000001E0H nextPC
TMHIC0
TMH1
01F0H
000001F0H nextPC
TMHIC1
I C0 A/D KR WT WT
Prescaler 3
2
0210H 0220H 0230H 0240H 0250H 0260H
00000210H 00000220H 00000230H 00000240H 00000250H 00000260H
nextPC nextPC nextPC nextPC nextPC nextPC
IICIC0 ADIC KRIC WTIIC WTIC BRGIC
INTTP0OV TMP0 overflow INTTP0CC0 TMP0 capture 0/ compare 0 match
000003A0H nextPC 000003B0H nextPC
48
INTTP0CC1 TMP0 capture 1/ compare 1 match
TMP
03C0H
000003C0H nextPC
TP0CCIC1
Remarks 1. Default priority: The priority order when two or more maskable interrupt requests with the same priority level are generated at the same time. The highest priority is 0. The priority of non-maskable interrupt request is as follows. INTWDT2 > INTWDT1 > NMI Restored PC: The value of the program counter (PC) saved to EIPC, FEPC, or DBPC when interrupt/exception processing is started. The restored PC when a non-maskable or maskable interrupt is acknowledged while either of the following instructions is being executed does not become nextPC (when an interrupt is acknowledged during the execution of an instruction, the execution of that instruction is stopped and is resumed following completion of interrupt servicing). * Load instructions (SLD.B, SLD.BU, SLD.H, SLD.HU, SLD.W) * Divide instructions (DIV, DIVH, DIVU, DIVHU) * PREPARE, DISPOSE instructions (only when an interrupt occurs before stack pointer update) nextPC: The PC value at which processing is started following interrupt/exception processing. 2. The execution address of the illegal opcode when an illegal opcode exception occurs is calculated with (Restored PC - 4).
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17.2 Non-Maskable Interrupts
Non-maskable interrupt request signals are acknowledged unconditionally, even when interrupts are disabled (DI state). Non-maskable interrupts (NMI) are not subject to priority control and take precedence over all other interrupt request signals. The following three types of non-maskable interrupt request signals are available in the V850ES/KE2. * NMI pin input (NMI) * Non-maskable interrupt request signal (INTWDT1) due to overflow of watchdog timer 1 * Non-maskable interrupt request signal (INTWDT2) due to overflow of watchdog timer 2 There are four choices for the valid edge of an NMI pin, namely: rising edge, falling edge, both edges, and no edge detection. The non-maskable interrupt request signal (INTWDT1) due to overflow of watchdog timer 1 functions by setting the WDTM1.WDTM14 and WDTM1.WDTM13 bits to 10. The non-maskable interrupt request signal (INTWDT2) due to overflow of watchdog timer 2 functions by setting the WDTM2.WDM21 and WDTM2.WDM20 bits to 01. When two or more non-maskable interrupts occur simultaneously, they are processed in a sequence determined by the following priority order (the interrupt request signals with low priority level are ignored). INTWDT2 > INTWDT1 > NMI If during NMI processing, an NMI, INTWDT1, or INTWDT2 request signal newly occurs, processing is performed as follows. (1) If an NMI request signal newly occurs during NMI processing The new NMI request signal is held pending regardless of the value of the PSW.NP bit. The NMI request signal held pending is acknowledged upon completion of processing of the NMI currently being executed (following RETI instruction execution). (2) If an INTWDT1 request signal newly occurs during NMI processing If the NP bit remains set (to 1) during NMI processing, the new INTWDT1 request signal is held pending. The INTWDT1 request signal held pending is acknowledged upon completion of processing of the NMI currently being executed (following RETI instruction execution). If the NP bit is cleared (to 0) during NMI processing, a newly generated INTWDT1 request signal is executed (NMI processing is interrupted). (3) If an INTWDT2 request signal newly occurs during NMI processing A newly generated INTWDT2 request signal is executed regardless of the value of the NP bit (NMI processing is interrupted). Caution For non-maskable interrupt servicing from non-maskable interrupt request signals (INTWDT1, INTWDT2), refer to 17.10 Cautions.
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Figure 17-1. Acknowledging Non-Maskable Interrupt Request Signals (1/2)
(a) If two or more NMI request signals are simultaneously generated
* NMI and INTWDT1 requests simultaneously generated
* NMI and INTWDT2 requests simultaneously generated
Main routine INTWDT1 processing NMI, INTWDT1 request (simultaneously generated)
Main routine INTWDT2 processing NMI, INTWDT2 request (simultaneously generated)
System reset
System reset
* INTWDT1 and INTWDT2 requests simultaneously generated
* NMI, INTWDT1, and INTWDT2 requests simultaneously generated
Main routine INTWDT2 processing INTWDT1, INTWDT2 request (simultaneously generated)
Main routine INTWDT2 processing NMI, INTWDT1, INTWDT2 requests (simultaneously generated)
System reset
System reset
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Figure 17-1. Acknowledging Non-Maskable Interrupt Request Signals (2/2)
(b) If a new non-maskable interrupt request signal is generated during a non-maskable interrupt servicing
Non-maskable interrupt currently being serviced NMI Non-maskable interrupt request newly generated during non-maskable interrupt servicing NMI * Generation of NMI request during NMI processing INTWDT1 INTWDT2
* Generation of INTWDT1 request during NMI processing * Generation of INTWDT2 request during NMI processing (NP = 1 state prior to INTWDT1 request is maintained)
Main routine NMI processing NMI request(Hold pending) (Held pending) NMI processing NMI request INTWDT1 request (Hold pending) INTWDT1 processing NMI request INTWDT2 request Main routine NMI processing NMI request Main routine NMI processing INTWDT2 processing
System reset
System reset
* Generation of INTWDT1 request during NMI processing (Set NP = 0 before INTWDT1 request)
Main routine NP = 0 NMI request INTWDT1 request
NMI processing
INTWDT1 processing
System reset
* Generation of INTWDT1 request during NMI processing (Set NP = 0 after INTWDT1 request)
Main routine
NMI processing INTWDT1(Hold pending) request NP = 0
INTWDT1 processing
NMI request
System reset
INTWDT1 * Generation of NMI request during INTWDT1 processing * Generation of INTWDT1 request during INTWDT1 processing * Generation of INTWDT2 request during INTWDT1 processing
Main routine INTWDT1 processing INTWDT1 request NMI request(Invalid) System reset
Main routine INTWDT1 processing INTWDT1 request INTWDT1(Invalid) request System reset INTWDT1 request INTWDT2 request Main routine INTWDT1 processing INTWDT2 processing
System reset
INTWDT2 * Generation of NMI request during INTWDT2 processing
* Generation of INTWDT1 request during INTWDT2 processing * Generation of INTWDT2 request during INTWDT2 processing
Main routine INTWDT2 processing INTWDT2 request NMI request(Invalid) System reset
Main routine INTWDT2 processing INTWDT1(Invalid) request System reset
Main routine INTWDT2 processing INTWDT2(Invalid) request System reset
INTWDT2 request
INTWDT2 request
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17.2.1 Operation Upon generation of a non-maskable interrupt request signal, the CPU performs the following processing and transfers control to a handler routine. <1> Saves the restored PC to FEPC. <2> Saves the current PSW to FEPSW. <3> Writes the exception code (0010H, 0020H, 0030H) to the higher halfword (FECC) of ECR. <4> Sets the PSW.NP and PSW.ID bits to 1 and clears the PSW.EP bit to 0. <5> Loads the handler address (00000010H, 00000020H, 00000030H) of the non-maskable interrupt to the PC and transfers control. Figure 17-2 shows the servicing flow for non-maskable interrupts. Figure 17-2. Non-Maskable Interrupt Servicing
NMI input
INTC acknowledged Non-maskable interrupt request
CPU processing PSW. NP 0 1
FEPC FEPSW ECR. FECC PSW. NP PSW. EP PSW. ID PC
Restored PC PSW Exception code 1 0 1 Handler address
Interrupt request held pending
Interrupt servicing
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17.2.2 Restore Execution is restored from non-maskable interrupt servicing by the RETI instruction. (1) In case of NMI Restore from NMI processing is done with the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. (i) Loads the values of the restored PC and PSW from FEPC and FEPSW, respectively, because the PSW.EP bit and the PSW.NP bit are 0 and 1, respectively. (ii) Transfers control back to the loaded address of the restored PC and PSW. Figure 17-3 shows the processing flow of the RETI instruction. Figure 17-3. RETI Instruction Processing
RETI instruction
1
PSW.EP 0 PSW.NP 0 1
PC PSW
EIPC EIPSW
PC PSW
FEPC FEPSW
Original processing restored
Caution When the EP bit and the NP bit are changed by the LDSR instruction during non-maskable interrupt servicing, in order to restore the PC and PSW correctly during restoring by the RETI instruction, it is necessary to clear the EP bit back to 0 and set the NP bit back to 1 using the LDSR instruction immediately before the RETI instruction. Remark The solid line shows the CPU processing flow.
(2) In case of INTWDT1, INTWDT2 signals For non-maskable interrupt servicing by the non-maskable interrupt request signals (INTWDT1, INTWDT2), refer to 17.10 Cautions.
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17.2.3 NP flag The NP flag is a status flag that indicates that non-maskable interrupt servicing is in progress. This flag is set when a non-maskable interrupt request has been acknowledged, and masks all non-maskable requests to prevent multiple interrupts.
After reset: 00000020H
PSW
0
NP
EP
ID SAT CY OV
S
Z
NP 0 1
NMI servicing status No non-maskable interrupt servicing Non-maskable interrupt serving in progress
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17.3 Maskable Interrupts
Maskable interrupt request signals can be masked by interrupt control registers. maskable interrupt sources (refer to 17.1.1 Features). If two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to the default priority. In addition to the default priority, eight levels of interrupt priorities can be specified by using the interrupt control registers, allowing programmable priority control. When an interrupt request signal has been acknowledged, the interrupt disabled (DI) status is set and the acknowledgment of other maskable interrupt request signals is disabled. When the EI instruction is executed in an interrupt servicing routine, the interrupt enabled (EI) status is set, which enables acknowledgment of interrupt request signals having a priority higher than that of the interrupt request signal currently in progress. Note that only interrupt request signals with a higher priority have this capability; interrupt request signals with the same priority level cannot be nested. To use multiple interrupts, it is necessary to save EIPC and EIPSW to memory or a register before executing the EI instruction, and restore EIPC and EIPSW to the original values by executing the DI instruction before the RETI instruction. When the WDTM1.WDTM14 bit is cleared to 0, the watchdog timer 1 overflow interrupt functions as a maskable interrupt (INTWDTM1). 17.3.1 Operation If a maskable interrupt request signal is generated, the CPU performs the following processing and transfers control to a handler routine. <1> Saves the restored PC to EIPC. <2> Saves the current PSW to EIPSW. <3> Writes an exception code to the lower halfword of ECR (EICC). <4> Sets the PSW.ID bit to 1 and clears the PSW.EP bit to 0. <5> Loads the corresponding handler address to the PC and transfers control. The maskable interrupt request signal masked by INTC and the maskable interrupt request signal that occurs while another interrupt is being serviced (when PSW.NP bit = 1 or ID bit = 1) are held pending internally. When the interrupts are unmasked, or when the NP bit = 0 and the ID bit = 0 by using the RETI and LDSR instructions, a new maskable interrupt servicing is started in accordance with the priority of the pending maskable interrupt request signal. Figure 17-4 shows the servicing flow for maskable interrupts. The V850ES/KE2 has 33
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Figure 17-4. Maskable Interrupt Servicing
INT input
Interrupt mask released? Yes INTC acknowledged Priority higher than that of interrupt currently being serviced? Yes Priority higher than that of other interrupt requests? Yes Highest default priority of interrupt requests with the same priority? Yes Maskable interrupt request
No
No
No
No
Interrupt request pending
1 PSW. NP 0 1 PSW. ID CPU processing EIPC EIPSW ECR. EICC PSW. EP PSW. ID ISPR. correspondingbitNote PC 0 Restored PC PSW Exception code 0 1 1 Handler address Interrupt request pending
Interrupt servicing
Note For the ISPR register, refer to 17.3.6 In-service priority register (ISPR).
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17.3.2 Restore Execution is restored from maskable interrupt servicing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. (1) Loads the values of the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit and the PSW.NP bit are both 0. (2) Transfers control back to the loaded address of the restored PC and PSW. Figure 17-5 shows the processing flow of the RETI instruction. Figure 17-5. RETI Instruction Processing
RETI instruction
1 PSW. EP 0 1
PSW. NP 0 PC PSW ISPR. corresponding -bitNote EIPC EIPSW
PC PSW
FEPC FEPSW
0
Original processing restored
Note For the ISPR register, refer to 17.3.6 In-service priority register (ISPR). Caution When the EP bit and the NP bit are changed by the LDSR instruction during maskable interrupt servicing, in order to restore the PC and PSW correctly during restoring by the RETI instruction, it is necessary to clear the EP bit back to 0 and the NP bit back to 0 using the LDSR instruction immediately before the RETI instruction. Remark The solid line shows the CPU processing flow.
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17.3.3 Priorities of maskable interrupts INTC provides a multiple interrupt servicing in which an interrupt can be acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels specified by the interrupt priority level specification bit (xxICn.xxPRn bit). When two or more interrupts having the same priority level specified by xxPRn are generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt request (default priority level) beforehand. For more information, refer to Table 17-1 Interrupt Source List. Programmable priority control divides interrupt requests into eight levels by setting the priority level specification flag. Note that when an interrupt request signal is acknowledged, the PSW.ID flag is automatically set (1). Therefore, when multiple interrupts are to be used, clear (0) the ID flag beforehand (for example, by placing the EI instruction into the interrupt service program) to enable interrupts. Remark xx: Identifying name of each peripheral unit (refer to Table 17-2 (xxICn)) n: Peripheral unit number (refer to Table 17-2 Interrupt Control Registers (xxICn)) Interrupt Control Registers
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Figure 17-6. Example of Interrupt Nesting (1/2)
Main routine Servicing of a EI Interrupt request a (level 3) EI Interrupt request b (level 2) Interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. Servicing of b
Servicing of c
Interrupt request c (level 3)
Interrupt request d (level 2) Although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled.
Servicing of d
Servicing of e EI Interrupt request e (level 2) Interrupt request f (level 3) Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. Servicing of f
Servicing of g EI Interrupt request g (level 1) Interrupt request h (level 1) Servicing of h
Interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g.
Caution The values of EIPC and EIPSW must be saved before executing multiple interrupts. Remarks 1. a to u in the figure are the names of interrupt request signals shown for the sake of explanation. 2. The default priority in the figure indicates the relative priority between two interrupt request signals.
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Figure 17-6. Example of Interrupt Nesting (2/2)
Main routine Servicing of i EI Interrupt request i (level 2) Interrupt request j (level 3) Interrupt request k (level 1) EI Servicing of k
Interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority.
Servicing of j
Servicing of l Interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status.
Interrupt request l (level 2)
Interrupt request m (level 3) Interrupt request n (level 1) Servicing of n
Pending interrupt requests are acknowledged after servicing of interrupt request l. At this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m.
Servicing of m
Interrupt request o (level 3)
Servicing of o Servicing of p EI Servicing of q EI Servicing of r EI Interrupt request p Interrupt request q EI (level 2) Interrupt request r (level 1) (level 0)
If levels 3 to 0 are acknowledged Servicing of s Pending interrupt requests t and u are acknowledged after processing of s. Because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. Servicing of u
Interrupt request s (level 1)
Interrupt request t (level 2)Note 1 Interrupt request u (level 2)Note 2
Servicing of t
Notes 1. Lower default priority 2. Higher default priority
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Figure 17-7. Example of Servicing Simultaneously Generated Interrupt Request Signals
Main routine EI Interrupt request a (level 2) Interrupt request b (level 1)Note 1 Interrupt request c (level 1)Note 2 Servicing of interrupt request b *Interrupt requests b and c are acknowledged first according to their priorities. *Because the priorities of b and c are the same, b is acknowledged first because it has the higher default priority.
Servicing of interrupt request c
Servicing of interrupt request a
Notes 1. Higher default priority 2. Lower default priority
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17.3.4 Interrupt control register (xxlCn) An interrupt control register is assigned to each maskable interrupt and sets the control conditions for each maskable interrupt request. The interrupt control registers can be read or written in 8-bit or 1-bit units. Reset sets xxICn to 47H. Caution Be sure to read the xxICn.xxIFn bit while interrupts are disabled (DI). If the xxIFn bit is read while interrupts are enabled (EI), an incorrect value may be read if there is a conflict between acknowledgment of the interrupt and reading of the bit.
After reset: 47H <>
R/W <>
Address: FFFFF110H to FFFFF168H
xxICn
xxIFn
xxMKn
0
0
0
xxPRn2
xxPRn1
xxPRn0
xxIFn 0 1
Interrupt request flagNote Interrupt request not generated Interrupt request generated
xxMKn 0 1 Enables interrupt servicing
Interrupt mask flag
Disables interrupt servicing (pending)
xxPRn2 0 0 0 0 1 1 1 1
xxPRn1 0 0 1 1 0 0 1 1
xxPRn0 0 1 0 1 0 1 0 1
Interrupt priority specification bit Specifies level 0 (highest) Specifies level 1 Specifies level 2 Specifies level 3 Specifies level 4 Specifies level 5 Specifies level 6 Specifies level 7 (lowest)
Note Automatically reset by hardware when interrupt request is acknowledged. Remark xx: Identifying name of each peripheral unit (refer to Table 17-2 (xxICn)) n: Peripheral unit number (refer to Table 17-2 Interrupt Control Registers (xxICn)) Interrupt Control Registers
Following tables list the addresses and bits of the interrupt control registers.
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Table 17-2. Interrupt Control Registers (xxlCn)
Address Register <7> FFFFF110H FFFFF112H FFFFF114H FFFFF116H FFFFF118H FFFFF11AH FFFFF11CH FFFFF11EH FFFFF124H FFFFF126H FFFFF128H FFFFF12AH FFFFF12CH FFFFF12EH FFFFF130H FFFFF132H FFFFF134H FFFFF136H FFFFF138H FFFFF13AH FFFFF13CH FFFFF13EH FFFFF142H FFFFF144H FFFFF146H FFFFF148H FFFFF14AH FFFFF14CH FFFFF172H FFFFF174H FFFFF176H FFFFF178H WDT1IC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 TM0IC10 TM0IC11 TM5IC0 TM5IC1 CSI0IC0 CSI0IC1 SREIC0 SRIC0 STIC0 SREIC1 SRIC1 STIC1 TMHIC0 TMHIC1 IICIC0 ADIC KRIC WTIIC WTIC BRGIC PIC7 TP0OVIC WDT1IF PIF0 PIF1 PIF2 PIF3 PIF4 PIF5 PIF6 TM0IF10 TM0IF11 TM5IF0 TM5IF1 CSI0IF0 CSI0IF1 SREIF0 SRIF0 STIF0 SREIF1 SRIF1 STIF1 TMHIF0 TMHIF1 IICIF0 ADIF KRIF WTIIF WTIF BRGIF PIF7 TP0OVIF <6> WDT1MK PMK0 PMK1 PMK2 PMK3 PMK4 PMK5 PMK6 TM0MK10 TM0MK11 TM5MK0 TM5MK1 CSI0MK0 CSI0MK1 SREMK0 SRMK0 STMK0 SREMK1 SRMK1 STMK1 TMHMK0 TMHMK1 IICMK0 ADMK KRMK WTIMK WTMK BRGMK PMK7 TP0OVMK 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0
WDT1PR2 WDT1PR1 WDT1PR0 PPR02 PPR12 PPR22 PPR32 PPR42 PPR52 PPR62 PPR01 PPR11 PPR21 PPR31 PPR41 PPR51 PPR61 PPR00 PPR10 PPR20 PPR30 PPR40 PPR50 PPR60
TM0PR102 TM0PR101 TM0PR100 TM0PR112 TM0PR111 TM0PR110 TM5PR02 TM5PR12 TM5PR01 TM5PR11 TM5PR00 TM5PR10
CSI0PR02 CSI0PR01 CSI0PR00 CSI0PR12 CSI0PR11 CSI0PR10 SREPR02 SRPR02 STPR02 SREPR12 SRPR12 STPR12 TMHPR02 TMHPR12 IICPR02 ADPR2 KRPR2 WTIPR2 WTPR2 BRGPR2 PPR72 SREPR01 SRPR01 STPR01 SREPR11 SRPR11 STPR11 TMHPR01 TMHPR11 IICPR01 ADPR1 KRPR1 WTIPR1 WTPR1 BRGPR1 PPR71 SREPR00 SRPR00 STPR00 SREPR10 SRPR10 STPR10 TMHPR00 TMHPR10 IICPR00 ADPR0 KRPR0 WTIPR0 WTPR0 BRGPR0 PPR70
TP0OVPR2 TP0OVPR1 TP0OVPR0 TP0CCPR02 TP0CCPR12 TP0CCPR01 TP0CCPR11 TP0CCPR00 TP0CCPR10
TP0CCIC0 TP0CCIF0 TP0CCMK0 TP0CCIC1 TP0CCIF1 TP0CCMK1
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17.3.5 Interrupt mask registers 0, 1, 3 (IMR0, IMR1, IMR3) These registers set the interrupt mask status for maskable interrupts. The xxMKn bit of the IMR0, IMR1, and IMR3 registers and the xxMKn bit of the xxlCn register are respectively linked. The IMRm register can be read or written in 16-bit units (m = 0, 1, 3). When the higher 8 bits of the IMRk register are treated as the IMRkH register and the lower 8 bits of the IMRk register as the IMRkL register, they can be read or written in 8-bit or 1-bit units (k = 0, 1). Caution In the device file, the xxMKn bit of the xxICn register is defined as a reserved word. Therefore, if bit manipulation is performed using the name xxMKn, the xxICn register, not the IMRm register, is rewritten (as a result, the IMRm register is also rewritten).
After reset: FFFFH
15
R/W
14
Address: IMR0 FFFFF100H, IMR0L FFFFF100H, IMR0H FFFFF101H
13 12 11 10 9 8
IMR0 (IMR0H
Note
) CSI0MK1 CSI0MK0 TM5MK1 TM5MK0 TM0MK11 TM0MK10
7 6 5 4 3 2
1
1
1
0
(IMR0L)
PMK6
PMK5
PMK4
PMK3
PMK2
PMK1
PMK0
WDT1MK
After reset: FFFFH
15
R/W
14
Address: IMR1 FFFFF102H, IMR1L FFFFF102H, IMR1H FFFFF103H
13 12 11 10 9 8
IMR1 (IMR1H
Note
)
1
7
BRGMK
6
WTMK
5
WTIMK
4
KRMK
3
ADMK
2
IICMK0
1
1
0
(IMR1L) TMHMK1 TMHMK0
STMK1
SRMK1
SREMK1
STMK0
SRMK0
SREMK0
After reset: FFFFH
15
R/W
14
Address: IMR3, IMR3L FFFFF106H
13 12 11 10 9 8
IMR3
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
(IMR3L)
1
1
1
TP0CCMK1 TP0CCMK0 TP0OVMK
PMK7
1
xxMKn 0 1
Interrupt mask flag setting Enables interrupt servicing Disables interrupt servicing
Note When reading from or writing to bits 8 to 15 of the IMR0 and IMR1 registers in 8-bit or 1bit units, specify these bits as bits 0 to 7 of the IMR0H and IMR1H registers. Caution Set bits 9 and 8 of the IMR0 register, bits 15 and 8 of the IMR1 register, and bits 15 to 5 and 0 of the IMR3 register to 1. The operation is not guaranteed if their value is changed. Remark xx: Identifying name of each peripheral unit (refer to Table 17-2 Interrupt Control Registers (xxICn)) n: Peripheral unit number (refer to Table 17-2 Interrupt Control Registers (xxICn))
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17.3.6 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently being acknowledged. When the interrupt request signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt request signal is set (1) and remains set while the interrupt is being serviced. When the RETI instruction is executed, the bit among those that are set (1) in the ISPR register that corresponds to the interrupt request signal having the highest priority is automatically cleared (0) by hardware. However, it is not cleared (0) when execution is returned from non-maskable interrupt servicing or exception processing. This register is read-only in 8-bit or 1-bit units. Reset sets ISPR to 00H. Caution If an interrupt is acknowledged while the ISPR register is being read in the interrupt enabled (EI) status, the value of the ISPR register after the bits of the register have been set to 1 by acknowledging the interrupt may be read. To accurately read the value of the ISPR register before an interrupt is acknowledged, read the register while interrupts are disabled (DI status).
After reset: 00H <>
R
Address: FFFFF1FAH <> <> <> <> <> <> <>
ISPR
ISPR7
ISPR6
ISPR5
ISPR4
ISPR3
ISPR2
ISPR1
ISPR0
ISPRn 0 1
Priority of interrupt currently being acknowledged Interrupt request with priority n is not acknowledged Interrupt request with priority n is being acknowledged
Remark
n = 0 to 7 (priority level)
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17.3.7 ID flag The interrupt disable flag (ID) is allocated to the PSW and controls the maskable interrupt's operating state, and stores control information regarding enabling/disabling reception of interrupt request signals. Reset sets this flag to 00000020H.
After reset: 00000020H
PSW
0
NP
EP
ID SAT CY OV
S
Z
ID 0 1
Maskable interrupt servicing specificationNote Maskable interrupt request signal acknowledgment enabled Maskable interrupt request signal acknowledgment disabled
Note Interrupt disable flag (ID) function ID is set (1) by the DI instruction and cleared (0) by the EI instruction. Its value is also modified by the RETI instruction or LDSR instruction when referencing the PSW. Non-maskable interrupt request signals and exceptions are acknowledged regardless of this flag. When a maskable interrupt request signal is acknowledged, the ID flag is automatically set (1) by hardware. An interrupt request signal generated during the acknowledgment disabled period (ID flag = 1) can be acknowledged when the xxICn.xxIFn bit is set (1), and the ID flag is cleared (0).
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17.3.8 Watchdog timer mode register 1 (WDTM1) This register is a special register that can be written to only in a special sequence. To generate a maskable interrupt (INTWDT1), clear the WDTM14 bit to 0. This register can be read or written in 8-bit or 1-bit units (for details, refer to CHAPTER 11 WATCHDOG TIMER FUNCTIONS).
After reset: 00H <> WDTM1 RUN1
R/W
Address: FFFFF6C2H
0
0
WDTM14 WDTM13
0
0
0
RUN1 0 1
Watchdog timer operation mode selectionNote 1 Stop count operation Clear counter and start count operation
WDTM14 WDTM13 0 0 1 1 0 1 0 1
Watchdog timer operation mode selectionNote 2 Interval timer mode (Generate maskable interrupt INTWDTM1 when overflow occurs) Watchdog timer mode 1Note 3 (Generate non-maskable interrupt INTWDT1 when overflow occurs) Watchdog timer mode 2 (Start WDTRES2 reset operation when overflow occurs)
Notes 1. Once the RUN1 bit has been set (1), it cannot be cleared (0) by software. Therefore, once counting starts, it cannot be stopped except by reset. 2. Once the WDTM14 and WDTM13 bits have been set (1), they cannot be cleared (0) by software. Reset is the only way to clear these bits. 3. For non-maskable interrupt servicing due to a non-maskable interrupt request signal (INTWDT1), refer to 17.10 Cautions.
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17.4 External Interrupt Request Input Pins (NMI, INTP0 to INTP7)
17.4.1 Noise elimination (1) Noise elimination for NMI pin The NMI pin includes a noise eliminator that operates using analog delay. Therefore, a signal input to the NMI pin is not detected as an edge unless it maintains its input level for a certain period. The edge is detected only after a certain period has elapsed. The NMI pin is used for releasing the STOP mode. In the STOP mode, noise elimination using the system clock is not performed because the internal system clock is stopped. (2) Noise elimination for INTP0 to INTP2 and INTP4 to INTP7 pins The INTP0 to INTP2 and INTP4 to INTP7 pins include a noise eliminator that operates using analog delay. Therefore, a signal input to each pin is not detected as an edge unless it maintains its input level for a certain period. The edge is detected only after a certain period has elapsed. (3) Noise elimination for INTP3 pin The INTP3 pin has a digital/analog noise eliminator that can be selected by the NFC.NFEN bit. The number of times the digital noise eliminator samples signals can be selected by the NFC.NFSTS bit from three or two. The sampling clock can be selected by the NFC.NFC2 to NFC.NFC0 bits from fXX/64, fXX/128, fXX/256, fXX/512, fXX/1024, and fXT. If the sampling clock is set to fXX/64, fXX/128, fXX/256, fXX/512, or fXX/1024, the sampling clock stops in the IDLE/STOP mode. It cannot therefore be used to release the standby mode. To release the standby mode, select fXT as the sampling clock or select the analog noise eliminator.
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(a) Digital noise elimination control register (NFC) The NFC register controls elimination of noise on the INTP3 pin. If fXT is used as the noise elimination clock, the external interrupt function of the INTP3 pin can be used even in the IDLE/STOP mode. This register can be read or written in 8-bit or 1-bit units. Reset sets NFC to 00H.
After reset: 00H
R/W
Address: FFFFF318H
NFC
NFEN
NFSTS
0
0
0
NFC2
NFC1
NFC0
NFEN 0 1 NFSTS 0 1
Setting of INTP3 pin noise elimination Analog noise elimination Digital noise elimination Setting of number of samplings of digital noise elimination Number of samplings = 3 times Number of samplings = 2 times
NFC2 0 0 0 0 1 1
NFC1 0 0 1 1 0 0
NFC0 0 1 0 1 0 1 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1024 fXT
Selection of sampling clock
Other than above
Setting prohibited
Remark
fXX: Main clock frequency fXT: Subclock frequency
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The digital noise elimination width (tWIT3) is as follows, where T is the sampling clock period and M is the number of samplings. * tWIT3 < (M - 1)T: * (M - 1)T tWIT3 < MT: * tWIT3 MT: Accurately eliminated as noise May be eliminated as noise or detected as valid edge Accurately detected as valid edge
To detect the valid edge input to the INTP3 pin accurately, therefore, a pulse wider than MT must be input.
NFSTS NFC2 NFC1 NFC0 Sampling Clock Minimum Elimination Noise Width fXX = 20 MHz 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1024 fXT (32.768 kHz) fXX/64 fXX/128 fXX/256 fXX/512 fXX/1024 fXT (32.768 kHz) Setting prohibited 6.4 s 12.8 s 25.6 s 51.2 s 102.4 s 61.04 s 3.2 s 6.4 s 12.8 s 25.6 s 51.2 s 30.52 s 6.4 s 12.8 s 25.6 s 51.2 s 102.4 s 8 s 16 s 32 s 64 s 128 s fXX = 10 MHz 12.8 s 25.6 s 51.2 s 102.4 s 204.8 s fXX = 8 MHz 16 s 32 s 64 s 128 s 256 s
Other than above
17.4.2 Edge detection The valid edges of the NMI and INTP0 to INTP7 pins can be selected from the following four types for each pin. * Rising edge * Falling edge * Both edges * No edge detection After reset, the edge detection for the NMI pin is set to "no edge detection". Therefore, interrupt requests cannot be acknowledged (the NMI pin functions as a normal port) unless a valid edge is specified by the INTR0 and INTF0 registers. When using the P02 pin as an output port, set the NMI pin valid edge to "no edge detection".
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(1) External interrupt rising and falling edge specification registers 0 (INTR0, INTF0) These are 8-bit registers that specify detection of the rising and falling edges of the NMI and INTP0 to INTP3 pins. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H. Caution When switching to the port function from the external interrupt function (alternate function), edge detection may be performed. Therefore, set the port mode after setting the INTF0n and INTR0n bits = 00.
After reset: 00H
R/W
Address: INTR0 FFFFFC20H, INTF0 FFFFFC00H
INTR0
0
INTR06 INTP3
INTR05 INTP2
INTR04 INTP1
INTR03 INTP0
INTR02 NMI
0
0
INTF0
0
INTF06 INTP3
INTF05 INTP2
INTF04 INTP1
INTF03 INTP0
INTF02 NMI
0
0
Remark
For specification of the valid edge, refer to Table 17-3.
Table 17-3. NMI and INTP0 to INTP3 Pins Valid Edge Specification
INTF0n 0 0 1 1 INTR0n 0 1 0 1 Valid edge specification (n = 2 to 6) No edge detection Rising edge Falling edge Both edges
Remark n = 2:
Control of NMI pin
n = 3 to 6: Control of INTP0 to INTP3 pins
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(2) External interrupt rising and falling edge specification registers 3 (INTR3, INTF3) These are 8-bit registers that specify detection of the rising and falling edges of the INTP7 pin. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H. Caution When switching to the port function from the external interrupt function (alternate function), edge detection may be performed. Therefore, set the port mode after setting the INTF31 and INTR31 bits = 00.
After reset: 00H
R/W
Address: INTR3 FFFFFC26H, INTF3 FFFFFC06H
INTR3
0
0
0
0
0
0
INTR31 INTP7
0
INTF3
0
0
0
0
0
0
INTF31 INTP7
0
Remark
For specification of the valid edge, refer to Table 17-4.
Table 17-4. INTP7 Pin Valid Edge Specification
INTF31 0 0 1 1 INTR31 0 1 0 1 No edge detection Rising edge Falling edge Both edges Valid edge specification
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(3) External interrupt rising and falling edge specification registers 9H (INTR9H, INTF9H) These are 8-bit registers that specify detection of the rising edge of the INTP4 to INTP6 pins. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H. Caution When switching to the port function from the external interrupt function (alternate function), edge detection may be performed. Therefore, set the port mode after setting the INTF9n and INTR9n bits = 00.
After reset: 00H
R/W
Address: INTR9H FFFFFC33H, INTF9H FFFFFC13H
INTR9H
INTR915 INTR914 INTR913 INTP6 INTP5 INTP4
0
0
0
0
0
INTF9H
INTF915 INTF914 INTF913 INTP6 INTP5 INTP4
0
0
0
0
0
Remark
For specification of the valid edge, refer to Table 17-5.
Table 17-5. INTP4 to INTP6 Pins Valid Edge Specification
INTF9n 0 0 1 1 INTR9n 0 1 0 1 Valid edge specification (n = 13 to 15) No edge detection Rising edge Falling edge Both edges
Remark n = 13 to 15: Control of INTP4 to INTP6 pins
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17.5 Software Exceptions
A software exception is generated when the CPU executes the TRAP instruction. Software exceptions can always be acknowledged. 17.5.1 Operation If a software exception occurs, the CPU performs the following processing and transfers control to a handler routine. <1> Saves the restored PC to EIPC. <2> Saves the current PSW to EIPSW. <3> Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source). <4> Sets the PSW.EP and PSW.ID bits to 1. <5> Loads the handler address (00000040H or 00000050H) for the software exception routine to the PC and transfers control. Figure 17-8 shows the software exception processing flow. Figure 17-8. Software Exception Processing
TRAP instructionNote
CPU processing
EIPC EIPSW ECR.EICC PSW.EP PSW.ID PC
Restored PC PSW Exception code 1 1 Handler address
Exception processing
Note TRAP instruction format: TRAP vector (However, vector = 00H to 1FH)
The handler address is determined by the operand (vector) of the TRAP instruction. If the vector is 00H to 1FH, the handler address is 00000040H, and if the vector is 10H to 1FH, the handler address is 00000050H.
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17.5.2 Restore Execution is restored from software exception processing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. <1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 1. <2> Transfers control to the address of the restored PC and PSW. Figure 17-9 shows the processing flow of the RETI instruction. Figure 17-9. RETI Instruction Processing
RETI instruction
1
PSW.EP 0 PSW.NP 0 1
PC PSW
EIPC EIPSW
PC PSW
FEPC FEPSW
Original processing restored
Caution When the EP bit and the NP bit are changed by the LDSR instruction during software exception processing, in order to restore the PC and PSW correctly during restoring by the RETI instruction, it is necessary to set the PSW.EP bit back to 1 using the LDSR instruction immediately before the RETI instruction. Remark The solid line shows the CPU processing flow.
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17.5.3 EP flag The EP flag, which is bit 6 of the PSW, is a status flag that indicates that exception processing is in progress. It is set when an exception occurs.
After reset: 00000020H
PSW
0
NP
EP
ID SAT CY OV
S
Z
EP 0 1
Exception processing status Exception processing not in progress Exception processing in progress
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17.6 Exception Trap
The exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850ES/KE2, an illegal opcode trap (ILGOP) is considered as an exception trap. 17.6.1 Illegal opcode An illegal opcode is defined as an instruction with instruction opcode (bits 10 to 5) = 111111B, sub-opcode (bits 26 to 23) = 0111B to 1111B, and sub-opcode (bit 16) = 0B. When such an instruction is executed, an exception trap is generated.
15
11 10
54
0 31
27 26
23 22
16
0111 XXXXX111111XXXXXXXXXX 1111 XXXXXX0
X: don't care
Caution It is recommended not to use illegal opcode because instructions may newly be assigned in the future. (1) Operation Upon generation of an exception trap, the CPU performs the following processing and transfers control to a handler routine. <1> Saves the restored PC to DBPC. <2> Saves the current PSW to DBPSW. <3> Sets the PSW.NP, PSW.EP, and PSW.ID bits. <4> Loads the handler address (00000060H) for the exception trap routine to the PC and transfers control. Figure 17-10 shows the exception trap processing flow.
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Figure 17-10. Exception Trap Processing
Exception trap (ILGOP) occurs
CPU processing
DBPC DBPSW PSW.NP PSW.EP PSW.ID PC
Restored PC PSW 1 1 1 00000060H
Exception processing
(2) Restore Execution is restored from exception trap processing by the DBRET instruction. When the DBRET instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. <1> Loads the restored PC and PSW from DBPC and DBPSW. <2> Transfers control to the loaded address of the restored PC and PSW. Figure 17-11 shows the processing flow for restore from exception trap processing. Figure 17-11. Processing Flow for Restore from Exception Trap
DBRET instruction
PC PSW
DBPC DBPSW
Jump to restored PC address
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17.6.2 Debug trap A debug trap is an exception that occurs upon execution of the DBTRAP instruction and that can be acknowledged at all times. When a debug trap occurs, the CPU performs the following processing. (1) Operation <1> Saves the restored PC to DBPC. <2> Saves the current PSW to DBPSW. <3> Sets the PSW.NP, PSW.EP, and PSW.ID bits to 1. <4> Sets the handler address (00000060H) for the debug trap routine to the PC and transfers control. Figure 17-12 shows the debug trap processing flow. Figure 17-12. Debug Trap Processing
DBTRAP instruction
CPU processing
DBPC DBPSW PSW.NP PSW.EP PSW.ID PC
Restored PC PSW 1 1 1 00000060H
Debug monitor routine processing
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(2) Restore Execution is restored from debug trap processing by the DBRET instruction. When the DBRET instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. <1> Loads the restored PC and PSW from DBPC and DBPSW. <2> Transfers control to the loaded address of the restored PC and PSW. Figure 17-13 shows the processing flow for restore from debug trap processing. Figure 17-13. Processing Flow for Restore from Debug Trap
DBRET instruction
PC PSW
DBPC DBPSW
Jump to restored PC address
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17.7 Multiple Interrupt Servicing Control
Multiple interrupt servicing control is a function that stops an interrupt service routine currently in progress if a higher priority interrupt request signal is generated, and processes the acknowledgment operation of the higher priority interrupt request signal. If an interrupt request signal with a lower or equal priority is generated and a service routine is currently in progress, the later interrupt request signal will be held pending. Multiple interrupt servicing control is performed when interrupts are enabled (PSW.ID bit = 0). Even in an interrupt servicing routine, multiple interrupt control must be performed while interrupts are enabled (ID bit = 0). If a maskable interrupt or software exception is generated in a maskable interrupt or software exception service program, EIPC and EIPSW must be saved. The following example illustrates the procedure. (1) To acknowledge maskable interrupt request signals in service program Service program for maskable interrupt or exception ... ... * EIPC saved to memory or register * EIPSW saved to memory or register * EI instruction (enables interrupt acknowledgment) ... ... ... ... * DI instruction (disables interrupt acknowledgment) * Saved value restored to EIPSW * Saved value restored to EIPC * RETI instruction
Acknowledges maskable interrupt
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(2) To generate exception in service program Service program for maskable interrupt or exception ... ... * EIPC saved to memory or register * EIPSW saved to memory or register ... * TRAP instruction ... * Saved value restored to EIPSW * Saved value restored to EIPC * RETI instruction Priorities 0 to 7 (0 is the highest) can be set for each maskable interrupt request in multiple interrupt servicing control by software. To set a priority level, write values to the xxICn.xxPRn0 to xxICn.xxPRn2 bits After reset, interrupt requests are masked by the corresponding to each maskable interrupt request. Acknowledges exceptions such as TRAP instruction.
xxICn.xxMKn bit, and the priority is set to level 7 by the xxPRn0 to xxPRn2 bits. Priorities of maskable interrupts are as follows. (High) Level 0 > Level 1 > Level 2 > Level 3 > Level 4 > Level 5 > Level 6 > Level 7 (Low) Interrupt servicing that has been suspended as a result of multiple interrupt servicing control is resumed after the interrupt servicing of the higher priority has been completed and the RETI instruction has been executed. A pending interrupt request signal is acknowledged after the current interrupt servicing has been completed and the RETI instruction has been executed. Caution In a non-maskable interrupt servicing routine (in the time until the RETI instruction is executed), maskable interrupts are not acknowledged and held pending.
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17.8 Interrupt Response Time
Except in the following cases, the CPU interrupt response time is a minimum of 4 clocks. If inputting consecutive interrupt request signals, at least 4 clocks must be placed between each interrupt request signal. * IDLE/STOP mode * External bus access * Consecutive interrupt request non-sample instruction (refer to 17.9 Acknowledged by CPU) * Access to interrupt control register * Access to peripheral I/O register Figure 17-14. Pipeline Operation During Interrupt Request Signal Acknowledgment (Outline) Periods in Which Interrupts Are Not
(1) Minimum interrupt response time
4 system clocks Internal clock
Interrupt request Instruction 1 Instruction 2 Interrupt acknowledgment operation Instruction (first instruction of interrupt servicing routine) IF ID EX MEM WB
IFX IDX INT1 INT2 INT3 INT4 IF ID EX
(2) Maximum interrupt response time
6 system clocks Internal clock
Interrupt request Instruction 1 Instruction 2 Interrupt acknowledgment operation Instruction (first instruction of interrupt servicing routine) IF ID EX MEM MEM MEM WB
IFX IDX INT1 INT2 INT3 INT3 INT3 INT4 IF ID EX
Remark
INT1 to INT4: Interrupt acknowledgment processing IFX: Invalid instruction fetch IDX: Invalid instruction decode
Interrupt response time (internal system clock) Internal interrupt Min. Max. 4 6 External interrupt 4 + analog delay 6 + analog delay
Condition
The following cases are excluded. * IDLE/STOP mode * External bus access * Consecutive interrupt request non-sample instruction * Access to interrupt control register * Access to peripheral I/O register
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17.9 Periods in Which Interrupts Are Not Acknowledged by CPU
Interrupts are acknowledged by the CPU while an instruction is being executed. pending). The following instructions are interrupt request non-sample instructions. * EI instruction * DI instruction * LDSR reg2, 0x5 instructions (vs. PSW) * Store instruction for the PRCMD register * Store instruction and SET1, NOT1, and CLR1 instructions for the following registers * Interrupt-related registers: Interrupt control register (xxlCn), interrupt mask registers 0, 1, 3 (IMR0, IMR1, IMR3) * Power save control register (PSC) However, no interrupt is
acknowledged between an interrupt request non-sample instruction and the next instruction (interrupts are held
17.10 Cautions
Design the system so that restoring by the RETI instruction is as follows after a non-maskable interrupt triggered by a non-maskable interrupt request signal (INTWDT1/INTWDT2) is serviced. Figure 17-15. Restoring by RETI Instruction
Generation of INTWDT1/INTWDT2
FEPC software reset processing address FEPSW value to set NP bit = 1, EP bit = 1 RETI INTWDT1/INTWDT2 servicing routine
Ten RETI instructions (FEPC and FEPSWNote must be set) PSW initial set value of PSW Initialization processing Software reset processing routine
Note FEPSW value to set NP bit = 1, EP bit = 0
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CHAPTER 18 KEY INTERRUPT FUNCTION
18.1 Function
A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins (KR0 to KR7) by setting the KRM register. Caution If any of the KR0 to KR7 pins is at low level, the INTKR signal is not generated even if a falling edge is input to another pin. Table 18-1. Assignment of Key Return Detection Pins
Flag KRM0 KRM1 KRM2 KRM3 KRM4 KRM5 KRM6 KRM7 Pin Description Controls KR0 signal in 1-bit units Controls KR1 signal in 1-bit units Controls KR2 signal in 1-bit units Controls KR3 signal in 1-bit units Controls KR4 signal in 1-bit units Controls KR5 signal in 1-bit units Controls KR6 signal in 1-bit units Controls KR7 signal in 1-bit units
Figure 18-1. Key Return Block Diagram
KR7 KR6 KR5 KR4 INTKR KR3 KR2 KR1 KR0
KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Key return mode register (KRM)
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18.2 Register
(1) Key return mode register (KRM) The KRM register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
After reset: 00H
R/W
Address: FFFFF300H
KRM
KRM7
KRM6
KRM5
KRM4
KRM3
KRM2
KRM1
KRM0
KRMn 0 1
Key return mode control Does not detect key return signal Detects key return signal
Caution If the KRM register is changed, an interrupt request signal (INTKR) may be generated. To prevent this, change the KRM register after disabling interrupts (DI), and then enable interrupts (EI) after clearing the interrupt request flag (KRIC.KRIF bit) to 0. Remark For the alternate-function pin settings, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions.
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CHAPTER 19 STANDBY FUNCTION
19.1 Overview
The power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. The available standby modes are listed in Table 19-1. Table 19-1. Standby Modes
Mode HALT mode IDLE mode STOP mode Subclock operation mode Sub-IDLE mode Functional Outline Mode to stop only the operating clock of the CPU Mode to stop all the operations of the internal circuits except the oscillator
Note 1
Mode to stop all the operations of the internal circuits except the subclock oscillator Mode to use the subclock as the internal system clock
Note 2
Mode to stop all the operations of the internal circuits, except the oscillator, in the subclock operation mode
Notes 1. The PLL does not stop. To realize low power consumption, stop the PLL and then shift to the IDLE mode. 2. Change to the clock-through mode, stop the PLL, then shift to the STOP mode. For details, refer to CHAPTER 5 CLOCK GENERATION FUNCTION.
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Figure 19-1. Status Transition (1/2)
Normal operation mode (operation with main clock) End of oscillation stabilization time count End of oscillation stabilization time count Interrupt requestNote 3 End of oscillation stabilization time count Interrupt request
Note 2
Setting of HALT mode
Wait for stabilization of oscillation
Setting of IDLE mode
Wait for stabilization of oscillation
Setting of STOP mode
ResetNote 1
Wait for stabilization of oscillation Interrupt requestNote 4 ResetNote 5
ResetNote 5
HALT mode
IDLE mode
STOP mode
Notes 1. Reset by RESET pin input, watchdog timer 1 overflow (WDTRES1), or watchdog timer 2 overflow (WDTRES2). 2. Non-maskable interrupt request signal (NMI, INTWDT1, INTWDT2) or unmasked maskable interrupt request signal. 3. Non-maskable interrupt request signal (NMI pin input, INTWDT2 (when the CPU is operating on the subclock)), unmasked external interrupt request signal (INTP0 to INTP7 pin input), or unmasked internal interrupt request signal from peripheral functions operable in IDLE mode. 4. Non-maskable interrupt request signal (NMI pin input, INTWDT2 (when the CPU is operating on the subclock)), unmasked external interrupt request signal (INTP0 to INTP7 pin input), or unmasked internal interrupt request signal from peripheral functions operable in STOP mode. 5. Reset by RESET pin input or watchdog timer 2 (when the CPU is operating on the subclock) overflow (WDTRES2).
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Figure 19-1. Status Transition (2/2)
Normal operation mode (operation with main clock) End of oscillation stabilization time count End of oscillation stabilization time count
Setting of subclock operation mode
Wait for stabilization of oscillation Setting of normal operation mode
Wait for stabilization of oscillation
ResetNote 1
ResetNote 1
Interrupt requestNote 2 Subclock operation mode (operation with subclock) Setting of IDLE mode Sub-IDLE mode
Notes 1. Reset by RESET pin input or watchdog timer 2 overflow (WDTRES2). 2. Non-maskable interrupt request signal (NMI pin input, INTWDT2 (when the CPU is operating on the subclock)), unmasked external interrupt request signal (INTP0 to INTP7 pin input), or unmasked internal interrupt request signal from peripheral functions operable in sub-IDLE mode.
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19.2 Registers
(1) Power save control register (PSC) This is an 8-bit register that controls the standby function. The STP bit of this register is used to specify the standby mode. The PSC register is a special register that can be written to only in a special sequence (refer to 3.4.7 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets PSC to 00H.
After reset: 00H <> PSC NMI2M
R/W
Address: FFFFF1FEH <> <> INTM 0 0 <> STP 0
0
NMI0M
NMI2M 0 1
Control of releasing standby modeNote by INTWDT2 signal Releasing standby modeNote by INTWDT2 signal enabled Releasing standby modeNote by INTWDT2 signal disabled Control of releasing standby modeNote by NMI pin input Releasing standby modeNote by NMI pin input enabled Releasing standby modeNote by NMI pin input disabled
NMI0M 0 1
INTM 0 1
Control of releasing standby modeNote by maskable interrupt request signals Releasing standby modeNote by maskable interrupt request signals enabled Releasing standby modeNote by maskable interrupt request signals disabled
STP 0 1 Normal mode Standby modeNote
Standby modeNote setting
Note In this case, standby mode means the IDLE/STOP mode; it does not include the HALT mode. Cautions 1. If the NMI2M, NMI0M, and INTM bits, and the STP bit are set to 1 at the same time, the setting of NMI2M, NMI0M, and INTM bits becomes invalid. If there is an unmasked interrupt request signal being held pending when the IDLE/STOP mode is set, set the bit corresponding to the interrupt request signal (NMI2M, NMI0M, or INTM) to 1, and then set the STP bit to 1. 2. When the IDLE/STOP mode is set, set the PSMR.PSM bit and then set the STP bit.
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(2) Power save mode register (PSMR) This is an 8-bit register that controls the operation status in the standby mode and the clock operation. This register can be read or written in 8-bit or 1-bit units. Reset sets PSMR to 00H.
After reset: 00H
R/W
After reset: FFFFF820H <>
PSMR
XTSTP
0
0
0
0
0
0
PSM
XTSTP 0 1
Specification of subclock oscillator use Subclock oscillator used Subclock oscillator not used
PSM 0 1 IDLE mode STOP mode
Specification of operation in standby mode
Cautions 1. Be sure to clear the XTSTP bit to 0 during subclock resonator connection. 2. Be sure to clear bits 1 to 6 of the PSMR register to 0. 3. The PSM bit is valid only when the PSC.STP bit is 1.
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(3) Oscillation stabilization time selection register (OSTS) The wait time until the oscillation stabilizes after the STOP mode is released is controlled by the OSTS register. The OSTS register can be read or written in 8-bit units. Reset sets OSTS to 01H.
After reset: 01H
R/W
Address: FFFFF6C0H
OSTS
0
0
0
0
0
OSTS2
OSTS1
OSTS0
OSTS2
OSTS1
OSTS0
Selection of oscillation stabilization time
fX
4 MHz
5 MHz
1.638 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 419.4 ms
10 MHz 0.819 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
2 /fX 215/fX 2 /fX 2 /fX 2 /fX 219/fX 2 /fX 2 /fX
21 20 18 17 16
13
2.048 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 262.1 ms 524.3 ms
Cautions 1. The wait time following release of the STOP mode does not include the time until the clock oscillation starts ("a" in the figure below) following release of the STOP mode, regardless of whether the STOP mode is released by reset or the occurrence of an interrupt request signal.
STOP mode release Voltage waveform of X1 pin a VSS
2. Be sure to clear bits 3 to 7 to "0". 3. The oscillation stabilization time following reset release is 215/fX (because the initial value of the OSTS register = 01H). 4. The oscillation stabilization time is also inserted during external clock input. Remark fX: Main clock oscillation frequency
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19.3 HALT Mode
19.3.1 Setting and operation status The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode. In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped; clock supply to the other on-chip peripheral functions continues. As a result, program execution is stopped, and the internal RAM retains the contents before the HALT mode was set. The on-chip peripheral functions that are independent of instruction processing by the CPU continue operating. Table 19-3 shows the operation status in the HALT mode. The average power consumption of the system can be reduced by using the HALT mode in combination with the normal operation mode for intermittent operation. Cautions 1. Insert five or more NOP instructions after the HALT instruction. 2. If the HALT instruction is executed with an unmasked interrupt request signal held pending, the system shift to the HALT mode, but the HALT mode is immediately released by the pending interrupt request signal. 19.3.2 Releasing HALT mode The HALT mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT1, INTWDT2 signal), an unmasked maskable interrupt request signal, and reset signal (RESET pin input, WDTRES1, WDTRES2 signal). After the HALT mode has been released, the normal operation mode is restored. (1) Releasing HALT mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The HALT mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request. If the HALT mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, only the HALT mode is released, and that interrupt request signal is not acknowledged. The interrupt request signal itself is retained. (b) If an interrupt request with a priority higher than that of the interrupt request signal currently being serviced is issued (including a non-maskable interrupt request signal), the HALT mode is released and that interrupt request signal is acknowledged. Table 19-2. Operation After Releasing HALT Mode by Interrupt Request Signal
Release Source Non-maskable interrupt request signal Maskable interrupt request signal Interrupt Enabled (EI) Status Execution branches to the handler address Execution branches to the handler address or the next instruction is executed The next instruction is executed Interrupt Disabled (DI) Status
(2) Releasing HALT mode by reset The same operation as the normal reset operation is performed.
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Table 19-3. Operation Status in HALT Mode
Setting of HALT Mode Item CPU Main clock oscillator Subclock oscillator Interrupt controller Timer P (TMP0) 16-bit timer (TM01) 8-bit timers (TM50, TM51) Timer H (TMH0, TMH1) Watch timer Operable Operable Operable Operable Operable Operable when main clock output is selected as count clock Watchdog timer 1 Watchdog timer 2 Operable Operable when main clock is selected as count clock Serial interface CSI00, CSI01 I C0 UART0, UART1 Key interrupt function A/D converter Real-time output Port function Internal data
2
When CPU Is Operating with Main Clock When Subclock Is Not Used Stops operation Oscillation enabled - Oscillation enabled When Subclock Is Used
Operable
Operable
Operable Operable Operable Operable Operable Operable Retains status before HALT mode was set. The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the HALT mode was set.
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19.4 IDLE Mode
19.4.1 Setting and operation status The IDLE mode is set by clearing the PSMR.PSM bit to 0 and setting the PSC.STP bit to 1 in the normal operation mode. In the IDLE mode, the clock oscillator continues operation but clock supply to the CPU and other on-chip peripheral functions stops. As a result, program execution stops and the contents of the internal RAM before the IDLE mode was set are retained. The CPU and other on-chip peripheral functions stop operating. However, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. Table 19-5 shows the operation status in the IDLE mode. The IDLE mode can reduce the power consumption more than the HALT mode because it stops the operation of the on-chip peripheral functions. The main clock oscillator does not stop, so the normal operation mode can be restored without waiting for the oscillation stabilization time after the IDLE mode has been released, in the same manner as when the HALT mode is released. Caution Insert five or more NOP instructions after the instruction that stores data in the PSC register to set the IDLE mode.
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19.4.2 Releasing IDLE mode The IDLE mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal (when the CPU is operating on the subclock)), unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the IDLE mode, or reset (RESET pin input, WDTRES2 signal (when the CPU is operating on the subclock)). After the IDLE mode has been released, the normal operation mode is restored. (1) Releasing IDLE mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The IDLE mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request. If the IDLE mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is processed as follows. (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, only the IDLE mode is released, and that interrupt request signal is not acknowledged. The interrupt request signal itself is retained. (b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the IDLE mode is released and that interrupt request signal is acknowledged. Table 19-4. Operation After Releasing IDLE Mode by Interrupt Request Signal
Release Source Non-maskable interrupt request signal Maskable interrupt request signal Interrupt Enabled (EI) Status Execution branches to the handler address Execution branches to the handler address or the next instruction is executed The next instruction is executed Interrupt Disabled (DI) Status
Caution The interrupt request signal that is disabled by setting the PSC.NMI2M, PSC.NMI0M, and PSC.INTM bits to 1 (interrupt disabled) becomes invalid and the IDLE mode is not released. (2) Releasing IDLE mode by reset The same operation as the normal reset operation is performed.
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Table 19-5. Operation Status in IDLE Mode
Setting of IDLE Mode Item CPU Main clock oscillator Subclock oscillator Interrupt controller Timer P (TMP0) 16-bit timer (TM01) Stops operation Stops operation Operable when INTWT is selected as count Operable when INTWT is selected as clock and fBRG is selected as count clock of WT 8-bit timers (TM50, TM51) * Operable when TI5m is selected as count clock * Operable when INTTM010 is selected as count clock and TM01 is enabled in IDLE mode Timer H (TMH0) Timer H (TMH1) Watch timer Stops operation Stops operation Operable when main clock is selected as count clock Watchdog timer 1 Watchdog timer 2 Serial interface CSI00, CSI01 I C0 UART0 UART1 Key interrupt function A/D converter Regulator Real-time output
2
When CPU Is Operating with Main Clock When Subclock Is Not Used Stops operation Oscillation enabled - Oscillation enabled When Subclock Is Used
count clock
Operable when fXT is selected as count clock Operable
Stops operation Stops operation Operable when fXT is selected as count clock
Operable when SCK0m input clock is selected as operation clock Stops operation Operable when ASCK0 is selected as count clock Stops operation Operable Stops operation
Note
Operation continues Operable when INTTM5m is selected as real-time output trigger and TM5m is enabled in IDLE mode. However, the RTBH0 and RTBL0 registers cannot be updated because the CPU is stopped.
Port function Internal data
Retains status before IDLE mode was set. The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the IDLE mode was set.
Note By setting the ADM.ADCS and ADM.ADCS2 bits to 00B before the IDLE mode is set, power consumption can be reduced. Remark m = 0, 1
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19.5 STOP Mode
19.5.1 Setting and operation status The STOP mode is set when the PSMR.PSM bit is set to 1 and the PSC.STP bit is set to 1 in the normal operation mode. In the STOP mode, the subclock oscillator continues operating but the main clock oscillator stops. Clock supply to the CPU and the on-chip peripheral functions is stopped. As a result, program execution is stopped, and the contents of the internal RAM before the STOP mode was set are retained. The on-chip peripheral functions that operate with the clock oscillated by the subclock oscillator or an external clock continue operating. Table 19-7 shows the operation status in the STOP mode. Because the STOP stops operation of the main clock oscillator, it reduces the power consumption to a level lower than the IDLE mode. If the subclock oscillator and external clock are not used, the power consumption can be minimized with only leakage current flowing. Caution Insert five or more NOP instructions after the instruction that stores data in the PSC register to set the STOP mode.
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19.5.2 Releasing STOP mode The STOP mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal (when the CPU is operating on the subclock)), unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the STOP mode, or reset (RESET pin input, WDTRES2 signal (when the CPU is operating on the subclock)). After the STOP mode has been released, the normal operation mode is restored after the oscillation stabilization time has been secured. (1) Releasing STOP mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The STOP mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request. If the software STOP mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, only the STOP mode is released, and that interrupt request signal is not acknowledged. The interrupt request signal itself is retained. (b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the STOP mode is released and that interrupt request signal is acknowledged. Table 19-6. Operation After Releasing STOP Mode by Interrupt Request Signal
Release Source Non-maskable interrupt request signal Maskable interrupt request signal Interrupt Enabled (EI) Status Execution branches to the handler address Execution branches to the handler address or the next instruction is executed The next instruction is executed Interrupt Disabled (DI) Status
Caution The interrupt request signal that is disabled by setting the PSC.NMI2M, PSC.NMI0M, and PSC.INTM bits to 1 (interrupt disabled) becomes invalid and the STOP mode is not released. (2) Releasing STOP mode by reset The same operation as the normal reset operation is performed.
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Table 19-7. Operation Status in STOP Mode
Setting of STOP Mode Item CPU Main clock oscillator Subclock oscillator Interrupt controller Timer P (TMP0) 16-bit timer (TM01) Stops operation Stops operation Stops operation Operable when INTWT is selected as count clock and fXT is selected as count clock of WT 8-bit timers (TM50, TM51) Operable when TI5m is selected as count clock Operable when TI5m is selected as count clock or when INTTM010 is selected as count clock and TM01 is enabled in STOP mode Timer H (TMH0) Timer H (TMH1) Watch timer Watchdog timer 1 Watchdog timer 2 Serial interface CSI00, CSI01 I C0 UART0 UART1 Key interrupt function A/D converter Real-time output
2
When CPU Is Operating with Main Clock When Subclock Is Not Used Stops operation Oscillation stops - Oscillation enabled When Subclock Is Used
Stops operation Stops operation Stops operation Stops operation Stops operation Operable when fXT is selected as count clock Operable when fXT is selected as count clock Operable when fXT is selected as count clock
Operable when SCK0m input clock is selected as operation clock Stops operation Operable when ASCK0 is selected as count clock Stops operation Operable Stops operation
Note
Operable when INTTM5m is selected as real-time output trigger and TM5m is enabled in STOP mode. However, the RTBH0 and RTBL0 registers cannot be updated because the CPU is stopped.
Port function Internal data
Retains status before STOP mode was set. The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the STOP mode was set.
Note By setting the ADM.ADCS and ADM.ADCS2 bits to 00B before the STOP mode is set, power consumption can be reduced. Remark m = 0, 1
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19.5.3 Securing oscillation stabilization time when STOP mode is released When the STOP mode is released, only the oscillation stabilization time set by the OSTS register elapses. If the STOP mode has been released by reset, however, the reset value of the OSTS register, 215/fX (8.192 ms at fX = 4 MHz) elapses. The operation performed when the STOP mode is released by an interrupt request signal is shown below. Figure 19-2. Oscillation Stabilization Time
Oscillated waveform Main clock
STOP mode status
Interrupt request Main clock oscillator stops Oscillation stabilization time count
Caution For details of the OSTS register, refer to 19.2 (3) register (OSTS).
Oscillation stabilization time selection
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19.6 Subclock Operation Mode
19.6.1 Setting and operation status The subclock operation mode is set when the PCC.CK3 bit is set to 1 in the normal operation mode. When the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock. When the PCC.MCK bit is set to 1, the operation of the main clock oscillator is stopped. As a result, the system operates only with the subclock. Table 19-8 shows the operation status in subclock operation mode. In the subclock operation mode, the power consumption can be reduced to a level lower than in the normal operation mode because the subclock is used as the internal system clock. In addition, the power consumption can be further reduced to the level of the STOP mode by stopping the operation of the main clock oscillator. Cautions 1. When manipulating the CK3 bit, do not change the set values of the PCC.CK2 to PCC.CK0 bits (using a bit manipulation instruction to manipulate the bit is recommended). For details, refer to 5.3 (1) Processor clock control register (PCC). 2. If the following conditions are not satisfied, change the CK2 to CK0 bits so that the conditions are satisfied and set the subclock operation mode. Internal system clock (fCLK) > Subclock (fXT: 32.768 kHz) x 4 Remark Internal system clock (fCLK): Clock generated from the main clock (fXX) by setting bits CK2 to CK0
19.6.2 Releasing subclock operation mode The subclock operation mode is released when the CK3 bit is cleared to 0 or by reset (RESET pin input, WDTRES1, WDTRES2 signal). If the main clock is stopped (MCK bit = 1), set the MCK bit to 1, secure the oscillation stabilization time of the main clock by software, and clear the CK3 bit to 0. The normal operation mode is restored when the subclock operation mode is released. Caution When manipulating the CK3 bit, do not change the set values of the CK2 to CK0 bits (using a bit manipulation instruction to manipulate the bit is recommended). For details, refer to 5.3 (1) Processor clock control register (PCC).
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Table 19-8. Operation Status in Subclock Operation Mode
Setting of Subclock Operation Item CPU Subclock oscillator Interrupt controller Timer P (TMP0) 16-bit timer (TM01) Mode Operation Status When Main Clock Is Oscillating Operable Oscillation enabled Operable Operable Operable Stops operation Operable when INTWT is selected as count clock and fXT is selected as count clock of WT 8-bit timers (TM50, TM51) Operable * Operable when TI5m is selected as count clock * Operable when INTTM010 is selected as count clock and when TM01 is enabled in subclock operation mode Timer H (TMH0) Timer H (TMH1) Watch timer Watchdog timer 1 Watchdog timer 2 Serial interface CSI00, CSI01
2
When Main Clock Is Stopped
Operable Operable Operable Stops operation Operable Operable
Stops operation Operable when fXT is selected as count clock Operable when fXT is selected as count clock
Operable when fXT is selected as count clock Operable when SCK0m input clock is selected as operation clock
I C0 UART0
Operable Operable
Stops operation Operable when ASCK0 is selected as count clock
UART1 Key interrupt function A/D converter Real-time output
Operable Operable Operable Operable
Stops operation
Stops operation Operable when INTTM5m is selected as real-time output trigger and TI5m is selected as count clock of TM5m
Port function Internal data
Settable Settable
Remark m = 0, 1
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19.7 Sub-IDLE Mode
19.7.1 Setting and operation status The sub-IDLE mode is set when the PSMR.PSM bit is cleared to 0 and the PSC.STP bit is set to 1 in the subclock operation mode. In this mode, the clock oscillator continues operation but clock supply to the CPU and the other on-chip peripheral functions is stopped. As a result, program execution is stopped and the contents of the internal RAM before the sub-IDLE mode was set are retained. The CPU and the other on-chip peripheral functions are stopped. However, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. Table 19-10 shows the operation status in the sub-IDLE mode. Because the sub-IDLE mode stops operation of the CPU and other on-chip peripheral functions, it can reduce the power consumption more than the subclock operation mode. If the sub-IDLE mode is set after the main clock has been stopped, the power consumption can be reduced to a level as low as that in the STOP mode. Caution Following the store instruction to set the PSC register to the sub-IDLE mode, insert five or more NOP instructions.
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19.7.2 Releasing sub-IDLE mode The sub-IDLE mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal (when the CPU is operating on the subclock)), unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the sub-IDLE mode, or reset (RESET pin input, WDTRES2 signal (when the CPU is operating on the subclock)). When the sub-IDLE mode is released by an interrupt request signal, the subclock operation mode is set. If it is released by reset, the normal operation mode is restored. (1) Releasing sub-IDLE mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The sub-IDLE mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request. If the sub-IDLE mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is serviced as follows. (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, only the sub-IDLE mode is released, and that interrupt request signal is not acknowledged. The interrupt request signal itself is retained. (b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the sub-IDLE mode is released and that interrupt request signal is acknowledged. Table 19-9. Operation After Releasing Sub-IDLE Mode by Interrupt Request Signal
Release Source Non-maskable interrupt request signal Maskable interrupt request signal Interrupt Enabled (EI) Status Execution branches to the handler address Execution branches to the handler address or the next instruction is executed The next instruction is executed Interrupt Disabled (DI) Status
Caution The interrupt request signal that is disabled by setting the PSC.NMI2M, PSC.NMI0M, and PSC.INTM bits to 1 (interrupt disabled) becomes invalid and the sub-IDLE mode is not released. (2) Releasing sub-IDLE mode by reset The same operation as the normal reset operation is performed.
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Table 19-10. Operation Status in Sub-IDLE Mode
Setting of Sub-IDLE Item CPU Subclock oscillator Interrupt controller Timer P (TMP0) 16-bit timer (TM01) Mode Operation Status When Main Clock Is Oscillating Stops operation Oscillation enabled Stops operation Stops operation Operable when INTWT is selected as count Operable when INTWT is selected as clock count clock and fXT is selected as count clock of WT 8-bit timers (TM50, TM51) * Operable when TI5m is selected as count clock * Operable when INTTM010 is selected as count clock and when TM01 is enabled in sub-IDLE mode Timer H (TMH0) Timer H (TMH1) Watch timer Watchdog timer 1 Watchdog timer 2 Serial interface CSI00, CSI01 I C0 UART0 UART1 Key interrupt function A/D converter Real-time output
2
When Main Clock Is Stopped
Stops operation Operable when fXT is selected as count clock Operable Stops operation Operable when fXT is selected as count clock Operable when SCK0m input clock is selected as operation clock Stops operation Operable when ASCK0 is selected as count clock Stops operation Operable Stops operation
Note
Operable when fXT is selected as count clock
Operable when INTTM5m is selected as real-time output trigger and TM5m is set to the operable conditions of the sub-IDLE mode
Port function Internal data
Retains status before sub-IDLE mode was set. The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the sub-IDLE mode was set.
Note By setting the ADM.ADCS and ADM.ADCS2 bits to 00B before the sub-IDLE mode is set, power consumption can be reduced. Remark m = 0, 1
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20.1 Overview
The following reset functions are available. * Reset function by RESET pin input * Reset function by overflow of watchdog timer 1 (WDTRES1) * Reset function by overflow of watchdog timer 2 (WDTRES2) If the RESET pin goes high, the reset status is released, and the CPU starts executing the program. Initialize the contents of each register in the program as necessary. The RESET pin has a noise eliminator that operates by analog delay to prevent malfunction caused by noise.
20.2 Configuration
Figure 20-1. Reset Block Diagram
RESET
Analog delay circuit Reset signal to CPU WDTRES1 issued due to overflow
Reset signal to CG Reset controller Reset signal to other peripheral macros
Count clock
Watchdog timer 1
Count clock
Watchdog timer 2 WDTRES2 issued due to overflow
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20.3 Operation
The system is reset, initializing each hardware unit, when a low level is input to the RESET pin or if watchdog timer 1 or watchdog timer 2 overflows (WDTRES1 or WDTRES2). While a low level is being input to the RESET pin, the main clock oscillator stops. Therefore, the overall power consumption of the system can be reduced. If the RESET pin goes high or if the WDTRES1 or WDTRES2 signal is received, the reset status is released. If the reset status is released by RESET pin input or the WDTRES2 signal, the oscillation stabilization time elapses (reset value of OSTS register: 215/fXX) and then the CPU starts program execution. If the reset status is released by the WDTRES1 signal, the oscillation stabilization time is not inserted because the main system clock oscillator does not stop.
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Table 20-1. Hardware Status on RESET Pin Input or Occurrence of WDTRES2 Signal
Item Main clock oscillator (fX) Subclock oscillator (fXT) Peripheral clock (fXX to fXX/1024) During Reset Oscillation stops Oscillation continues Operation stops Operation starts after securing oscillation stabilization time Internal system clock (fCLK) Operation stops Operation starts after securing oscillation stabilization time (initialized to fXX/8) CPU clock (fCPU) Operation stops Operation starts after securing oscillation stabilization time (initialized to fXX/8) Watchdog timer 1 clock (fXW) CPU Operation stops Initialized Operation starts Program execution starts after securing oscillation stabilization time Internal RAM Undefined if power-on reset or writing data to RAM (by CPU or DMA) and reset input conflict (data is damaged). Otherwise value immediately before reset input is retained. I/O lines On-chip peripheral I/O registers Watchdog timer 2 High impedance Initialized to specified status Operation stops Operation starts after securing oscillation stabilization time Other on-chip peripheral functions Operation stops Operation can be started after securing oscillation stabilization time After Reset Oscillation starts
Table 20-2. Hardware Status on Occurrence of WDTRES1 Signal
Item Main clock oscillator (fX) Subclock oscillator (fXT) Peripheral clock (fXX to fXX/1024) Internal system clock (fCLK) CPU clock (fCPU) Watchdog timer 1 clock (fXW) Internal RAM During Reset Oscillation continues Oscillation continues Operation stops Oscillation continues (initialized to fXX/8) Oscillation continues (initialized to fXX/8) Operation continues Undefined if writing data to RAM (by CPU or DMA) and reset input conflict (data is damaged). Otherwise value immediately before reset input is retained. I/O lines On-chip peripheral I/O registers Watchdog timer 2 Other on-chip peripheral functions High impedance Initialized to specified status Operation stops Operation stops Operation starts Operation can be started Operation starts After Reset
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Figure 20-2. Hardware Status on RESET Input
fX
fCLK Initialized to fXX/8 operation
RESET
Analog delay (eliminated as noise) Internal system reset signal
Analog Analog delay Analog delay (eliminated as noise) delay
Oscillation stabilization time count
Overflow of timer for oscillation stabilization
Figure 20-3. Operation on Power Application
VDD
fX
fCLK Initialized to fXX/8 operation
RESET Analog delay Internal system reset signal Oscillation stabilization time count
Overflow of timer for oscillation stabilization
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Figure 20-4. Timing of Reset Operation by Watchdog Timer 1
fX
fCLK Initialized to fXX/8 operation WDTRES1 signal (active low) Internal system reset signal (active low) fCLK: 12-clock width
Figure 20-5. Timing of Reset Operation by Watchdog Timer 2
fX
fCLK Initialized to fXX/8 operation WDTRES2 signal (active low)
Analog delay Internal system reset signal (active low) Oscillation stabilization time count
Overflow of oscillation stabilization time counter
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Caution
For the electrical specifications related to the flash memory rewriting, refer to CHAPTER 23 ELECTRICAL SPECIFICATIONS (TARGET).
Flash memory versions are commonly used in the following development environments and mass production applications. For altering software after the V850ES/KE2 is soldered onto the target system. For data adjustment when starting mass production. For differentiating software according to the specification in small scale production of various models. For facilitating inventory management. For updating software after shipment.
21.1 Features
4-byte/1-clock access (when instruction is fetched) Capacity: 128 KB Write voltage: Erase/write with a single power supply Rewriting method * Rewriting by communication with dedicated flash programmer via serial interface (on-board/off-board programming) * Rewriting flash memory by user program (self programming) Flash memory write prohibit function supported (security function) Safe rewriting of entire flash memory area by self programming using boot swap function Interrupts can be acknowledged during self programming.
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21.2 Memory Configuration
The 128 KB internal flash memory area is divided into 64 blocks and can be programmed/erased in block units. All the blocks can also be erased at once. When the boot swap function is used, the physical memory (blocks 0 to 3) located at the addresses of boot area 0 is replaced by the physical memory (blocks 4 to 7) located at the addresses of boot area 1. For details of the boot swap function, refer to 21.5 Rewriting by Self Programming. Figure 21-1. Flash Memory Mapping
3FFFFFFH 3FEC000H 3FEBFFFH
On-chip peripheral I/O area (4 KB) Internal RAM area (60 KB)
3FF0000H 3FEFFFFH
001FFFFH Block 63 (2 KB) 0005000H 0004FFFH 0004800H 00047FFH Block 8 (2 KB) 0004000H 0003FFFH Block 7 (2 KB) Use prohibited Block 6 (2 KB) 0003000H 0002FFFH Block 5 (2 KB) 0002800H 00027FFH Block 4 (2 KB) 0002000H 0001FFFH Block 3 (2 KB) 0001800H 00017FFH Block 2 (2 KB) 0001000H 0000FFFH 0020000H 001FFFFH Internal flash memory area (128 KB) 0000000H Block 1 (2 KB) 0000800H 00007FFH Block 0 (2 KB) 0000000H Boot area 0Note (8 KB) Boot area 1Note (8 KB) 0003800H 00037FFH
Note Boot area 0 (blocks 0 to 3): Boot area Boot area 1 (blocks 4 to 7): Area to be replaced with the boot area by the boot swap function
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21.3 Functional Outline
The internal flash memory of the V850ES/KE2 can be rewritten by using the rewrite function of the dedicated flash programmer, regardless of whether the V850ES/KE2 has already been mounted on the target system or not (onboard/off-board programming). In addition, a security function that prohibits rewriting the user program written to the internal flash memory is also supported, so that the program cannot be changed by an unauthorized person. The rewrite function using the user program (self programming) is ideal for an application where it is assumed that the program is changed after production/shipment of the target system. A boot swap function that rewrites the entire flash memory area safely is also supported. In addition, interrupt servicing is supported during self programming, so that the flash memory can be rewritten under various conditions, such as while communicating with an external device. Table 21-1. Rewrite Method
Rewrite Method On-board programming Functional Outline Flash memory can be rewritten after the device is mounted on the target system, by using a dedicated flash programmer. Flash memory can be rewritten before the device is mounted on the target system, by using a dedicated flash programmer and a dedicated program adapter board (FA series). Self programming Flash memory can be rewritten by executing a user program that has been written to the flash memory in advance by means of on-board/offboard programming. (During self-programming, instructions cannot be fetched from or data access cannot be made to the internal flash memory area. Therefore, the rewrite program must be transferred to the internal RAM or external memory in advance). Normal operation mode Operation Mode Flash memory programming mode
Off-board programming
Remark
The FA series is a product of Naito Densei Machida Mfg. Co., Ltd.
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Table 21-2. Basic Functions
Function Functional Outline Support ( : Supported, x: Not supported) On-Board/Off-Board Programming Block erasure The contents of specified memory blocks are erased. The contents of the entire memory area are erased all at once. Write Writing to specified addresses, and a verify check to see if write level is secured are performed. Verify/checksum Data read from the flash memory is compared with data transferred from the flash programmer. Blank check The erasure status of the entire memory is checked. Security setting Use of the block erase command, chip erase command, and program command can be prohibited. x (Supported only when setting is changed from enable to disable) x (Can be read by user program) x Self Programming
Chip erasure
The following table lists the security functions. The block erase command prohibit, chip erase command prohibit, and program command prohibit functions are enabled by default after shipment, and security can be set by rewriting via on-board/off-board programming. Each security function can be used in combination with the others at the same time. Table 21-3. Security Functions
Function Function Outline Rewriting Operation When Prohibited ( : Executable, x: Not Executable) On-Board/Off-Board Programming Block erase command prohibit Execution of a block erase command on all blocks is prohibited. Setting of prohibition can be initialized by execution of a chip erase command. Execution of block erase and chip erase commands on all the blocks is prohibited. Once prohibition is set, setting of prohibition cannot be initialized because the chip erase command cannot be executed. Program command prohibit Write and block erase commands on all the blocks are prohibited. Setting of prohibition can be initialized by execution of the chip erase command. Block erase command: x Chip erase command: Program command: x Block erase command: x Chip erase command: Program command: Block erase command: x Chip erase command: x Program command: Can always be rewritten regardless of setting of prohibition Self Programming
Chip erase command prohibit
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21.4 Rewriting by Dedicated Flash Programmer
The flash memory can be rewritten by using a dedicated flash programmer after the V850ES/KE2 is mounted on the target system (on-board programming). The flash memory can also be rewritten before the device is mounted on the target system (off-board programming) by using a dedicated program adapter (FA series). 21.4.1 Programming environment The following shows the environment required for writing programs to the flash memory of the V850ES/KE2. Figure 21-2. Environment Required for Writing Programs to Flash Memory
RS-232C
XXXX YYYY
FLMD0 FLMD1
Bxxxxx Cxxxxxx
XXXX XXXXXX
Axxxx
XXX YYY
PG-FP4 (Flash Pro4)
USB Dedicated flash programmer Host machine
XXXXX
STATVE
VDD VSS RESET UART0/CSI00 V850ES/KE2
A host machine is required for controlling the dedicated flash programmer. UART0 or CSI00 is used for the interface between the dedicated flash programmer and the V850ES/KE2 to perform writing, erasing, etc. A dedicated program adapter (FA series) is required for off-board writing. Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd.
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21.4.2 Communication mode Communication between the dedicated flash programmer and the V850ES/KE2 is performed by serial communication using the UART0 or CSI00 interfaces of the V850ES/KE2. (1) UART0 Transfer rate: 9,600 to 153,600 bps Figure 21-3. Communication with Dedicated Flash Programmer (UART0)
FLMD0 FLMD1
XXXX YYYY
FLMD0 FLMD1
Bxxxxx Cxxxxxx
STATVE
XXX YYY
XXXXX
XXXX
XXXXXX
Axxxx
VDD GND RESET RxD TxD CLK
VDD VSS RESET TXD0 RXD0 X1 X2 V850ES/KE2
PG-FP4 (Flash Pro4)
Dedicated flash programmer
(2) CSI00 Serial clock: 2.4 kHz to 2.5 MHz (MSB first) Figure 21-4. Communication with Dedicated Flash Programmer (CSI00)
FLMD0 FLMD1
FLMD0 FLMD1
VDD
XXXXXX
VDD VSS RESET SO00 SI00 SCK00 X1 X2 V850ES/KE2
Axxxx
XXXX YYYY
Bxxxxx Cxxxxxx
STATVE
GND RESET
XXX YYY
PG-FP4 (Flash Pro4)
XXXXX
XXXX
Dedicated flash programmer
SI SO SCK CLK
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(3) CSI00 + HS Serial clock: 2.4 kHz to 2.5 MHz (MSB first) Figure 21-5. Communication with Dedicated Flash Programmer (CSI00 + HS)
FLMD0 FLMD1
FLMD0 FLMD1
VDD
XXXX YYYY
VDD VSS RESET SO00 SI00 SCK00 X1 X2 V850ES/KE2
Bxxxxx Cxxxxxx
STATVE
XXXX
XXXXXX
Axxxx
GND RESET SI SO SCK CLK
XXX YYY
PG-FP4 (Flash Pro4)
Dedicated flash programmer
XXXXX
HS
PCM0
The dedicated flash programmer outputs the transfer clock, and the V850ES/KE2 operates as a slave. When the PG-FP4 is used as the dedicated flash programmer, it generates the following signals to the V850ES/KE2. For details, refer to the PG-FP4 User's Manual (U15260E). Table 21-4. Signal Connections of Dedicated Flash Programmer (PG-FP4)
PG-FP4 Signal Name FLMD0 FLMD1 VDD GND CLK RESET SI/RxD SO/TxD SCK HS I/O Output Output - - Output Output Input Output Output Input Pin Function Write enable/disable Write enable/disable VDD voltage generation/voltage monitor Ground Clock output to V850ES/KE2 Reset signal Receive signal Transmit signal Transfer clock Handshake signal for CSI00 + HS communication V850ES/KE2 Pin Name FLMD0 FLMD1 VDD VSS X1, X2 RESET SO00 SI00 SCK00 PCM0 x x x x
Note 2 Note 1 Note 1 Note 1
Processing for Connection UART0 CSI00 CSI00 + HS
x
Note 2
x
Note 2
Notes 1. Wire the pin as shown in Figure 21-6, or connect it to GND on board via a pull-down resistor. 2. Connect these pins to supply a clock from the PG-FP4 (wire as shown in Figure 21-6, or create an oscillator on board and supply the clock). Remark : Must be connected. x: Does not have to be connected.
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Table 21-5. Wiring Between V850ES/KE2 and PG-FP4
Pin Configuration of Flash Programmer (PG-FP4) Signal Name SI/RXD SO/TXD I/O Input Output Pin Function Receive signal Transmit signal Pin Name on FA Board SI SO With CSI00-HS Pin Name P41/SO00 P40/SI00 Pin No. 20 19 With CSI00 Pin Name P41/SO00 P40/SI00 Pin No. 20 19 With UART0 Pin Name P30/TXD0 Pin No. 22
P31/RXD0/ 23 INTP7
SCK CLK
Output Output
Transfer clock Clock to V850ES/KE2
SCK X1 X2
P42/SCK00 21 X1 X2
Note
P42/SCK00 21 X1 X2
Note
Not needed Not needed X1 X2
Note
7 8 9 3 52
7 8 9 3 52
7 8 9 3 52
/RESET FLMD0 FLMD1
Output Input Input
Reset signal Write voltage Write voltage
/RESET FLMD0 FLMD1
RESET FLMD0 PDL5/ FLMD1
RESET FLMD0 PDL5/ FLMD1
RESET FLMD0 PDL5/ FLMD1
HS
Input
Handshake signal for CSI00 + HS communication
RESERVE /HS
PCM0
45
Not needed Not needed Not needed Not needed
VDD
-
VDD voltage generation/voltage monitor
VDD
VDD EVDD AVREF0
4 33 1 6 2 32
VDD EVDD AVREF0 VSS AVSS EVSS
4 33 1 6 2 32
VDD EVDD AVREF0 VSS AVSS EVSS
4 33 1 6 2 32
GND
-
Ground
GND
VSS AVSS EVSS
Note When using the clock out of the flash programmer, connect CLK of the programmer to X1, and connect its inverse signal to X2.
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Figure 21-6. Wiring Example of V850ES/KE2 Flash Writing Adapter (FA-64GB-8EU-A) (1/2)
VD
D G N D
D VD D N G
45
33 32
52
Note 1
PD70F3726
23
Note 3
22
21
Connect to GND. Connect to VDD.
20
19
Note 2
1 2 3 4 6 7 8 9
G
N
D VD D
G N D
CLKIN SI SO SCK X1 X2 /RESET VPP RESERVE/HS RFU-3 RFU-2 RFU-1 VDE FLMD1 FLMD0 SI SO SCK CLKOUT /RESET VPP RESERVE/HS
VD D
J1 VDD2 VDD
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Figure 21-6. Wiring Example of V850ES/KE2 Flash Writing Adapter (FA-64GB-8EU-A) (2/2)
Notes 1. Wire the FLMD1 pin as shown in the figure, or connect it to GND on board via a pull-down resistor. 2. The above figure shows an example of wiring when the clock is supplied from the PG-FP4. Be sure to set and connect as follows when the clock is supplied from the PG-FP4. * Set J1 of the flash adapter (FA) to the VDD side. * Connect CLKOUT of FA to CLKIN of FA. * Connect X1 of FA to X1 of the device. * Connect X2 of FA to X2 of the device. If an oscillator is created on the flash adapter and a clock is supplied, the above setting and connections will not necessary. The following shows a circuit example.
X1 X2
3. Corresponding pin when using UART0 Remarks 1. Handle the pins not described above in accordance with the specified handling of unused pins (refer to 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins). When connecting to VDD via a resistor, use of a resistor of 1 k to 10 k is recommended. 2. This adapter is for a 64-pin plastic LQFP (fine pitch) package. 3. This diagram shows the wiring when using a handshake-supporting CSI.
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21.4.3 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 21-7. Procedure for Manipulating Flash Memory
Start
Supplies FLMD0 pulse
Switch to flash memory programming mode
Select communication system
Manipulate flash memory
End? Yes End
No
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21.4.4 Selection of communication mode In the V850ES/KE2, the communication mode is selected by inputting pulses (12 pulses max.) to the FLMD0 pin after switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated flash programmer. The following shows the relationship between the number of pulses and the communication mode. Figure 21-8. Selection of Communication Mode
VDD VDD VSS VDD RESET (input) VSS VDD FLMD1 (input) VSS VDD FLMD0 (input) VSS VDD RXD0 (input) VSS VDD TXD0 (output) VSS Oscillation stabilized Power on Reset released Communication mode selected Flash control command communication (erasure, write, etc.) (Note)
Note The number of clocks is as follows depending on the communication mode.
FLMD0 Pulse 0 8 11 Other Communication Mode UART0 CSI00 CSI00 + HS RFU Remarks Communication rate: 9600 bps (after reset), LSB first V850ES/KE2 performs slave operation, MSB first V850ES/KE2 performs slave operation, MSB first Setting prohibited
Caution
When UART0 is selected, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after receiving the FLMD0 pulse.
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21.4.5 Communication commands The V850ES/KE2 communicates with the dedicated flash programmer by means of commands. The signals sent from the dedicated flash programmer to the V850ES/KE2 are called "commands". The response signals sent from the V850ES/KE2 to the dedicated flash programmer are called "response commands". Figure 21-9. Communication Commands
Command
XXXX YYYY
Bxxxxx Cxxxxxx
XXX YYY
PG-FP4 (Flash Pro4)
XXXXX
STATVE
XXXX
XXXXXX
Axxxx
Response command V850ES/KE2
Dedicated flash programmer
The following shows the commands for flash memory control in the V850ES/KE2. All of these commands are issued from the dedicated flash programmer, and the V850ES/KE2 performs the processing corresponding to the commands. Table 21-6. Flash Memory Control Commands
Classification Command Name CSI00 Blank check Block blank check command Erase Chip erase command Block erase command Support CSI00 + HS UART0 Checks if the contents of the memory in the specified block have been correctly erased. Erases the contents of the entire memory. Erases the contents of the memory of the specified block. Write Write command Writes the specified address range, and executes a contents verify check. Verify Verify command Compares the contents of memory in the specified address range with data transferred from the flash programmer. Checksum command Reads the checksum in the specified address range. System setting, control Silicon signature command Security setting command Disables the chip erase command, block erase command, and write command. Reads silicon signature information. Function
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21.4.6 Pin connection When performing on-board writing, mount a connector on the target system to connect to the dedicated flash programmer. Also, incorporate a function on-board to switch from the normal operation mode to the flash memory programming mode. In the flash memory programming mode, all the pins not used for flash memory programming become the same status as that immediately after reset. Therefore, pin handling is required when the external device does not acknowledge the status immediately after a reset. (1) FLMD0 pin In the normal operation mode, input a voltage of VSS level to the FLMD0 pin. programming mode, supply a write voltage of VDD level to the FLMD0 pin. Because the FLMD0 pin serves as a write protection pin in the self programming mode, a voltage of VDD level must be supplied to the FLMD0 pin via port control, etc., before writing to the flash memory. For details, refer to 21.5.5 (1) FLMD0 pin. Figure 21-10. FLMD0 Pin Connection Example In the flash memory
V850ES/KE2 Dedicated flash programmer connection pin FLMD0
Pull-down resistor (RFLMD0)
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(2) FLMD1 pin When 0 V is input to the FLMD0 pin, the FLMD1 pin does not function. When VDD is supplied to the FLMD0 pin, the flash memory programming mode is entered, so 0 V must be input to the FLMD1 pin. The following shows an example of the connection of the FLMD1 pin. Figure 21-11. FLMD1 Pin Connection Example
V850ES/KE2
FLMD1
Other device
Pull-down resistor (RFLMD1)
Caution
If the VDD signal is input to the FLMD1 pin from another device during on-board writing and immediately after reset, isolate this signal.
Table 21-7. Relationship Between FLMD0 and FLMD1 Pins and Operation Mode When Reset Is Released
FLMD0 0 VDD VDD FLMD1 don't care 0 VDD Operation Mode Normal operation mode Flash memory programming mode Setting prohibited
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(3) Serial interface pin The following shows the pins used by each serial interface. Table 21-8. Pins Used by Serial Interfaces
Serial Interface UART0 CSI00 CSI00 + HS Pins Used TXD0, RXD0 SO00, SI00, SCK00 SO00, SI00, SCK00, PCM0
When connecting a dedicated flash programmer to a serial interface pin that is connected to another device on-board, care should be taken to avoid conflict of signals and malfunction of the other device. (a) Conflict of signals When the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status. Figure 21-12. Conflict of Signals (Serial Interface Input Pin)
V850ES/KE2 Conflict of signals Input pin Other device Output pin Dedicated flash programmer connection pins
In the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals another device outputs. Therefore, isolate the signals on the other device side.
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(b) Malfunction of other device When the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), the signal is output to the other device, causing the device to malfunction. To avoid this, isolate the connection to the other device. Figure 21-13. Malfunction of Other Device
V850ES/KE2 Dedicated flash programmer connection pin Pin Other device Input pin
In the flash memory programming mode, if the signal the V850ES/KE2 outputs affects the other device, isolate the signal on the other device side.
V850ES/KE2 Dedicated flash programmer connection pin Pin Other device Input pin
In the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side.
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(4) RESET pin When the reset signals of the dedicated flash programmer are connected to the RESET pin that is connected to the reset signal generator on-board, a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generator. When a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. Therefore, do not input signals other than the reset signals from the dedicated flash programmer. Figure 21-14. Conflict of Signals (RESET Pin)
V850ES/KE2 Conflict of signals RESET Reset signal generator Output pin Dedicated flash programmer connection pin
In the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. Therefore, isolate the signals on the reset signal generator side.
(5) Port pins (including NMI) When the system shifts to the flash memory programming mode, all the pins that are not used for flash memory programming are in the same status as that immediately after reset. If the external device connected to each port does not recognize the status of the port immediately after reset, pins require appropriate processing, such as connecting to VDD via a resistor or connecting to VSS via a resistor. (6) Other signal pins Connect X1, X2, XT1, and XT2 in the same status as that in the normal operation mode. (7) Power supply Supply the same power (VDD, VSS, EVDD, EVSS, AVSS, AVREF0) as in normal operation mode.
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21.5 Rewriting by Self Programming
21.5.1 Overview The V850ES/KE2 supports a flash macro service that allows the user program to rewrite the internal flash memory by itself. By using this interface and a self programming library that is used to rewrite the flash memory with a user application program, the flash memory can be rewritten by a user application transferred in advance to the internal RAM or external memory. Consequently, the user program can be upgraded and constant data can be rewritten in the field. Figure 21-15. Concept of Self Programming
Application program Self programming library Flash function execution Flash information Flash macro service Erase, write Flash memory
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21.5.2 Features (1) Secure self programming (boot swap function) The V850ES/KE2 supports a boot swap function that can exchange the physical memory (blocks 0 to 3) of boot area 0 with the physical memory (blocks 4 to 7) of boot area 1. By writing the start program to be rewritten to boot area 1 in advance and then swapping the physical memory, the entire area can be safely rewritten even if a power failure occurs during rewriting because the correct user program always exists in boot area 0. Figure 21-16. Rewriting Entire Memory Area (Boot Swap)
Block N
Block 63
Block 63
Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0 Rewriting boot areas 0 and 1
Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0
Boot swap
Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0
(2) Interrupt support Instructions cannot be fetched from the flash memory during self programming. Conventionally, therefore, a user handler written to the flash memory could not be used even if an interrupt occurred. Therefore, in the V850ES/KE2, to use an interrupt during self programming, processing transits to the specific addressNote in the internal RAM. Allocate the jump instruction that transits processing to the user interrupt servicing at the specific addressNote in the internal RAM. Note NMI interrupt: Start address of internal RAM
Maskable interrupt: Start address of internal RAM + 4 addresses
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21.5.3 Standard self programming flow The entire processing to rewrite the flash memory by flash self programming is illustrated below. Figure 21-17. Standard Self Programming Flow
(a) Rewriting at once
Flash memory manipulation
Flash environment initialization processing
(b) Rewriting in block units
Flash memory manipulation
Flash environment initialization processing
Erase processing
* Disable accessing flash area * Disable setting of STOP mode * Disable stopping clock
Erase processing
* Disable accessing flash area * Disable setting of STOP mode * Disable stopping clock
Write processing
Write processing
Internal verify processing
Flash information setting processingNote 1 Boot area swapping processingNote 2 Flash environment end processing
Internal verify processing
All blocks end? Yes
Flash information setting processingNote 1 Boot area swapping processingNote 2 Flash environment end processing
No
End of processing
End of processing
Notes 1. If a security setting is not performed, flash information setting processing does not have to be executed. 2. If boot swap is not used, flash information setting processing and boot area swap processing do not have to be executed.
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21.5.4 Flash functions Table 21-9. Main Flash Function List
Function Name FlashEnv FlashBlockErase FlashWordWrite FlashBlockIVerify FlashBlockBlankCheck FlashFLMDCheck FlashGetInfo FlashSetInfo FlashBootSwap FlashWordRead Outline Initialization of flash control macro Erasure of only specified one block Writing from specified address Internal verification of specified block Blank check of specified block Check of FLMD pin Reading of flash information Setting of flash information Swapping of boot area Reading data from specified address Support
Remark
For details, refer to the V850 Series Flash Memory Self Programming (Single Power Supply Flash Memory) User's Manual. Contact an NEC Electronics sales representative for the above manual.
21.5.5 Pin processing (1) FLMD0 pin The FLMD0 pin is used to set the operation mode when reset is released and to protect the flash memory from being written during self rewriting. It is therefore necessary to keep the voltage applied to the FLMD0 pin at 0 V when reset is released and a normal operation is executed. It is also necessary to apply a voltage of VDD level to the FLMD0 pin during the self programming mode period via port control before the memory is rewritten. When self programming has been completed, the voltage on the FLMD0 pin must be returned to 0 V. Figure 21-18. Mode Change Timing
RESET signal
VDD 0V Self programming mode VDD
FLMD0 pin
0V Normal operation mode Normal operation mode
Caution
Make sure that the FLMD0 pin is at 0 V when reset is released.
604
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21.5.6 Internal resources used The following table lists the internal resources used for self programming. These internal resources can also be used freely for purposes other than self programming. Table 21-10. Internal Resources Used
Resource Name Entry RAM area (internal RAM/external RAM size: 136 bytes) Stack area (stack size: 600 bytes) Description Routines and parameters used for the flash macro service are located in this area. The entry program and default parameters are copied by calling a library initialization function. An extension of the stack used by the user is used by the library (can be used in both the internal RAM and external RAM). Library code (code size: Approx. 1600 bytes) Application program Program entity of library (can be used anywhere other than the flash memory block to be manipulated). Executed as user application. Calls flash functions. Maskable interrupt Can be used in user application execution status or self programming status. To use this interrupt in the self-programming status, since the processing transits to the address of the internal RAM start address + 4 addresses (3FFE004H), allocate the jump instruction that transits the processing to the user interrupt servicing at the address of the internal RAM start address + 4 addresses (3FFE004H) in advance. NMI interrupt Can be used in user application execution status or self programming status. To use this interrupt in the self-programming status, since the processing transits to the address of the internal RAM start address (3FFE000H), allocate the jump instruction that transits the processing to the user interrupt servicing at the internal RAM start address (3FFE000H) in advance. TM50, TM51 Because TM50 and TM51 are used in the flash macro service, do not use them in the self programming status. When using TM50 and TM51 after self programming, set them again.
Remark
For details, refer to the V850 Series Flash Memory Self Programming (Single Power Supply Flash Memory) User's Manual. Contact an NEC Electronics sales representative for the above manual.
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CHAPTER 22 ON-CHIP DEBUG FUNCTION
The V850ES/KE2 is not provided with an on-chip debug function. However, a pseudo on-chip debug function can be realized by using the on-chip debug emulator (MINICUBE) and debug adapter (QB-V850ESKX1H-DA).
22.1 ROM Security Function
22.1.1 Security ID The flash memory versions of the V850ES/KE2 perform authentication using a 10-byte ID code to prevent the contents of the flash memory from being read by an unauthorized person during on-chip debugging by the on-chip debug emulator. Set the ID code in the 10-byte on-chip flash memory area from 0000070H to 0000079H to allow the debugger perform ID authentication. If the IDs match, the security is released and reading flash memory and using the on-chip debug emulator are enabled. * Set the 10-byte ID code to 0000070H to 0000079H. * Bit 7 of 0000079H is the on-chip debug emulator enable flag. (0: Disable, 1: Enable) * When the on-chip debug emulator is started, the debugger requests ID input. When the ID code input on the debugger and the ID code set in 0000070H to 0000079H match, the debugger starts. * Debugging cannot be performed if the on-chip debug emulator enable flag is 0, even if the ID codes match.
0000079H Security ID (10 bytes) 0000070H
0000000H
Caution When the data in the flash memory has been deleted, all the bits are set to 1.
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22.1.2 Setting The following shows how to set the ID code as shown in Table 22-1. When the ID code is set as shown in Table 22-1, the ID code input in the configuration dialog box of the ID850QB is "123456789ABCDEF123D4". Table 22-1. ID Code
Address 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x12 0x34 0x56 0x78 0x9A 0xBC 0xDE 0XF1 0x23 0xD4 Value
The ID code can be specified for the device file that supports the CA850 Ver. 2.60 or later and the security ID by the PM+ linker option setting.
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[Program example (when using CA850 Ver. 2.60 or later)]
#-------------------------------------# SECURITYID (continue ILGOP .section .word .word .hword Remark "SECURITY_ID" 0x78563412 0xF1DEBC9A 0xD423 handler) --Interrupt handler address 0x70 --0-3 byte code --4-7 byte code --8-9 byte code #--------------------------------------
Add the above program example to the startup files.
22.2 Cautions
(1) If a reset signal is input (from the target system or a reset signal from an internal reset source) during RUN (program execution), the break function may malfunction. (2) Even if the reset signal is masked by the mask function, the I/O buffer (port pin) may be reset if a reset signal is input from a pin. (3) Because a software breakpoint set in the internal flash memory is realized by the ROM correction function, it is made temporarily invalid by target reset or internal reset generated by watchdog timer 2. The breakpoint becomes valid again when a hardware break or forced break occurs, but a software break does not occur until then. (4) Pin reset during a break is masked and the CPU and peripheral I/O are not reset. If pin reset or internal reset is generated as soon as the flash memory is read by the RAM monitor function while the user program is being executed, the CPU and peripheral I/O may not be correctly reset.
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Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD AVREF0 EVDD VSS AVSS EVSS Input voltage VI1 Conditions VDD = EVDD = AVREF0 VDD = EVDD = AVREF0 VDD = EVDD = AVREF0 VSS = EVSS = AVSS VSS = EVSS = AVSS VSS = EVSS = AVSS P00 to P06, P30 to P35, P38, P39, P40 to P42, P50 to P55, P90, P91, P96 to P99, P913 to P915, PCM0, PCM1, PDL0 to PDL7, RESET, FLMD0 VI2 Analog input voltage Output current, low VIAN IOL X1, X2, XT1, XT2 P70 to P77 Note 2 P38, P39 P00 to P06, P30 to P35, P38, P39, P40 to P42 P50 to P55, P90, P91, P96 to P99, P913 to P915, PCM0, PCM1, PDL0 to PDL7 Output current, high IOH Note 2 P00 to P06, P30 to P35, P40 to P42 P50 to P55, P90, P91, P96 to P99, P913 to P915, PCM0, PCM1, PDL0 to PDL7 Operating ambient temperature Storage temperature TA Normal operation mode Flash memory programming mode Tstg Total of all pins: 70 mA Per pin -0.3 to VDD + 0.3
Note 1
Ratings -0.3 to +6.5 -0.3 to +6.5 -0.3 to +6.5 -0.3 to +0.3 -0.3 to +0.3 -0.3 to +0.3 -0.3 to EVDD + 0.3
Note 1
Unit V V V V V V V
V V mA mA mA mA
-0.3 to AVREF0 + 0.3 20 30 35 35
Note 1
Per pin Total of all pins: -60 mA
-10 -30 -30
mA mA mA
-40 to +85 -40 to +85 -40 to +125
C C C
Notes 1. Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage. 2. P00 to P06, P30 to P35, P40 to P42, P50 to P55, P90, P91, P96 to P99, P913 to P915, PCM0, PCM1, PDL0 to PDL7 Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other, or to VDD, VCC, and GND. Open-drain pins or open-collector pins, however, can be directly connected to each other. Direct connection of the output pins between an IC product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation.
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Capacitance (TA = 25C, VDD = EVDD = AVREF0 = VSS = EVSS = AVSS = 0 V)
Parameter Input capacitance I/O capacitance Symbol CI CIO Conditions fX = 1 MHz Unmeasured pins returned to 0 V P70 to P77 Note P38, P39 MIN. TYP. MAX. 15 15 20 Unit pF pF pF
Note P00 to P06, P30 to P35, P40 to P42, P50 to P55, P90, P91, P96 to P99, P913 to P915, PCM0, PCM1, PDL0 to PDL7 Remark fX: Main clock oscillation frequency
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Operating Conditions (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Parameter Internal system clock frequency Symbol fCLK In PLL mode Conditions VDD = 4.5 to 5.5 V VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V In clock-through mode Operating with subclock VDD = 2.7 to 5.5 V Note MIN. 0.25 0.25 0.25 0.0625 32.768 TYP. MAX. 20 16 10 10 Unit MHz MHz MHz MHz kHz
Note VDD = 2.7 to 5.5 V Internal System Clock Frequency vs. Supply Voltage
100
Internal system clock frequency fCLK [MHz]
20.0 16.0 10.0
1.0
0.1 0.032
0.01 2.0 2.5 2.7 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Supply voltage VDD [V]
PLL Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V, VSS = 0 V)
Parameter Input frequency Output frequency Lock time Symbol fX fXX tPLL After VDD reaches 2.7 V (MIN.) Conditions MIN. 2 8 TYP. MAX. 5 20 200 Unit MHz MHz
s
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Operating Conditions for EEPROM Emulation (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Parameter Internal system clock frequency Symbol fCLK In PLL mode Conditions VDD = 4.5 to 5.5 V VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V In clock-through mode VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V Operating with subclock Notes 1, 2 MIN. 0.25 0.25 0.25 0.0625 0.0625 32.768 TYP. MAX. 16 12 6 10 6 Unit MHz MHz MHz MHz MHz kHz
Notes 1. VDD = 2.7 to 5.5 V 2. Do not stop the main clock. Internal System Clock Frequency vs. Supply Voltage
100
Internal system clock frequency fCLK [MHz]
20.0 16.0 10.0 6.0
1.0
0.1 0.032
0.01 2.0 2.5 2.7 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Supply voltage VDD [V]
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Main Clock Oscillator Characteristics (1) Crystal resonator, ceramic resonator (TA = -40 to +85C, VDD = 2.7 to 5.5 V, VSS = 0 V)
Recommended Circuit Parameter Oscillation
X1 X2
Conditions In PLL mode VDD = 4.5 to 5.5 V VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V In clock through mode VDD = 2.7 to 5.5 V OSTS0 = 1
MIN. 2 2 2 2
TYP.
MAX. 5 4 2.5 10
Unit MHz MHz MHz MHz s s
frequency (fX)
Note 1
Oscillation stabilization time
Note 2
After reset is released
2 /fX Note 3
15
After STOP mode is released
Notes 1. Indicates only oscillator characteristics. 2. Time required to stabilize the resonator after reset or STOP mode is released. 3. The value differs depending on the OSTS register settings. (2) External clock (TA = -40 to +85C, VDD = 2.7 to 5.5 V, VSS = 0 V)
Recommended Circuit
X1 X2
Parameter X1, X2 input frequency (fX)
Note
Conditions In PLL mode VDD = 4.5 to 5.5 V VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V In clock through mode VDD = 2.7 to 5.5 V
MIN. 2 2 2 2
TYP.
MAX. 5 4 2.5 10
Unit MHz MHz MHz MHz
External clock
Note The duty ratio of the input waveform must be within 50% 5%. Cautions 1. When using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main clock is stopped and the device is operating on the subclock, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock.
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Subclock Oscillator Characteristics (1) Crystal resonator (TA = -40 to +85C, VDD = 2.7 to 5.5 V, VSS = 0 V)
Recommended Circuit Parameter Oscillation
XT1 XT2
Conditions
MIN. 32
TYP. 32.768
MAX. 35
Unit kHz
frequency (fXT)
Note 1
Oscillation stabilization time
Note 2
10
s
Notes 1. Indicates only oscillator characteristics. 2. Time required from when VDD reaches oscillation voltage range (2.7 V (MIN.)) to when the crystal resonator stabilizes. (2) External clock (TA = -40 to +85C, VDD = 2.7 to 5.5 V, VSS = 0 V)
Recommended Circuit
XT1 XT2
Parameter
Input frequency (fXT)
Note
Conditions
VDD = 2.7 to 5.5 V
MIN.
32
TYP.
MAX.
35
Unit
kHz
External clock
Note The duty ratio of the input waveform must be within 50% 5%. Cautions 1. When using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subclock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main clock oscillator. Particular care is therefore required with the wiring method when the subclock is used.
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DC Characteristics (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, VSS = EVSS = AVSS = 0 V) (1/3)
Parameter Output current, high Symbol IOH1 Conditions Per pin for P00 to P06, P30 to P35, P40 to P42, P50 to P55, P90, P91, P96 to P99, P913 to P915, PCM0, PCM1, PDL0 to PDL7 Total of P00 to P06, P30 to P35, P40 to P42 Total of P50 to P55, P90, P91, P96 to P99, P913 to P915, PCM0, PCM1, PDL0 to PDL7 Output current, low IOL1 Per pin for P00 to P06, P30 to P35, P40 to P42, P50 to P55, P90, P91, P96 to P99, P913 to P915, PCM0, PCM1, PDL0 to PDL7 Per pin for P38, P39 EVDD = 4.0 to 5.5 V EVDD = 2.7 to 5.5 V Total of P00 to P06, P30 to P35, P40 to P42 Total of P38, P39, P50 to P55, P90, P91, P96 to P99, P913 to P915, PCM0, PCM1, PDL0 to PDL7 Input voltage, high VIH1 VIH2 VIH3 VIH4 Input voltage, low VIL1 VIL2 VIL3 VIL4 Note 1 Note 2 P70 to P77 X1, X2, XT1, XT2 Note 1 Note 2 P70 to P77 X1, X2, XT1, XT2 0.7EVDD 0.8EVDD 0.7AVREF0 VDD - 0.5 EVSS EVSS AVSS VSS EVDD EVDD AVREF0 VDD 0.3EVDD 0.2EVDD 0.3AVREF0 0.4 V V V V V V V V 15 8 30 30 mA mA mA mA EVDD = 4.0 to 5.5 V EVDD = 2.7 to 5.5 V EVDD = 4.0 to 5.5 V EVDD = 2.7 to 5.5 V -30 -15 -30 -15 10 mA mA mA mA mA MIN. TYP. MAX. -5.0 Unit mA
Notes 1. P00, P01, P30, P41, P98, PCM0, PCM1, PDL0 to PDL7 and their alternate-function pins. 2. RESET, FLMD0, P02 to P06, P31 to P35, P38, P39, P40, P42, P50 to P55, P90, P91, P96, P97, P99, P913 to P915 and their alternate-function pins.
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DC Characteristics (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, VSS = EVSS = AVSS = 0 V) (2/3)
Parameter Output voltage, high Symbol VOH1 Note 1 Conditions IOH = -2.0 mA, EVDD = 4.0 to 5.5 V Note 2 IOH = -0.1 mA, EVDD = 2.7 to 5.5 V Output voltage, low VOL1 VOL2 Note 3 P38, P39 IOL = 2.0 mA IOL = 15 mA, EVDD = 4.0 to 5.5 V IOL = 8 mA, EVDD = 3.0 to 5.5 V IOL = 5 mA, EVDD = 2.7 to 5.5 V Input leakage current, high Input leakage current, low Output leakage current, high Output leakage current, low Pull-up resistor ILIH ILIL ILOH ILOL RL VIN = VDD VIN = 0 V VO = VDD VO = 0 V VIN = 0 V 10 30 3.0 -3.0 3.0 -3.0 100 0 1.0 V 0 1.0 V
Note 4
MIN. EVDD - 1.0 EVDD - 0.5 0 0
TYP.
MAX. EVDD
Unit V
EVDD
V
0.8 2.0
V V
A A A A
k
Notes 1. Total of P00 to P06, P30 to P35, P40 to P42 and their alternate-function pins: IOH = -30 mA, total of P50 to P55, P90, P91, P96 to P99, P913 to P915, PCM0, PCM1, PDL0 to PDL7 and their alternate-function pins: IOH = -30 mA. 2. Total of P00 to P06, P30 to P35, P40 to P42 and their alternate-function pins: IOH = -15 mA, total of P50 to P55, P90, P91, P96 to P99, P913 to P915, PCM0, PCM1, PDL0 to PDL7 and their alternate-function pins: IOH = -15 mA. 3. Total of P00 to P06, P30 to P35, P40 to P42 and their alternate-function pins: IOL = 30 mA, total of P38, P39, P50 to P55, P90, P91, P96 to P99, P913 to P915, PCM0, PCM1, PDL0 to PDL7 and their alternate-function pins: IOL = 30 mA. 4. Refer to IOL1 for IOL of P38 and P39.
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DC Characteristics (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, VSS = EVSS = AVSS = 0 V) (3/3)
Parameter Supply current
Note 1
Symbol IDD1
Conditions
MIN.
TYP.
Note 2
MAX.
Unit
Normal operation mode (all peripheral functions operating) fXX = 20 MHz (fX = 5 MHz) (in PLL mode) VDD = 5 V 10% fXX = 10 MHz (in clock-through mode) VDD = 3 V 10% 17 34 mA 51 70 mA
IDD2
HALT mode (all peripheral functions operating) fXX = 20 MHz (fX = 5 MHz) (in PLL mode) VDD = 5 V 10% fXX = 10 MHz (in clock-through mode) VDD = 3 V 10% 9 15 mA 25 38 mA
IDD3
IDLE mode (watch timer operating) fX = 5 MHz (when PLL mode off) VDD = 5 V 10% fX = 10 MHz (in clock-through mode) VDD = 3 V 10% 1.4 2.4 mA 1.8 2.9 mA
IDD4
Subclock operation mode (fXT = 32.768 kHz) Main oscillation stopped
240
400
A A
IDD5
Sub-IDLE mode (fXT = 32.768 kHz) Watch timer operating, main oscillation stopped
20
75
IDD6
STOP mode Subclock oscillating Subclock stopped (XT1 = VSS, PSMR.XTSTP bit = 1) Flash memory erase/write (TA = -40 to +85C) fXX = 20 MHz (fX = 5 MHz) (in PLL mode) VDD = 5 V 10% fXX = 10 MHz (in clock-through mode) VDD = 3 V 10% 17 34 mA 51 70 mA 15 0.1 60 30
A A
IDD7
Notes 1. Total current of VDD and EVDD (all ports stopped). AVREF0 is not included. 2. TYP. value of VDD is as follows. VDD = 5.0 V when VDD = 5 V 10% VDD = 3.0 V when VDD = 3 V 10% Remark fXX: Main clock frequency fX: Main clock oscillation frequency fXT: Subclock frequency
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Data Retention Characteristics STOP Mode (TA = -40 to +85C)
Parameter Data retention voltage STOP release signal input time Symbol VDDDR tDREL Conditions STOP mode MIN. 2.0 0 TYP. MAX. 5.5 Unit V
s
Caution Shifting to STOP mode and restoring from STOP mode must be performed within the rated operating range.
STOP mode setting Operating voltage lower limit VDD
STOP release signal input
VDDDR
tDREL
RESET (input)
STOP mode release interrupt (NMI, etc.) (Released by falling edge)
STOP mode release interrupt (NMI, etc.) (Released by rising edge)
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AC Characteristics
AC Test Input Measurement Points (VDD, AVREF0, EVDD)
VDD
VIH Measurement points VIL
VIH VIL
0V
AC Test Output Measurement Points
VOH Measurement points VOL
VOH VOL
Load Conditions
DUT (Device under measurement)
CL = 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
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CLKOUT Output Timing (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Parameter Output cycle High-level width Symbol tCYK tWKH <1> <2> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V Low-level width tWKL <3> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V Rise time tKR <4> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V Fall time tKF <5> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V Conditions MIN. 50 ns tCYK/2 - 17 tCYK/2 - 26 tCYK/2 - 17 tCYK/2 - 26 17 26 17 26 MAX. 30.6 s ns ns ns ns ns ns ns ns Unit
Clock Timing
<1> <2> <3>
CLKOUT (output)
<4>
<5>
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Basic Operation
(1) Reset/external interrupt timing (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Parameter RESET low-level width Symbol tWRSL1 tWRSL2 NMI high-level width NMI low-level width INTPn high-level width tWNIH tWNIL tWITH <87> <88> <89> <90> <91> Conditions Reset in power-on status Power-on reset Analog noise elimination Analog noise elimination n = 0 to 7 (analog noise elimination) n = 3 (when digital noise elimination selected) INTPn low-level width tWITL <92> n = 0 to 7 (analog noise elimination) n = 3 (when digital noise elimination selected) ADTRG high-level width tWADH <93> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V ADTRG low-level width tWADL <94> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V MIN. 2 2 1 1 600 Ni x tISMP + 200 600 Ni x tISMP + 200 T + 50 T + 100 T + 50 T + 100 MAX. Unit
s s s s
ns ns ns ns ns ns ns ns
Remarks 1. Ni: T:
Number of samplings set with the NFC.NFSTS bit A/D base clock cycle (fAD)
tISMP: Digital noise elimination sampling clock cycle of INTP3 pin 2. The above specification shows the pulse width that is accurately detected as a valid edge. If a pulse narrower than the above specification is input, therefore, it may also be detected as a valid edge.
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Reset/Interrupt
VDD <88> RESET (input) <87>
<89>/<91>/<93> NMI (input) INTPn (input) ADTRG (input)
<90>/<92>/<94>
Remark n = 0 to 7
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Timer Timing (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Parameter TI01 high-level width Symbol tTI0H <95> Conditions VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V TI01 low-level width tTI0L <96> VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V TI5m high-level width tTI5H <97> VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V TI5m low-level width tTI5L <98> VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V TIP0m high-level width tTIPH <99> VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V TIP0m low-level width tTIPL <100> VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V MIN. 2Tsmp0 + 100 2Tsmp0 + 200 2Tsmp0 + 100 2Tsmp0 + 200 50 100 50 100 np x Tsmpp + 100 np x Tsmpp + 200 np x Tsmpp + 100 np x Tsmpp + 200
Note 2 Note 1
MAX.
Unit ns ns ns ns ns ns ns ns ns ns ns ns
Note 1
Note 1
Note 1
Note 2
Note 2
Note 2
Notes 1. Tsmp0: Timer 0 count clock cycle However, Tsmp0 = 4/fXX when TI0n is used as an external clock. 2. np: Number of sampling clocks set by the PmNFC.PmNFSTS bit Tsmpp: Digital noise elimination sampling clock cycle of TIP0m pin If TIP00 is used as an external clock or an external clear, however, Tsmpp = 0 (digital noise is not eliminated). Remarks 1. m = 0, 1 2. The above specification shows the pulse width that is accurately detected as a valid edge. If a pulse narrower than the above specification is input, therefore, it may also be detected as a valid edge. Timer Input Timing
<95>/<97>/<99> TI01 (input) TI5m (input) TIP0m (input) <96>/<98>/<100>
Remark
m = 0, 1
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UART Timing (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Parameter Transmit rate ASCK0 frequency VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V Symbol Conditions MIN. MAX. 312.5 12 6 Unit kbps MHz MHz
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CSI0 Timing
(1) Master mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Parameter SCK0n cycle time tKCY1 Symbol <101> Conditions VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V SCK0n high-/low-level width SI0n setup time (to SCK0n) tKH1, tKL1 tSIK1 <102> <103> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V SI0n hold time (from SCK0n) tKSI1 <104> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V Delay time from SCK0n to SO0n output tKSO1 <105> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V MIN. 200 400 tKCY1/2 - 30 30 50 30 50 30 60 MAX. Unit ns ns ns ns ns ns ns ns ns
Remark n = 0, 1 (2) Slave mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Parameter SCK0n cycle time tKCY2 Symbol <101> Conditions VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V SCK0n high-/low-level width tKH2, tKL2 <102> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V SI0n setup time (to SCK0n) tSIK2 <103> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V SI0n hold time (from SCK0n) tKSI2 <104> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V Delay time from SCK0n to SO0n output tKSO2 <105> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V MIN. 200 400 45 90 30 60 30 60 50 100 MAX. Unit ns ns ns ns ns ns ns ns ns ns
Remark n = 0, 1
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(a) CSICn.CKPn, DAPn bits = 00 or 11
<101> <102> SCK0n (I/O) <102>
<103> <104> Hi-Z SI0n (input)
Input data
Hi-Z
<105>
SO0n (output)
Output data
(b) CSICn.CKPn, DAPn bits = 01 or 10
<101> <102> SCK0n (I/O) <102>
<103> <104> Hi-Z SI0n (input)
Input data
Hi-Z
<105>
SO0n (output)
Output data
Remark
n = 0, 1
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CHAPTER 23 ELECTRICAL SPECIFICATIONS (TARGET)
I2C Bus Mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, VSS = EVSS = AVSS = 0 V, CL = 50 pF)
Parameter Symbol Normal Mode MIN. SCL0 clock frequency Bus free time (Between start and stop conditions) Hold time
Note 1
High-Speed Mode MIN. 0 1.3 MAX. 400 -
Unit
MAX. 100 -
fCLK tBUF <111>
0 4.7
kHz
s s s s s s s
ns ns ns
tHD:STA tLOW tHIGH tSU:STA
<112> <113> <114> <115> <116>
4.0 4.7 4.0 4.7
- - - - - - - 1000 300 - - 400
0.6 1.3 0.6 0.6 - 0
Note 2
- - - - - 0.9
Note 3
SCL0 clock low-level width SCL0 clock high-level width Setup time for start/restart conditions Data hold time CBUS compatible master I C mode Data setup time SDA0 and SCL0 signal rise time SDA0 and SCL0 signal fall time Stop condition setup time Pulse width of spike suppressed by input filter Capacitance load of each bus line
2
tHD:DAT
5.0
Note 2
0 tSU:DAT tR tF tSU:STO tSP <117> <118> <119> <120> <121>
250 - - 4.0 - -
100
Note 4
-
Note 5
20 + 0.1Cb
300 300 - 50
20 + 0.1Cb 0.6 0 -
Note 5
s
ns
Cb
400
pF
Notes 1. At the start condition, the first clock pulse is generated after the hold time. 2. The system requires a minimum of 300 ns hold time internally for the SDA0 signal (at VIHmin. of SCL0 signal) in order to occupy the undefined area at the falling edge of SCL0. 3. If the system does not extend the SCL0 signal low hold time (tLOW), only the maximum data hold time (tHD:DAT) needs to be satisfied. 4. The high-speed mode I2C bus can be used in the normal-mode I2C bus system. In this case, set the highspeed mode I2C bus so that it meets the following conditions. * If the system does not extend the SCL0 signal's low state hold time: tSU:DAT 250 ns * If the system extends the SCL0 signal's low state hold time: Transmit the following data bit to the SDA0 line prior to the SCL0 line release (tRmax. + tSU:DAT = 1000 + 250 = 1250 ns: Normal mode I2C bus specification). 5. Cb: Total capacitance of one bus line (unit: pF)
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I2C Bus Mode
<113> <114> SCL0 (I/O) <119> <118> <112> <116> <117> <115> <112> <121> <120>
SDA0 (I/O) <111> Stop condition Start condition <118> <119> Restart condition Stop condition
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A/D Converter (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, VSS = EVSS = AVSS = 0 V)
Parameter Resolution Overall error
Note 1
Symbol
Conditions
MIN. 10
TYP. 10 0.2 0.3
MAX. 10 0.4 0.6 100 100 100 100 100 100 100 100 0.4 0.6 0.4 0.6 2.5 4.5 1.5 2.0
Unit bit %FSR %FSR
AINL
4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V
Conversion time
tCONV
4.5 AVREF0 5.5 V
High-speed mode Normal mode
3.0 14.0 4.8 14.0 6.0 17.0 14.0 17.0
s s s s s s s s
%FSR %FSR %FSR %FSR LSB LSB LSB LSB V mA
4.0 AVREF0 4.5 V
High-speed mode Normal mode
2.85 AVREF0 4.0 V
High-speed mode Normal mode
2.7 AVREF0 2.85 V
High-speed mode Normal mode
Zero-scale error
Note 1
Ezs
4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V
Full-scale error
Note 1
Efs
4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V
Non-linearity error
Note 2
ILE
4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V
Differential linearity error
Note 2
DLE
4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V
Analog input voltage AVREF0 current
VIAN IAREF0 When using A/D converter When not using A/D converter
Note 3
0 1.3 1.0
AVREF0 2.5 10
A
Notes 1. Excluding quantization error (0.05 %FSR). 2. Excluding quantization error (0.5 LSB). 3. ADM.ADCS bit = 0, ADM.ADCS2 bit = 0 Remark LSB: Least Significant Bit FSR: Full Scale Range
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Flash Memory Programming Characteristics (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, VSS = EVSS = AVSS = 0 V, CL = 50 pF) (1) Basic characteristics
Parameter Programming operation frequency Symbol Conditions VDD = 4.5 to 5.5 V VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V Supply voltage Number of rewrites Programming temperature VDD CERWR tPRG Note 1 Note 2 -40 MIN. 2 2 2 2.7 100 +85 TYP. MAX. 20 16 10 5.5 Unit MHz MHz MHz V Times C
Notes 1. When writing initially to shipped products, it is counted as one rewrite for both "erase to write" and "write only". Example (P: Write, E: Erase) Shipped product PEPEP: 3 rewrites Shipped product E PEPEP: 3 rewrites 2. These values may change after evaluation. (2) Serial write operation characteristics
Parameter Setup time from VDD to FLMD0 Time from RESET to FLMD0 pulse input start FLMD0 pulse high-/low-level width FLMD0 pulse rise time FLMD0 pulse fall time tPW tR tF <124> <125> <126> 10 100 50 50 Symbol tDP tRP <122> <123> Conditions MIN. 10 ms 66611.2/fX TYP. MAX. 3s s Unit
s
ns ns
Serial Write Operation Timing
VDD FLMD0
<122> FLMD1 0V
<124> <124>
<125> <126>
RESET <123>
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CHAPTER 24 PACKAGE DRAWING
64-PIN PLASTIC LQFP (10x10)
A B
48 49
33 32 S P
detail of lead end
C
D
T
R 64 1 F G H I
M
L U
17 16
Q
J
K S
ITEM A B C D F G H I J K L M N P Q R S T U
MILLIMETERS 12.00.2 10.00.2 10.00.2 12.00.2 1.25 1.25 0.220.05 0.08 0.5 (T.P.) 1.00.2 0.5 0.17 +0.03 -0.07 0.08 1.4 0.10.05 3 +4 -3 1.50.10 0.25 0.60.15 S64GB-50-8EU-2
N
NOTE
S
M
Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
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A.1 Conventions
(1) Register symbols used to describe operands
Register Symbol reg1 reg2 Explanation General-purpose registers: Used as source registers. General-purpose registers: Used mainly as destination registers. Also used as source register in some instructions. reg3 General-purpose registers: Used mainly to store the remainders of division results and the higher 32 bits of multiplication results. bit#3 immX dispX regID vector cccc sp ep listX 3-bit data for specifying the bit number X bit immediate data X bit displacement data System register number 5-bit data that specifies the trap vector (00H to 1FH) 4-bit data that shows the condition codes Stack pointer (r3) Element pointer (r30) X item register list
(2) Register symbols used to describe opcodes
Register Symbol R r w d I i cccc CCCC bbb L 1-bit data of a code that specifies reg1 or regID 1-bit data of the code that specifies reg2 1-bit data of the code that specifies reg3 1-bit displacement data 1-bit immediate data (indicates the higher bits of immediate data) 1-bit immediate data 4-bit data that shows the condition codes 4-bit data that shows the condition codes of Bcond instruction 3-bit data for specifying the bit number 1-bit data that specifies a program register in the register list Explanation
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(3) Register symbols used in operations
Register Symbol GR [ ] SR [ ] zero-extend (n) sign-extend (n) load-memory (a, b) store-memory (a, b, c) load-memory-bit (a, b) store-memory-bit (a, b, c) saturated (n) Input for General-purpose register System register Expand n with zeros until word length. Expand n with signs until word length. Read size b data from address a. Write data b into address a in size c. Read bit b of address a. Write c to bit b of address a. Execute saturated processing of n (n is a 2's complement). If, as a result of calculations, n 7FFFFFFFH, let it be 7FFFFFFFH. n 80000000H, let it be 80000000H. result Byte Halfword Word + - ll x / % AND OR XOR NOT logically shift left by logically shift right by arithmetically shift right by Reflects the results in a flag. Byte (8 bits) Halfword (16 bits) Word (32 bits) Addition Subtraction Bit concatenation Multiplication Division Remainder from division results Logical product Logical sum Exclusive OR Logical negation Logical shift left Logical shift right Arithmetic shift right Explanation
(4) Register symbols used in execution clock
Register Symbol i r l Explanation If executing another instruction immediately after executing the first instruction (issue). If repeating execution of the same instruction immediately after executing the first instruction (repeat). If using the results of instruction execution in the instruction immediately after the execution (latency).
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(5) Register symbols used in flag operations
Identifier (Blank) 0 X R No change Clear to 0 Set or cleared in accordance with the results. Previously saved values are restored. Explanation
(6) Condition codes
Condition Code (cccc) 0000 1000 0001 OV = 1 OV = 0 CY = 1 Overflow No overflow Carry Lower (Less than) 1001 CY = 0 No carry Not lower (Greater than or equal) 0010 1010 0011 1011 0100 1100 0101 1101 0110 1110 0111 1111 SAT = 1 (S xor OV) = 1 (S xor OV) = 0 ((S xor OV) or Z) = 1 ((S xor OV) or Z) = 0 Z=1 Z=0 (CY or Z) = 1 (CY or Z) = 0 S=1 S=0 - Zero Not zero Not higher (Less than or equal) Higher (Greater than) Negative Positive Always (Unconditional) Saturated Less than signed Greater than or equal signed Less than or equal signed Greater than signed Condition Formula Explanation
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APPENDIX A INSTRUCTION SET LIST
A.2 Instruction Set (in Alphabetical Order)
(1/6)
Mnemonic Operand Opcode Operation Execution Clock i ADD reg1,reg2 imm5,reg2 ADDI imm16,reg1,reg2 r r rr r0 01 11 0 RRRRR rrrrr010010iiiii r r rr r1 10 00 0 RRRRR iiiiiiiiiiiiiiii AND ANDI reg1,reg2 imm16,reg1,reg2 r r rr r0 01 01 0 RRRRR r r rr r1 10 11 0 RRRRR iiiiiiiiiiiiiiii Bcond disp9 ddddd1011dddcccc if conditions are satisfied Note 1 then PCPC+sign-extend(disp9) When conditions are satisfied When conditions are not satisfied BSH reg2,reg3 rrrrr11111100000 GR[reg3]GR[reg2] (23 : 16) ll GR[reg2] (31 : 24) ll 1 1 1 x x 0 x x x x 2 2 2 GR[reg2]GR[reg2]AND GR[reg1] GR[reg2]GR[reg1]AND zero-extend(imm16) 1 1 1 1 1 1 0 0 x x x x GR[reg2]GR[reg2]+GR[reg1] GR[reg2]GR[reg2]+sign-extend(imm5) GR[reg2]GR[reg1]+sign-extend(imm16) 1 1 1 r 1 1 1 l 1 1 1 CY OV S x x x x x x x x x Z SAT x x x Flags
Note 2 Note 2 Note 2
1
1
1
wwwww01101000010 GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) BSW reg2,reg3 rrrrr11111100000 GR[reg3]GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) ll GR 1 1 1 0
wwwww01101000000 [reg2] (23 : 16) ll GR[reg2] (31 : 24) CALLT imm6 0000001000iiiiii CTPCPC+2(return PC) CTPSWPSW adrCTBP+zero-extend(imm6 logically shift left by 1) PCCTBP+zero-extend(Load-memory(adr,Halfword)) CLR1 bit#3,disp16[reg1] 10bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot(Load-memory-bit(adr,bit#3)) Store-memory-bit(adr,bit#3,0) reg2,[reg1] r r rr r1 11 11 1 RRRRR 0000000011100100 adrGR[reg1] Z flagNot(Load-memory-bit(adr,reg2)) Store-memory-bit(adr,reg2,0) CMOV cccc,imm5,reg2,reg3 r r r r r 1 1 1 1 1 1 i i i i i wwwww011000cccc0 if conditions are satisfied then GR[reg3]sign-extended(imm5) else GR[reg3]GR[reg2] cccc,reg1,reg2,reg3 r r rr r1 11 11 1 RRRR if conditions are satisfied else GR[reg3]GR[reg2] CMP reg1,reg2 imm5,reg2 CTRET r r rr r0 01 11 1 RRRRR rrrrr010011iiiii 0000011111100000 0000000101000100 DBRET 0000011111100000 0000000101000110 resultGR[reg2]-GR[reg1] resultGR[reg2]-sign-extend(imm5) PCCTPC PSWCTPSW PCDBPC PSWDBPSW 3 3 3 R R R R R 1 1 3 1 1 3 1 1 3 x x R x x R x x R x x R R 1 1 1 1 1 1 3 3 3 x 3 3 3 x 4 4 4
Note 3 Note 3 Note 3
Note 3 Note 3 Note 3
wwwww011001cccc0 then GR[reg3]GR[reg1]
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Mnemonic Operand Opcode Operation Execution Clock i DBTRAP 1111100001000000 DBPCPC+2 (restored PC) DBPSWPSW PSW.NP1 PSW.EP1 PSW.ID1 PC00000060H DI 0000011111100000 0000000101100000 DISPOSE imm5,list12 0000011001iiiiiL LLLLLLLLLLL00000 spsp+zero-extend(imm5 logically shift left by 2) GR[reg in list12]Load-memory(sp,Word) spsp+4 repeat 2 steps above until all regs in list12 is loaded imm5,list12,[reg1] 0000011001iiiiiL spsp+zero-extend(imm5 logically shift left by 2) n+3 n+3 n+3
Note 4 Note 4 Note 4
Flags
r 3
l 3
CY OV S
Z SAT
3
PSW.ID1
1
1
1
n+1 n+1 n+1
Note 4 Note 4 Note 4
LLLLLLLLLLLRRRRR GR[reg in list12]Load-memory(sp,Word) Note 5 spsp+4 repeat 2 steps above until all regs in list12 is loaded PCGR[reg1] DIV reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR GR[reg2]GR[reg2]/GR[reg1]
35 35 35
x x x x x
x x x x x
x x x x x
wwwww01011000000 GR[reg3]GR[reg2]%GR[reg1] DIVH reg1,reg2 reg1,reg2,reg3 r r rr r0 00 01 0 RRRRR r r rr r1 11 11 1 RRRRR GR[reg2]GR[reg2]/GR[reg1]Note 6 GR[reg2]GR[reg2]/GR[reg1]
Note 6
35 35 35 35 35 35
wwwww01010000000 GR[reg3]GR[reg2]%GR[reg1] DIVHU reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR GR[reg2]GR[reg2]/GR[reg1]Note 6 34 34 34
wwwww01010000010 GR[reg3]GR[reg2]%GR[reg1] DIVU reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR GR[reg2]GR[reg2]/GR[reg1] 34 34 34
wwwww01011000010 GR[reg3]GR[reg2]%GR[reg1] EI 1000011111100000 0000000101100000 HALT 0000011111100000 0000000100100000 HSW reg2,reg3 rrrrr11111100000 wwwww01101000100 JARL disp22,reg2 rrrrr11110dddddd ddddddddddddddd0 Note 7 JMP JR [reg1] disp22 00000000011RRRRR PCGR[reg1] 0000011110dddddd ddddddddddddddd0 Note 7 LD.B disp16[reg1],reg2 r r rr r1 11 00 0 RRRRR dddddddddddddddd LD.BU disp16[reg1],reg2 r r rr r1 11 10 b RRRRR dddddddddddddd1 Notes 8, 10 adrGR[reg1]+sign-extend(disp16) GR[reg2]sign-extend(Load-memory(adr,Byte)) adrGR[reg1]+sign-extend(disp16) GR[reg2]zero-extend(Load-memory(adr,Byte)) 1 1 1 1
Note 11 Note 11
PSW.ID0
1
1
1
Stop
1
1
1
GR[reg3]GR[reg2](15 : 0) ll GR[reg2] (31 : 16)
1
1
1
x
0
x
x
GR[reg2]PC+4 PCPC+sign-extend(disp22)
2
2
2
3 2
3 2
3 2
PCPC+sign-extend(disp22)
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Mnemonic Operand Opcode Operation Execution Clock i LD.H disp16[reg1],reg2 rrrrr111001RRRRR ddddddddddddddd0 Note 8 LDSR reg2,regID rrrrr111111RRRRR 0000000000100000 Note 12 LD.HU disp16[reg1],reg2 r r rr r1 11 11 1 RRRRR ddddddddddddddd1 Note 8 LD.W disp16[reg1],reg2 r r rr r1 11 00 1 RRRRR ddddddddddddddd1 Note 8 MOV reg1,reg2 imm5,reg2 imm32,reg1 r r rr r0 00 00 0 RRRRR rrrrr010000iiiii GR[reg2]GR[reg1] GR[reg2]sign-extend(imm5) 1 1 2 1 1 2 1 1 2 adrGR[reg1]+sign-extend(disp16) GR[reg2]Load-memory(adr,Word) 1 1
Note 11
Flags
r 1
l
Note 11
CY OV S
Z SAT
adrGR[reg1]+sign-extend(disp16) GR[reg2]sign-extend(Load-memory(adr,Halfword))
1
SR[regID]GR[reg2]
Other than regID = PSW regID = PSW
1 1
1 1
1 1 x x x x x
adrGR[reg1]+sign-extend(disp16) GR[reg2]zero-extend(Load-memory(adr,Halfword)
1
1
Note 11
00000110001RRRRR GR[reg1]imm32 iiiiiiiiiiiiiiii IIIIIIIIIIIIIIII
MOVEA
imm16,reg1,reg2
r r rr r1 10 00 1 RRRRR iiiiiiiiiiiiiiii
GR[reg2]GR[reg1]+sign-extend(imm16)
1
1
1
MOVHI
imm16,reg1,reg2
r r rr r1 10 01 0 RRRRR iiiiiiiiiiiiiiii
GR[reg2]GR[reg1]+(imm16 ll 016)
1
1
1
MUL
reg1,reg2,reg3
r r rr r1 11 11 1 RRRRR
GR[reg3] ll GR[reg2]GR[reg2]xGR[reg1]
1
4
5
wwwww01000100000 Note 14 imm9,reg2,reg3 rrrrr111111iiiii wwwww01001IIII 00 Note 13 MULH reg1,reg2 imm5,reg2 MULHI imm16,reg1,reg2 r r rr r0 00 11 1 RRRRR rrrrr010111iiiii r r rr r1 10 11 1 RRRRR iiiiiiiiiiiiiiii MULU reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR GR[reg3] ll GR[reg2]GR[reg2]xGR[reg1] 1 4 5 GR[reg2]GR[reg2]Note 6xGR[reg1]Note 6 GR[reg2]GR[reg2] GR[reg2]GR[reg1]
Note 6
GR[reg3] ll GR[reg2]GR[reg2]xsign-extend(imm9)
1
4
5
1 1 1
1 1 1
2 2 2
xsign-extend(imm5) ximm16
Note 6
wwwww01000100010 Note 14 imm9,reg2,reg3 rrrrr111111iiiii wwwww01001IIII 10 Note 13 NOP NOT NOT1 reg1,reg2 bit#3,disp16[reg1] 0000000000000000 Pass at least one clock cycle doing nothing. r r rr r0 00 00 1 RRRRR GR[reg2]NOT(GR[reg1]) 1 1 3 1 1 3 1 1 3 0 x x x GR[reg3] ll GR[reg2]GR[reg2]xzero-extend(imm9) 1 4 5
01bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot(Load-memory-bit(adr,bit#3)) Store-memory-bit(adr,bit#3,Z flag)
Note 3 Note 3 Note 3
reg2,[reg1]
r r rr r1 11 11 1 RRRRR 0000000011100010
adrGR[reg1] Z flagNot(Load-memory-bit(adr,reg2)) Store-memory-bit(adr,reg2,Z flag)
3
3
3
x
Note 3 Note 3 Note 3
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Mnemonic Operand Opcode Operation Execution Clock i OR ORI reg1,reg2 imm16,reg1,reg2 r r rr r0 01 00 0 RRRRR r r rr r1 10 10 0 RRRRR iiiiiiiiiiiiiiii PREPARE list12,imm5 0000011110iiiiiL Store-memory(sp-4,GR[reg in list12],Word) repeat 1 step above until all regs in list12 is stored spsp-zero-extend(imm5) list12,imm5, sp/immNote 15 0000011110iiiiiL LLLLLLLLLLLff011 imm16/imm32 Store-memory(sp-4,GR[reg in list12],Word) spsp+4 repeat 1 step above until all regs in list12 is stored Note 16 spsp-zero-extend (imm5) epsp/imm RETI 0000011111100000 if PSW.EP=1 0000000101000000 then PC EIPC PSW EIPSW else if PSW.NP=1 then else PC PC FEPC EIPC x x x x x x PSW FEPSW PSW EIPSW SAR reg1,reg2 r r rr r1 11 11 1 RRRRR 0000000010100000 imm5,reg2 rrrrr010101iiiii GR[reg2]GR[reg2]arithmetically shift right by GR[reg1] GR[reg2]GR[reg2]arithmetically shift right by zero-extend (imm5) SASF cccc,reg2 rrrrr1111110cccc 0000001000000000 if conditions are satisfied then GR[reg2](GR[reg2]Logically shift left by 1) OR 00000001H else GR[reg2](GR[reg2]Logically shift left by 1) OR 00000000H SATADD reg1,reg2 imm5,reg2 SATSUB SATSUBI reg1,reg2 imm16,reg1,reg2 r r rr r0 00 11 0 RRRRR rrrrr010001iiiii r r rr r0 00 10 1 RRRRR r r rr r1 10 01 1 RRRRR iiiiiiiiiiiiiiii SATSUBR reg1,reg2 SETF cccc,reg2 r r rr r0 00 10 0 RRRRR rrrrr1111110cccc 0000000000000000 GR[reg2]saturated(GR[reg1]-GR[reg2]) If conditions are satisfied then GR[reg2]00000001H else GR[reg2]00000000H 1 1 1 1 1 1 x x x x x GR[reg2]saturated(GR[reg2]+GR[reg1]) GR[reg2]saturated(GR[reg2]+sign-extend(imm5)) GR[reg2]saturated(GR[reg2]-GR[reg1]) GR[reg2]saturated(GR[reg1]-sign-extend(imm16)) 1 1 1 1 1 1 1 1 1 1 1 1 x x x x x x x x x x x x x x x x x x x x 1 1 1 1 1 1 0 1 1 1 0
Note17 Note17 Note17
Flags
r 1 1
l 1 1
CY OV S 0 0 x x
Z SAT x x
GR[reg2]GR[reg2]OR GR[reg1] GR[reg2]GR[reg1]OR zero-extend(imm16)
1 1
n+1 n+1 n+1
Note 4 Note 4 Note 4
LLLLLLLLLLL00001 spsp-4
n+2 n+2 n+2
Note 4 Note 4 Note 4
3
3
3
R
R
R
R
R
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APPENDIX A INSTRUCTION SET LIST
(5/6)
Mnemonic Operand Opcode Operation Execution Clock i SET1 bit#3,disp16[reg1] 00bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot (Load-memory-bit(adr,bit#3)) Store-memory-bit(adr,bit#3,1) reg2,[reg1] r r rr r1 11 11 1 RRRRR 0000000011100000 adrGR[reg1] Z flagNot(Load-memory-bit(adr,reg2)) Store-memory-bit(adr,reg2,1) SHL reg1,reg2 r r rr r1 11 11 1 RRRRR 0000000011000000 imm5,reg2 rrrrr010110iiiii GR[reg2]GR[reg2] logically shift left by zero-extend(imm5) SHR reg1,reg2 r r rr r1 11 11 1 RRRRR 0000000010000000 imm5,reg2 rrrrr010100iiiii GR[reg2]GR[reg2] logically shift right by zero-extend(imm5) SLD.B disp7[ep],reg2 rrrrr0110ddddddd adrep+zero-extend(disp7) GR[reg2]sign-extend(Load-memory(adr,Byte)) SLD.BU disp4[ep],reg2 r r r r r 0 0 0 0 1 1 0 d d d d adrep+zero-extend(disp4) Note 18 GR[reg2]zero-extend(Load-memory(adr,Byte)) SLD.H disp8[ep],reg2 r r r r r 1 0 0 0 d d d d d d d adrep+zero-extend(disp8) Note 19 GR[reg2]sign-extend(Load-memory(adr,Halfword)) SLD.HU disp5[ep],reg2 r r r r r 0 0 0 0 1 1 1 d d d d adrep+zero-extend(disp5) Notes 18, 20 GR[reg2]zero-extend(Load-memory(adr,Halfword)) SLD.W disp8[ep],reg2 r r r r r 1 0 1 0 d d d d d d 0 adrep+zero-extend(disp8) Note 21 GR[reg2]Load-memory(adr,Word) SST.B reg2,disp7[ep] rrrrr0111ddddddd adrep+zero-extend(disp7) Store-memory(adr,GR[reg2],Byte) SST.H reg2,disp8[ep] r r r r r 1 0 0 1 d d d d d d d adrep+zero-extend(disp8) Note 19 Store-memory(adr,GR[reg2],Halfword) SST.W reg2,disp8[ep] r r r r r 1 0 1 0 d d d d d d 1 adrep+zero-extend(disp8) Note 21 Store-memory(adr,GR[reg2],Word) ST.B reg2,disp16[reg1] r r rr r1 11 01 0 RRRRR dddddddddddddddd ST.H reg2,disp16[reg1] adrGR[reg1]+sign-extend(disp16) Store-memory(adr,GR[reg2],Byte) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Note 9
Flags
r 3
l 3
CY OV S
Z SAT x
3
Note 3 Note 3 Note 3
3
3
3
x
Note 3 Note 3 Note 3
GR[reg2]GR[reg2] logically shift left by GR[reg1]
1
1
1
x x x x
0
x x x x
x x x x
1
1
1
0
GR[reg2]GR[reg2] logically shift right by GR[reg1]
1
1
1
0
1
1
1
0
1
1
Note 9
1
1
Note 9
1
1
Note 9
1
1
Note 9
r r rr r1 11 01 1 RRRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd0 Store-memory (adr,GR[reg2], Halfword) Note 8
ST.W
reg2,disp16[reg1]
rrrrr111011RRRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd1 Store-memory (adr,GR[reg2], Word) Note 8
1
1
1
STSR
regID,reg2
r r rr r1 11 11 1 RRRRR 0000000001000000
GR[reg2]SR[regID]
1
1
1
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APPENDIX A INSTRUCTION SET LIST
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Mnemonic Operand Opcode Operation Execution Clock i SUB SUBR SWITCH reg1,reg2 reg1,reg2 reg1 r r rr r0 01 10 1 RRRRR r r rr r0 01 10 0 RRRRR GR[reg2]GR[reg2]-GR[reg1] GR[reg2]GR[reg1]-GR[reg2] 1 1 5 r 1 1 5 l 1 1 5 CY OV S x x x x x x Z SAT x x Flags
00000000010RRRRR adr(PC+2) + (GR [reg1] logically shift left by 1) PC(PC+2) + (sign-extend (Load-memory (adr,Halfword)) logically shift left by 1
SXB
reg1
00000000101RRRRR GR[reg1]sign-extend (GR[reg1] (7 : 0))
1
1
1
SXH
reg1
00000000111RRRRR GR[reg1]sign-extend (GR[reg1] (15 : 0))
1
1
1
TRAP
vector
00000111111iiiii 0000000100000000
EIPC EIPSW PSW.EP PSW.ID PC
PC+4 (Restored PC) PSW 1 1 00000040H (when vector is 00H to 0FH) 00000050H (when vector is 10H to 1FH)
3
3
3
ECR.EICC Interrupt code
TST TST1
reg1,reg2 bit#3,disp16[reg1]
r r rr r0 01 01 1 RRRRR
resultGR[reg2] AND GR[reg1]
1 3
1 3
1 3
0
x
x x x
11bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot (Load-memory-bit (adr,bit#3)) adrGR[reg1] Z flagNot (Load-memory-bit (adr,reg2)) GR[reg2]GR[reg2] XOR GR[reg1] GR[reg2]GR[reg1] XOR zero-extend (imm16)
Note 3 Note 3 Note 3
reg2, [reg1]
r r rr r1 11 11 1 RRRRR 0000000011100110
3
3
3
Note 3 Note 3 Note 3
XOR XORI
reg1,reg2 imm16,reg1,reg2
r r rr r0 01 00 1 RRRRR r r rr r1 10 10 1 RRRRR iiiiiiiiiiiiiiii
1 1
1 1
1 1
0 0
x x
x x
ZXB ZXH
reg1 reg1
00000000100RRRRR GR[reg1]zero-extend (GR[reg1] (7 : 0)) 00000000110RRRRR GR[reg1]zero-extend (GR[reg1] (15 : 0))
1 1
1 1
1 1
Notes 1. 2. 3. 4. 5. 6. 7. 8. 9.
dddddddd: Higher 8 bits of disp9. 3 if there is an instruction that rewrites the contents of the PSW immediately before. If there is no wait state (3 + the number of read access wait states). n is the total number of list12 load registers. (According to the number of wait states. Also, if there are no wait states, n is the total number of list12 registers. If n = 0, same operation as when n = 1) RRRRR: other than 00000. The lower halfword data only are valid. ddddddddddddddddddddd: The higher 21 bits of disp22. ddddddddddddddd: The higher 15 bits of disp16. According to the number of wait states (1 if there are no wait states).
10. b: bit 0 of disp16. 11. According to the number of wait states (2 if there are no wait states).
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APPENDIX A INSTRUCTION SET LIST
Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic description and in the opcode differs from other instructions. rrrrr = regID specification RRRRR = reg2 specification 13. i i i i i : Lower 5 bits of imm9. I I I I : Higher 4 bits of imm9. 14. Do not specify the same register for general-purpose registers reg1 and reg3. 15. sp/imm: specified by bits 19 and 20 of the sub-opcode. 16. ff = 00: Load sp in ep. 01: Load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: Load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: Load 32-bit immediate data (bits 63 to 32) in ep. 17. If imm = imm32, n + 3 clocks. 18. r r r r r : Other than 00000. 19. ddddddd: Higher 7 bits of disp8. 20. dddd: Higher 4 bits of disp5. 21. dddddd: Higher 6 bits of disp8.
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APPENDIX B REGISTER INDEX
(1/6)
Symbol ADCR ADCRH ADIC ADM ADS ASIF0 ASIF1 ASIM0 ASIM1 ASIS0 ASIS1 BRGC0 BRGC1 BRGIC CKSR0 CKSR1 CMP00 CMP01 CMP10 CMP11 CR010 CR011 CR5 CR50 CR51 CRC01 CSI0IC0 CSI0IC1 CSIC0 CSIC1 CSIM00 CSIM01 CTBP CTPC CTPSW DBPC DBPSW ECR EIPC EIPSW A/D conversion result register A/D conversion result register H Interrupt control register A/D converter mode register Analog input channel specification register Asynchronous serial interface transmit status register 0 Asynchronous serial interface transmit status register 1 Asynchronous serial interface mode register 0 Asynchronous serial interface mode register 1 Asynchronous serial interface status register 0 Asynchronous serial interface status register 1 Baud rate generator control register 0 Baud rate generator control register 1 Interrupt control register Clock select register 0 Clock select register 1 8-bit timer H compare register 00 8-bit timer H compare register 01 8-bit timer H compare register 10 8-bit timer H compare register 11 16-bit timer capture/compare register 010 16-bit timer capture/compare register 011 16-bit timer compare register 5 8-bit timer compare register 50 8-bit timer compare register 51 Capture/compare control register 01 Interrupt control register Interrupt control register Clocked serial interface clock selection register 0 Clocked serial interface clock selection register 1 Clocked serial interface mode register 00 Clocked serial interface mode register 01 CALLT base pointer CALLT execution status saving register CALLT execution status saving register Exception/debug trap status saving register Exception/debug trap status saving register Interrupt source register Interrupt status saving register Interrupt status saving register Name Unit ADC ADC INTC ADC ADC UART UART UART UART UART UART UART UART INTC UART UART TMH TMH TMH TMH TM0 TM0 TM5 TM5 TM5 TM0 INTC INTC CSI0 CSI0 CSI0 CSI0 CPU CPU CPU CPU CPU CPU CPU CPU Page 365 365 533 361 364 391 391 388 388 390 390 409 409 533 408 408 306 307 306 307 218 219 288 288 288 224 533 533 421 421 419 419 41 40 40 41 41 38 37 37
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APPENDIX B REGISTER INDEX
(2/6)
Symbol FEPC FEPSW IIC0 IICC0 IICCL0 IICF0 IICIC0 IICS0 IICX0 IMR0 IMR0H IMR0L IMR1 IMR1H IMR1L IMR3 IMR3L INTF0 INTF3 INTF9H INTR0 INTR3 INTR9H ISPR KRIC KRM NFC OSTS P0 P0NFC P1NFC P3 P3H P3L P4 P5 P7 P9 P9H P9L PC PCC PCM NMI status saving register NMI status saving register IIC shift register 0 IIC control register 0 IIC clock selection register 0 IIC flag register 0 Interrupt control register IIC status register 0 IIC function expansion register 0 Interrupt mask register 0 Interrupt mask register 0H Interrupt mask register 0L Interrupt mask register 1 Interrupt mask register 1H Interrupt mask register 1L Interrupt mask register 3 Interrupt mask register 3L External interrupt falling edge specification register 0 External interrupt falling edge specification register 3 External interrupt falling edge specification register 9H External interrupt rising edge specification register 0 External interrupt rising edge specification register 3 External interrupt rising edge specification register 9H In-service priority register Interrupt control register Key return mode register Digital noise elimination control register Oscillation stabilization time selection register Port 0 register TIP00 noise elimination control register TIP01 noise elimination control register Port 3 register Port 3 register H Port 3 register L Port 4 register Port 5 register Port 7 register Port 9 register Port 9 register H Port 9 register L Program counter Processor clock control register Port CM register Name Unit CPU CPU IC IC IC IC INTC IC IC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC KR INTC Standby Port TMP TMP Port Port Port Port Port Port Port Port Port CPU CG Port
2 2 2 2 2 2
Page 38 38 460 447 457 455 534 452 458 535 535 535 535 535 535 535 535 542 543 544 542 543 544 536 533 557 540 563 70 213 213 73 73 73 78 80 83 85 85 85 35 121 90
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APPENDIX B REGISTER INDEX
(3/6)
Symbol PDL PF3H PF4 PF9H PFC3 PFC5 PFC9 PFC9H PFC9L PFCE3 PFM PFT PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 PIC7 PLLCTL PM0 PM3 PM3H PM3L PM4 PM5 PM9 PM9H PM9L PMC0 PMC3 PMC3H PMC3L PMC4 PMC5 PMC9 PMC9H PMC9L PMCCM PMCM PMDL PRCMD Port DL register Port 3 function register H Port 4 function register Port 9 function register H Port 3 function control register Port 5 function control register Port 9 function control register Port 9 function control register H Port 9 function control register L Port 3 function control expansion register Power fail comparison mode register Power fail comparison threshold register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register PLL control register Port 0 mode register Port 3 mode register Port 3 mode register H Port 3 mode register L Port 4 mode register Port 5 mode register Port 9 mode register Port 9 mode register H Port 9 mode register L Port 0 mode control register Port 3 mode control register Port 3 mode control register H Port 3 mode control register L Port 4 mode control register Port 5 mode control register Port 9 mode control register Port 9 mode control register H Port 9 mode control register L Port CM mode control register Port CM mode register Port DL mode register Command register Name Unit Port Port Port Port Port Port Port Port Port Port ADC ADC INTC INTC INTC INTC INTC INTC INTC INTC CG Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port CPU Page 93 75 79 87 75 82 88 88 88 75 367 367 533 533 533 533 533 533 533 533 126, 356 70 73 73 73 78 80 85 85 85 71 74 74 74 79 81 86 86 86 90 90 93 58
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APPENDIX B REGISTER INDEX
(4/6)
Symbol PRM01 PRSCM PRSM PSC PSMR PSW PU0 PU3 PU4 PU5 PU9 PU9H PU9L PUCM PUDL r0 to r31 RTBH0 RTBL0 RTPC0 RTPM0 RXB0 RXB1 SELCNT1 SIO00 SIO00L SIO01 SIO01L SIRB0 SIRB0L SIRB1 SIRB1L SIRBE0 SIRBE0L SIRBE1 SIRBE1L SOTB0 SOTB0L SOTB1 SOTB1L SOTBF0 SOTBF0L SOTBF1 SOTBF1L Prescaler mode register 01 Interval timer BRG compare register Interval timer BRG mode register Power save control register Power save mode register Program status word Pull-up resistor option register 0 Pull-up resistor option register 3 Pull-up resistor option register 4 Pull-up resistor option register 5 Pull-up resistor option register 9 Pull-up resistor option register 9H Pull-up resistor option register 9L Pull-up resistor option register CM Pull-up resistor option register DL General-purpose registers Real-time output buffer register H0 Real-time output buffer register L0 Real-time output port control register 0 Real-time output port mode register 0 Receive buffer register 0 Receive buffer register 1 Selector operation control register 1 Serial I/O shift register 0 Serial I/O shift register 0L Serial I/O shift register 1 Serial I/O shift register 1L Clocked serial interface receive buffer register 0 Clocked serial interface receive buffer register 0L Clocked serial interface receive buffer register 1 Clocked serial interface receive buffer register 1L Clocked serial interface read-only receive buffer register 0 Clocked serial interface read-only receive buffer register 0L Clocked serial interface read-only receive buffer register 1 Clocked serial interface read-only receive buffer register 1L Clocked serial interface transmit buffer register 0 Clocked serial interface transmit buffer register 0L Clocked serial interface transmit buffer register 1 Clocked serial interface transmit buffer register 1L Clocked serial interface initial transmit buffer register 0 Clocked serial interface initial transmit buffer register 0L Clocked serial interface initial transmit buffer register 1 Clocked serial interface initial transmit buffer register 1L Name Unit TM0 CG CG Standby Standby CPU Port Port Port Port Port Port Port Port Port CPU RTP RTP RTP RTP UART UART TM0 CSI0 CSI0 CSI0 CSI0 CSI0 CSI0 CSI0 CSI0 CSI0 CSI0 CSI0 CSI0 CSI0 CSI0 CSI0 CSI0 CSI0 CSI0 CSI0 CSI0 Page 227 331 330 561 562 39 71 77 79 82 89 89 89 91 93 35 350 350 352 351 392 392 228 426 426 426 426 422 422 422 422 423 423 423 423 424 424 424 424 425 425 425 425
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APPENDIX B REGISTER INDEX
(5/6)
Symbol SREIC0 SREIC1 SRIC0 SRIC1 STIC0 STIC1 SVA0 SYS TCL50 TCL51 TM01 TM0IC10 TM0IC11 TM5 TM50 TM51 TM5IC0 TM5IC1 TMC01 TMC50 TMC51 TMCYC0 TMCYC1 TMHIC0 TMHIC1 TMHMD0 TMHMD1 TOC01 TP0CCIC0 TP0CCIC1 TP0CCR0 TP0CCR1 TP0CNT TP0CTL0 TP0CTL1 TP0IOC0 TP0IOC1 TP0IOC2 TP0OPT0 TP0OVIC TXB0 TXB1 VSWC Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Slave address register 0 System status register Timer clock selection register 50 Timer clock selection register 51 16-bit timer counter 01 Interrupt control register Interrupt control register 16-bit timer counter 5 8-bit timer counter 50 8-bit timer counter 51 Interrupt control register Interrupt control register 16-bit timer mode control register 01 8-bit timer mode control register 50 8-bit timer mode control register 51 8-bit timer H carrier control register 0 8-bit timer H carrier control register 1 Interrupt control register Interrupt control register 8-bit timer H mode register 0 8-bit timer H mode register 1 16-bit timer output control register 01 Interrupt control register Interrupt control register TMP0 capture/compare register 0 TMP0 capture/compare register 1 TMP0 counter read buffer register TMP0 control register 0 TMP0 control register 1 TMP0 I/O control register 0 TMP0 I/O control register 1 TMP0 I/O control register 2 TMP0 option register 0 Interrupt control register Transmit buffer register 0 Transmit buffer register 1 System wait control register Name Unit INTC INTC INTC INTC INTC INTC IC CPU TM5 TM5 TM0 INTC INTC TM5 TM5 TM5 INTC INTC TM0 TM5 TM5 TMH TMH INTC INTC TMH TMH TM0 INTC INTC TMP TMP TMP TMP TMP TMP TMP TMP TMP INTC UART UART CPU
2
Page 533 533 533 533 533 533 460 58 289 289 218 533 533 287 287 287 533 533 222 290 290 311 311 533 533 308 308 225 533 533 137 139 141 131 132 133 134 135 136 533 393 393 59
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APPENDIX B REGISTER INDEX
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Symbol WDCS WDT1IC WDTE WDTM1 WDTM2 WTIC WTIIC WTM Name Watchdog timer clock selection register Interrupt control register Watchdog timer enable register Watchdog timer mode register 1 Watchdog timer mode register 2 Interrupt control register Interrupt control register Watch timer operation mode register Unit WDT INTC WDT WDT WDT INTC INTC WT Page 341 533 347 342, 538 346 533 533 334
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